KR100536627B1 - Method for fabricating gate oxide of semiconductor device - Google Patents
Method for fabricating gate oxide of semiconductor device Download PDFInfo
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- KR100536627B1 KR100536627B1 KR10-2003-0102070A KR20030102070A KR100536627B1 KR 100536627 B1 KR100536627 B1 KR 100536627B1 KR 20030102070 A KR20030102070 A KR 20030102070A KR 100536627 B1 KR100536627 B1 KR 100536627B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
- H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
본 발명은 반도체 소자의 게이트 산화막 형성방법에 관한 것으로, 보다 자세하게는 일산화질소를 과도하게 열처리하여 질화산화막을 형성하고 식각함으로써 고농도의 균일한 질소 분포를 얻을 수 있어 보론의 침투를 효과적으로 방지할 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a gate oxide film of a semiconductor device, and more particularly, to form a nitrogen oxide film by excessive heat treatment of nitrogen monoxide to form a high concentration of nitrogen to obtain a uniform nitrogen distribution can effectively prevent the penetration of boron It is about a method.
본 발명의 반도체 소자의 게이트 산화막 형성방법은 실리콘 기판의 상부에 소정 두께의 산화막을 형성하는 단계; 상기 산화막을 포함하는 기판을 질소를 포함한 가스 분위기에서 열처리하는 단계; 상기 열처리된 산화막을 최종적으로 원하는 두께로 식각하는 단계; 및 상기 산화막의 상부에 소정 구조의 게이트를 형성하는 단계로 이루어짐에 기술적 특징이 있다.A method of forming a gate oxide film of a semiconductor device of the present invention includes forming an oxide film having a predetermined thickness on an upper surface of a silicon substrate; Heat-treating the substrate including the oxide film in a gas atmosphere including nitrogen; Finally etching the heat-treated oxide film to a desired thickness; And forming a gate having a predetermined structure on the oxide film.
따라서, 본 발명의 반도체 소자의 게이트 산화막 형성방법은 일산화질소를 과도하게 열처리하여 질화산화막을 형성하고 식각함으로써 고농도의 균일한 질소분포를 얻을 수 있어 보론의 침투를 효과적으로 방지할 수 있는 효과가 있다.Therefore, the method of forming a gate oxide film of the semiconductor device of the present invention can obtain a high concentration of uniform nitrogen distribution by excessively heat-treating nitrogen monoxide to form a nitride oxide film and etching, thereby effectively preventing the penetration of boron.
Description
본 발명은 반도체 소자의 게이트 산화막 형성방법에 관한 것으로, 보다 자세하게는 일산화질소(NO)로 과도하게 열처리하여 질화산화막을 형성하고 식각함으로써 고농도의 균일한 질소분포를 얻을 수 있어 보론(Boron)의 침투(penetration)를 효과적으로 방지할 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a gate oxide film of a semiconductor device, and more particularly, to form a nitrogen oxide film by excessive heat treatment with nitrogen monoxide (NO) and to etch to obtain a uniform nitrogen distribution of high concentration, so that boron penetration It is about a method which can effectively prevent (penetration).
현재, 논리 소자(logic device) 또는 메모리와 논리 소자를 하나의 칩으로 만든 MML(merged memory on logic) 소자 등은 이중 게이트 산화막 구조를 채택하고 있다. 실리콘 산화막(SiO2)을 근간으로 하는 이중 게이트 산화막의 통상적인 형성 방법은 두꺼운 게이트 산화막과 얇은 게이트 산화막을 형성하기 위하여 장시간의 습식 또는 건식 산화 공정을 각각 실시하고 있으며, 포토리소그래피 공정과 식각 공정 역시 각각 추가로 진행되고 있다. 이는 전통적인 습식 산화 방법 이외에 게이트 산화막을 위한 양질의 실리콘 산화막 형성 방법이 없기 때문이다. 결국, 이중 게이트 산화막을 형성하는 방법은 단일 게이트 산화막을 형성하는 것에 비하여 공정 추가에 따른 비용 상승을 초래하게 된다.Currently, a logic device or a merged memory on logic (MML) device in which a memory and a logic device are formed as one chip employs a double gate oxide film structure. The conventional method of forming a double gate oxide film based on a silicon oxide film (SiO 2 ) is to perform a long time wet or dry oxidation process in order to form a thick gate oxide film and a thin gate oxide film, and the photolithography process and the etching process are also performed. Each is going further. This is because there is no high quality silicon oxide film formation method for gate oxides other than the traditional wet oxidation method. As a result, the method of forming the double gate oxide film results in an increase in cost due to the addition of the process compared to forming the single gate oxide film.
한편, 얇은 게이트 산화막을 형성하기 위한 기존의 방법은 습식 또는 건식 산화 공정의 진행 후 일산화질소(NO) 열처리 단계를 추가로 진행하여 질화산화막을 형성한다. 질화산화막은 소자 구동시 유발되는 핫 캐리어 효과(hot carrier effect) 및 후속 열처리에 의한 보론의 침투를 방지하기 위한 것이다. 보다 자세하게는 이중 게이트 전극을 사용하는 PMOS(p-type metal-oxide-semiconductor) 소자의 경우에는 게이트 산화막의 두께가 30Å 이하인 저전압 영역에서 폴리실리콘에 이온주입된 보론이 상기 얇은 게이트 산화막을 침투하여 채널영역으로 유입될 수 있다. 이것을 방지하기 위하여 게이트 산화막에 질소를 주입하는 열처리 단계를 거쳐 질화산화막을 형성하게 된다. Meanwhile, the conventional method for forming a thin gate oxide film further proceeds with a nitric oxide (NO) heat treatment step after the wet or dry oxidation process to form an oxide nitride film. The nitride oxide film is intended to prevent the penetration of boron by the hot carrier effect and subsequent heat treatment caused when driving the device. More specifically, in the case of a p-type metal-oxide-semiconductor (PMOS) device using a double gate electrode, boron ion-implanted with polysilicon penetrates the thin gate oxide film in a low voltage region having a gate oxide thickness of 30 kΩ or less. Can enter the area. In order to prevent this, a nitride oxide film is formed through a heat treatment step of injecting nitrogen into the gate oxide film.
종래의 질화산화막을 형성하기 위한 기술에서는 고온의 퍼니스(furnace)에서 열산화에 의해 산화막을 형성한 후 일산화질소 또는 아산화질소(N2O)의 분위기에서 열처리를 하여 질소를 주입하게 된다. 하지만 높은 열적 대류에 의해 주입된 질소는 산화막과 실리콘의 계면에 모이게 되어 농도의 불균일이 발생한다. 이러한 질소 농도의 불균일로 인해 균일한 농도 분포를 보이는 산화막에 비해 보론의 침투를 방지하는 효과가 떨어지게 된다. 또한 과도한 열처리는 산화막 표면의 산소를 해리시키고, 상기 해리된 산소에 의해 산화막 표면에서 국부적인 산화가 진행되면서 부식성과 반응성이 강한 일산화질소에 의해 게이트 산화막의 표면이 거칠어져서 열화하는 문제가 발생한다.In the conventional technique for forming an oxide film of the nitride oxide, the oxide film is formed by thermal oxidation in a furnace at a high temperature, followed by heat treatment in an atmosphere of nitrogen monoxide or nitrous oxide (N 2 O) to inject nitrogen. However, the nitrogen injected by the high thermal convection collects at the interface between the oxide film and the silicon, resulting in uneven concentration. Due to such non-uniformity of nitrogen concentration, the effect of preventing penetration of boron is inferior to that of an oxide film having a uniform concentration distribution. In addition, excessive heat treatment dissociates oxygen on the surface of the oxide film, and local oxidation proceeds on the surface of the oxide film by the dissociated oxygen, thereby causing a problem that the surface of the gate oxide film is roughened by the nitrogen monoxide which is highly corrosive and reactive, resulting in deterioration.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 일산화질소로 과도하게 열처리하여 질화산화막을 형성하고 식각함으로써 고농도의 균일한 질소분포를 얻을 수 있어 보론의 침투를 효과적으로 방지할 수 있는 방법을 제공함에 본 발명의 목적이 있다. Therefore, the present invention is to solve the problems of the prior art as described above, by forming a heat treatment with nitrogen monoxide excessively to form a nitride oxide film and etching to obtain a uniform nitrogen distribution of high concentration can effectively prevent the penetration of boron. It is an object of the present invention to provide a method.
본 발명의 상기 목적은 실리콘 기판의 상부에 소정 두께의 산화막을 형성하는 단계; 상기 산화막을 포함하는 기판을 질소를 포함한 가스 분위기에서 열처리하는 단계; 상기 열처리된 산화막을 최종적으로 원하는 두께로 식각하는 단계; 및 상기 산화막의 상부에 소정 구조의 게이트를 형성하는 단계로 이루어진 반도체 소자의 게이트 산화막 형성방법에 의해 달성된다.The object of the present invention is to form an oxide film having a predetermined thickness on top of a silicon substrate; Heat-treating the substrate including the oxide film in a gas atmosphere including nitrogen; Finally etching the heat-treated oxide film to a desired thickness; And forming a gate having a predetermined structure on the oxide film.
먼저, 퍼니스 장치에서 최종적으로 원하는 산화막의 두께보다 더 두껍게 산화막을 형성한다. 이후 일산화질소 또는 아산화질소의 분위기에서 열처리를 행한다. 이때 산화막은 600℃ 이상의 온도에서 H2/O2를 사용하여 형성하며, 이후 NO 또는 N2O 가스를 600℃ 이상의 온도에서 100sccm 이상으로 흘려주면서, 30분 이상 열처리를 행한다.First, in the furnace apparatus, an oxide film is finally formed thicker than the thickness of the desired oxide film. Thereafter, heat treatment is performed in an atmosphere of nitrogen monoxide or nitrous oxide. At this time, the oxide film is formed using H 2 / O 2 at a temperature of 600 ° C. or higher, and then heat treatment is performed for 30 minutes or more, while flowing NO or N 2 O gas at 100 sccm or higher at a temperature of 600 ° C. or higher.
이와 같은 과도한 열처리에 의해 고농도의 질소층이 산화막과 실리콘의 계면에서 소정의 높이만큼 확산하게 된다. 이때 질소의 확산은 처음 산화막을 종래보다 그리고 최종적으로 원하는 두께보다 두껍게 하였으므로 그만큼 확산길이가 증가하게 된다. 상기 열처리와 질소의 확산에 의해 산화막은 질화산화막으로 바뀌게 된다. Due to such excessive heat treatment, a high concentration of nitrogen layer diffuses by a predetermined height at the interface between the oxide film and silicon. At this time, the diffusion of nitrogen first made the oxide film thicker than conventionally and finally to a desired thickness, thereby increasing the diffusion length. The oxide film is changed into a nitride oxide film by the heat treatment and diffusion of nitrogen.
이후 희석된 불산(HF) 용액으로 산화막을 소정 두께만큼 습식식각하여 고농도의 질소를 가진 산화질화막을 형성하고, 과도한 열처리에 의해 산화막의 표면에 형성된 표면거칠기를 제거한다. 이때 불산 식각액은 불산과 탈이온수를 200 : 1 이상으로 희석하여 준비하고, 균일한 습식식각이 가능하도록 초기 산화막의 두께를 예정된 높이에 5Å을 추가하여 성장한다.Thereafter, the oxide film is wet-etched by a predetermined thickness with a hydrofluoric acid (HF) solution to form an oxynitride film having a high concentration of nitrogen, and the surface roughness formed on the surface of the oxide film is removed by excessive heat treatment. At this time, the hydrofluoric acid etchant is prepared by diluting the hydrofluoric acid and deionized water to 200: 1 or more, and grows the thickness of the initial oxide layer by adding 5 k to the predetermined height so as to enable uniform wet etching.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
이하 도면을 참조하여 설명하면 다음과 같다.A description with reference to the drawings as follows.
도 1은 종래의 기술에 비해 산화막의 두께를 더 두껍게 형성하여 NO 열처리를 실시한 후의 두께에 따른 질소농도의 분포를 보여주는 도면이다. 왼쪽에는 기판의 상부에 산화막(20)이 종래의 두께(점선, 10)보다 더 두껍게 형성된 모습을 보여주는 단면도이고, 오른쪽에는 NO 가스 열처리를 실시한 후에 질소의 농도 분포를 보여주는 그래프이다. 실리콘 기판과 질화산화막의 계면영역에서 질소농도가 가장 높고, 계면에서 멀어질수록 농도가 점차적으로 감소함을 알 수 있다.1 is a view showing the distribution of the nitrogen concentration according to the thickness after the NO heat treatment by forming a thicker oxide film than the prior art. The left side is a cross-sectional view showing the oxide film 20 formed on the upper portion of the substrate thicker than the conventional thickness (dotted line, 10), the right side is a graph showing the concentration distribution of nitrogen after the NO gas heat treatment. It can be seen that the nitrogen concentration is highest in the interface region of the silicon substrate and the nitride oxide film, and the concentration gradually decreases as the distance from the interface increases.
도 2는 상기 열처리가 완료된 질화산화막을 식각한 후의 질소농도의 분포를 보여주는 도면이다. 왼쪽에는 상기 열처리된 질화산화막(30)을 원하는 두께만큼 식각한 후의 질화산화막(40)의 단면도이고, 오른쪽에는 식각한 후의 질소농도의 분포를 보여주는 그래프이다. 상기 식각에 의해 질소의 농도가 낮은 윗부분이 제거되어 전체적으로 질소의 농도가 높으면서도 균일한 분포를 하고 있음을 알 수 있다.FIG. 2 is a view showing a distribution of nitrogen concentration after etching the nitride oxide film after the heat treatment. On the left is a cross-sectional view of the nitride oxide film 40 after etching the heat-treated nitrided oxide film 30 to a desired thickness, and on the right is a graph showing the distribution of nitrogen concentration after etching. The etching removes the upper portion of the low nitrogen concentration, it can be seen that the overall concentration of the nitrogen while having a uniform distribution.
또한 상술한 바와 같이 고농도의 균질한 산화질화막을 얻기 위해 식각공정을 실시함으로써, 과도한 열처리시 발생한 표면의 거칠기도 동시에 제거하여 게이트의 특성저하를 방지할 수 있다.In addition, by performing an etching process to obtain a high concentration of homogeneous oxynitride film as described above, it is possible to simultaneously remove the roughness of the surface generated during excessive heat treatment, thereby preventing the deterioration of the gate characteristics.
이후 게이트 폴리실리콘을 증착하고 패터닝하는 등의 공지된 트랜지스터 제조공정이 이어진다.This is followed by known transistor manufacturing processes such as depositing and patterning gate polysilicon.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 게이트 산화막 형성방법은 일산화질소를 과도하게 열처리하여 질화산화막을 형성하고 식각함으로써 고농도의 균일한 질소분포를 얻을 수 있어 보론의 침투를 효과적으로 방지할 수 있는 효과가 있다. Therefore, the method of forming a gate oxide film of the semiconductor device of the present invention can obtain a high concentration of uniform nitrogen distribution by excessively heat-treating nitrogen monoxide to form a nitride oxide film and etching, thereby effectively preventing the penetration of boron.
도 1 내지 도 2는 본 발명에 의한 게이트 산화막 형성방법의 단면도 및 농도 분포도.1 to 2 are cross-sectional views and concentration distribution diagrams of the gate oxide film forming method according to the present invention.
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