KR19980060883A - Device isolation insulating film formation method of semiconductor device - Google Patents
Device isolation insulating film formation method of semiconductor device Download PDFInfo
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- KR19980060883A KR19980060883A KR1019960080250A KR19960080250A KR19980060883A KR 19980060883 A KR19980060883 A KR 19980060883A KR 1019960080250 A KR1019960080250 A KR 1019960080250A KR 19960080250 A KR19960080250 A KR 19960080250A KR 19980060883 A KR19980060883 A KR 19980060883A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Abstract
본 발명은 반도체 소자의 소자분리절연막 형성방법에 관한 것으로, 반도체기판 상부에 패드절연막과 제 1 절연막을 형성하고 상기 제 1 절연막과 패드절연막 그리고 일정 두께의 반도체기판을 식각하여 트렌치를 형성한 다음, 상기 트렌치를 포함한 전체 표면 상부에 실리콘막을 형성하고 상기 실리콘막을 산화시켜 열산화막을 형성한 다음, 상기 열산화막을 플라즈마 처리하고 상기 트렌치를 매립하는 제 2 절연막을 형성하는 공정으로 완전히 트렌치를 매립하되 균일하고 재현성을 갖는 소자분리절연막을 형성함으로써 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, wherein a pad insulating film and a first insulating film are formed on a semiconductor substrate, and the trench is formed by etching the first insulating film, the pad insulating film, and a semiconductor substrate having a predetermined thickness. A silicon film is formed over the entire surface including the trench, and the silicon film is oxidized to form a thermal oxide film. Then, the thermal oxide film is plasma-processed to form a second insulating film filling the trench. And forming a device isolation insulating film having reproducibility, thereby facilitating subsequent processes, thereby improving the characteristics and reliability of the semiconductor device and thereby enabling high integration of the semiconductor device.
Description
따라서, 본 발명은 상기한 종래 기술의 문제점을 해결하기 위하여, 트렌치 형성공정후 트렌치 표면에 산화막을 형성하고 플라즈마 처리한 다음, 상기 트렌치를 매립하여 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체 소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, an oxide film is formed on the surface of the trench after the trench formation process and plasma treatment, and then the trench is embedded to facilitate the subsequent process to improve the characteristics and reliability of the semiconductor device. It is an object of the present invention to provide a method for forming a device isolation insulating film of a semiconductor device that can be improved.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 소자분리절연막 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11, 41 : 반도체기판13, 43 : 패드산화막11, 41: semiconductor substrate 13, 43: pad oxide film
15, 45 : 질화막17, 47 : 트렌치15, 45: nitride film 17, 47: trench
19 : 실리콘막21 : 열산화막19 silicon film 21 thermal oxide film
23 : N2/NH2플라즈마25 : 플라즈마처리된 열산화막23 N 2 / NH 2 plasma 25 Plasma treated thermal oxide film
27 : O3-TEOS USG49 : 산화막27: O 3 -TEOS USG49: oxide film
ⓐ : 턱짐현상Ⓐ: Jaw load phenomenon
본 발명은 반도체 소자의 소자분리절연막 형성방법에 관한 것으로, 특히 반도체 소자의 소자 분리 기술의 하나인 얕은 트렌치를 형성하고 이를 매립하는 소자분리방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation insulating film of a semiconductor device, and more particularly, to a device isolation method of forming a shallow trench, which is one of the device isolation technologies of a semiconductor device, and filling it.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역(isolation region)의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices in terms of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. In terms of size, the device isolation technology is a technology for determining the memory cell size.
소자분리절연막을 제조하는 종래 기술로는 절연물 분리방식의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS라 함) 방법, 실리콘기판 상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. (Poly - Buffed LOCOS, 이하에서 PBL이라 함) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치(trench) 방법 등이 있다.Conventional methods for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method of insulating material isolation, LOCOS, polycrystalline silicon layer, and nitride film on silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL), a trench method in which a groove is formed in a substrate and then embedded with an insulating material.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.
그리고, 상기 PBL을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판 내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-described PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 소자분리절연막 형성방법을 도시한 단면도로서, 트렌치를 형성하고 이를 매립하는 소자분리방법으로 턱짐현상이 발생되는 경우를 도시한다.1A to 1C are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the related art, and illustrate a case in which a jaw phenomenon occurs in a device isolation method of forming a trench and filling the trench.
먼저, 반도체기판(41) 상부에 패드산화막(43)을 형성하고, 상기 패드산화막(43) 상부에 질화막(45)을 형성한다.First, a pad oxide film 43 is formed on the semiconductor substrate 41, and a nitride film 45 is formed on the pad oxide film 43.
그리고, 소자분리마스크(도시안됨)을 이용한 식각공정으로 상기 질화막(45)과 패드산화막(43) 및 일정 두께의 반도체기판(41)을 식각하여 상기 반도체기판(41)에 트렌치(37)를 형성한다.In addition, the trench 37 is formed in the semiconductor substrate 41 by etching the nitride layer 45, the pad oxide layer 43, and the semiconductor substrate 41 having a predetermined thickness by an etching process using an element isolation mask (not shown). do.
그 다음에, 상기 트렌치(47)를 매립하는 산화막(49)을 형성하고, 상기 산화막(49)을 CMP 하여 상부면을 평탄하게 형성한다. (도 1a)Next, an oxide film 49 filling the trench 47 is formed, and the oxide film 49 is CMP to form a flat upper surface. (FIG. 1A)
그리고, 상기 질화막(45)을 제거한다. 이때, 상기 질화막(45)은 인산용액을 이용한 습식방법으로 제거한다. (도 1b)Then, the nitride film 45 is removed. At this time, the nitride film 45 is removed by a wet method using a phosphoric acid solution. (FIG. 1B)
그 다음에, 상기 패드산화막(43)을 제거하는 습식세정공정을 실시하고, 상기 패드산화막(43)이 제거된 반도체기판(41) 상부에 게이트산화막(도시안됨)을 형성하기 위하여 습식세정공정을 실시한다.Then, a wet cleaning process is performed to remove the pad oxide film 43, and a wet cleaning process is performed to form a gate oxide film (not shown) on the semiconductor substrate 41 from which the pad oxide film 43 is removed. Conduct.
이때, 상기 산화막(49)과 반도체기판(41)의 경계부에 위치한 상기 산화막(49)이 상기 트렌치(47) 안쪽으로 ⓐ와 같이 식각되는 턱짐현상이 발생하여 후속공정을 어렵게 할 뿐만 아니라 반도체기판의 누설전류를 유발시킴으로써 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. (도 1c)At this time, the oxidization film 49 located at the boundary between the oxide film 49 and the semiconductor substrate 41 is etched into the trench 47 as shown by ⓐ, thereby making the subsequent process difficult, as well as the semiconductor substrate. By inducing leakage current, there is a problem in that the characteristics and reliability of the semiconductor device are lowered, thereby making it difficult to integrate the semiconductor device. (FIG. 1C)
여기서, 상기 도 1a의 트렌치(47) 형성공정시 상기 패드산화막(43)의 일부분이 측면식각되어 상기 트렌치(47)에 산화막(49)을 매립하는 공정시 완전한 매립을 형성할 수 없어 후속공정을 어렵게 한다.Here, in the process of forming the trench 47 of FIG. 1A, a part of the pad oxide film 43 is laterally etched to form a complete filling in the process of embedding the oxide film 49 in the trench 47. Makes it difficult.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 소자분리절연막 형성방법은, 반도체기판 상부에 패드절연막과 제 1 절연막을 형성하는 공정과, 상기 제 1 절연막과 패드절연막 그리고 일정 두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과, 상기 트렌치를 포함한 전체 표면 상부에 실리콘막을 형성하는 공정과, 상기 실리콘막을 산화시켜 열산화막을 형성하는 공정과, 상기 열산화막을 플라즈마 처리하는 공정과, 상기 트렌치를 매립하는 제 2 절연막을 형성하는 공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a device isolation insulating film of a semiconductor device according to the present invention includes forming a pad insulating film and a first insulating film on an upper surface of the semiconductor substrate, and forming the first insulating film, the pad insulating film, and a semiconductor substrate having a predetermined thickness. Etching to form a trench; forming a silicon film over the entire surface including the trench; oxidizing the silicon film to form a thermal oxide film; and plasma treating the thermal oxide film; And a step of forming a buried second insulating film.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, O3-TEOS USG를 매립 절연막으로 증착할 때 증착을 정상적으로 하기 위하여 트렌치 표면을 하나의 재료로 만들어 주기 위하여, 표면에 실리콘막을 증착하고 이를 산화시켜 산화막을 형성한 다음, N2/NH2플라즈마 처리를 균일하게 하고 후속 O3-TEOS USG를 증착하여 상기 트렌치를 균일하고 재현성 있게 매립할 수 있도록 한다. 또한, 후속 공정 진행시 매립된 절연막이 손실되는 문제를 단차피복성이 우수한 실리콘막을 트렌치 표면에 형성하고 이를 산화시켜 막질을 치밀하게 형성하는 것이다.On the other hand, the principle of the present invention for achieving the above object is to deposit a silicon film on the surface and to oxidize it in order to make the trench surface as a single material for the normal deposition when the O 3 -TEOS USG is deposited as a buried insulating film To form an oxide film, and then uniformize the N 2 / NH 2 plasma treatment and deposit the subsequent O 3 -TEOS USG so as to uniformly and reproducibly fill the trench. In addition, the problem that the buried insulating film is lost during the subsequent process is to form a silicon film having excellent step coverage on the trench surface and oxidize it to form a film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 패드산화막(13), 질화막(15)을 순차적으로 형성한다. 이때, 상기 패드산화막(13)은 50 ~ 200Å 정도의 두께로 증착하고, 상기 질화막(15)은 1500 ~ 2500Å 정도의 증착한다.First, the pad oxide film 13 and the nitride film 15 are sequentially formed on the semiconductor substrate 11. At this time, the pad oxide film 13 is deposited to a thickness of about 50 ~ 200Å, the nitride film 15 is deposited to about 1500 ~ 2500Å.
그 다음에, 소자분리마스크를 이용한 식각공정으로 트렌치(17)를 형성한다.Next, the trench 17 is formed by an etching process using an element isolation mask.
그리고, 상기 트렌치(17)의 측벽의 산화시켜 산화막(도시안됨)을 형성한다. 이때, 상기 산화막은 트렌치 형성공정시 발생되는 응력 및 결함을 제거하기 위하여 100 ~ 200Å 정도의 두께로 형성한다.In addition, an oxide layer (not shown) is formed by oxidizing sidewalls of the trench 17. At this time, the oxide film is formed to a thickness of about 100 ~ 200Å in order to remove the stress and defects generated during the trench forming process.
그 다음에, 상기 산화막을 습식방법으로 제거하여 상기 트렌치 형성시 발생한 결함 및 오염을 제거한다. 이때, 상기 패드산화막(13)이 일부 측면식각된다. (도 2a)Then, the oxide film is removed by a wet method to remove defects and contamination generated during the trench formation. In this case, the pad oxide layer 13 is partially etched. (FIG. 2A)
그리고, 상기 트렌치(17)의 표면을 포함한 전체 표면 상부에 실리콘막(19)을 일정 두께 형성한다. 이때, 상기 실리콘막(19)은 폴리실리콘이나 비정질 실리콘으로 형성한다.The silicon film 19 is formed to have a predetermined thickness on the entire surface including the trench 17. In this case, the silicon film 19 is made of polysilicon or amorphous silicon.
여기서, 상기 실리콘막(19)을 폴리실리콘으로 형성하는 경우는 50 ~ 200Å 정도의 두께로 형성하되, SiH4또는 Si2H6가스를 사용하며, 600 ~ 800℃ 정도의 온도, 100 ~ 500 mTorr 정도의 압력에서 형성한다.In this case, when the silicon film 19 is formed of polysilicon, it is formed to a thickness of about 50 ~ 200Å, using SiH 4 or Si 2 H 6 gas, temperature of about 600 ~ 800 ℃, 100 ~ 500 mTorr Form at a pressure of degree.
그리고, 상기 실리콘막(19)을 상기 비정질 실리콘으로 형성하는 경우는 50 ~ 200Å 정도의 두께로 증착하되, Si2H6가스를 사용하며 450 ~ 600℃ 정도의 온도, 100 ~ 500 mTorr 정도의 압력에서 형성한다. (도 2b)When the silicon film 19 is formed of the amorphous silicon, the silicon film 19 is deposited to a thickness of about 50 to 200 kPa, using Si 2 H 6 gas, a temperature of about 450 to 600 ° C., and a pressure of about 100 to 500 mTorr. Form from. (FIG. 2B)
그 다음에, 상기 실리콘막(19)을 열산화시켜 열산화막(21)을 형성한다. 이때, 상기 열산화공정은 수소 및 산소를 혼합한 습식 산화 방법을 이용하여 형성한다. (도 2c)Then, the silicon film 19 is thermally oxidized to form a thermal oxide film 21. In this case, the thermal oxidation process is formed using a wet oxidation method in which hydrogen and oxygen are mixed. (FIG. 2C)
그리고, 열산화막(21)을 N2/NH2플라즈마 처리(23)를 실시한다. 이때, 상기 플라즈마 처리공정은 N2/NH3가스를 각각 1 ~ 3 SLM / 3 ~ 10 SLM의 유량, HF / LF를 각각 0.1 ~ 1.0 kW / 0.1 ~ 1.0 kw 정도의 전력, 300 ~ 400℃ 정도의 온도, 1.0 ~ 3.0 Torr 정도의 압력, 50 ~ 200초 정도의 시간으로 한다. (2d)Then, the thermal oxidation film 21 is subjected to N 2 / NH 2 plasma treatment 23. At this time, the plasma treatment process is N 2 / NH 3 gas flow rate of 1 ~ 3 SLM / 3 ~ 10 SLM, HF / LF of 0.1 ~ 1.0 kW / 0.1 ~ 1.0 kw, respectively, about 300 ~ 400 ℃ At a temperature of about 1.0 to 3.0 Torr and a time of about 50 to 200 seconds. (2d)
그 다음에, 상기 플라즈마 처리된 열산화막(23)이 형성된 반도체기판(11) 상부에 상기 트렌치(17)를 매립할 수 있는 O3-TEOS USG 막(27)을 형성한다. 이때, 상기 O3-TEOS USG 막(27)은 고밀도 플라즈마 산화막으로 대신 형성할 수도 있다.Next, an O 3 -TEOS USG film 27 capable of filling the trench 17 is formed on the semiconductor substrate 11 on which the plasma oxide thermal oxide film 23 is formed. In this case, the O 3 -TEOS USG film 27 may be formed instead of a high density plasma oxide film.
여기서, 상기 O3-TEOS USG 막(27)의 증착 조건은, N215 ~ 25 SLM, TEOS 플로우 N21 ~ 3 SLM, 350 ~ 450 ℃ 정도의 온도, O3농도 100 ~ 150g/㎥ 정도 조건에서 6000Å ~ 8000Å 정도의 두께로 형성한다.Here, the deposition conditions of the O 3 -TEOS USG film 27 is N 2 15-25 SLM, TEOS flow N 2 1-3 SLM, temperature of about 350 ~ 450 ℃, O 3 concentration of about 100 ~ 150g / ㎥ Under the conditions, form a thickness of about 6000Å ~ 8000.
또한, 고밀도 플라즈마 산화막을 형성하는 경우는, SiH4와 산소의 혼합가스를 이용하며 50 ~ 100 sccm 정도의 가스유량으로 하고, 온도 600 ~ 700 ℃ 정도, 압력 1 ~ 100 mTorr 정도, 플라즈마 발생 전력 1000 ~ 3000 와트, 기판에 인가되는 바이어스 전력은 500 ~ 2000 와트 정도의 조건에서 5000 ~ 8000Å 정도의 두께로 형성한다. (도 2e)In the case of forming a high-density plasma oxide film, a mixed gas of SiH 4 and oxygen is used to set a gas flow rate of about 50 to 100 sccm, a temperature of about 600 to 700 ° C., a pressure of about 1 to 100 mTorr, and a plasma generating power of 1000. ~ 3000 watts, the bias power applied to the substrate is formed to a thickness of 5000 ~ 8000 에서 under the conditions of 500 ~ 2000 watts. (FIG. 2E)
위와 같은 방법으로 상기 트렌치(17)를 매립하고 CMP 및 후속 공정을 완료하여 소자분리절연막을 형성한다.The trench 17 is buried in the same manner as above, and the device isolation insulating film is formed by completing the CMP and subsequent processes.
이상에서 설명한 바와 같이 본 발명에 따른 반도체 소자의 소자분리절연막 형성방법은, 트렌치를 완전히 매립하되 균일하게 재현성을 가지고 함으로써 후속공정을 용이하게 하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과가 있다.As described above, the method of forming a device isolation insulating film of the semiconductor device according to the present invention facilitates the subsequent process by filling the trench completely and having uniform reproducibility, thereby improving the characteristics and reliability of the semiconductor device and thereby It has the effect of enabling high integration.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20020071063A (en) * | 2001-03-02 | 2002-09-12 | 삼성전자 주식회사 | Dent free trench isolation structure and method for fabricating the same |
| KR100639182B1 (en) * | 2000-12-21 | 2006-10-31 | 매그나칩 반도체 유한회사 | Method for isolating semiconductor devices |
| KR100873357B1 (en) * | 2002-10-31 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
| WO2013048872A1 (en) * | 2011-09-26 | 2013-04-04 | Applied Materials, Inc. | Pretreatment and improved dielectric coverage |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0823027A (en) * | 1994-07-07 | 1996-01-23 | Nippondenso Co Ltd | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100639182B1 (en) * | 2000-12-21 | 2006-10-31 | 매그나칩 반도체 유한회사 | Method for isolating semiconductor devices |
| KR20020071063A (en) * | 2001-03-02 | 2002-09-12 | 삼성전자 주식회사 | Dent free trench isolation structure and method for fabricating the same |
| KR100873357B1 (en) * | 2002-10-31 | 2008-12-10 | 매그나칩 반도체 유한회사 | Method for forming the Isolation Layer of Semiconductor Device |
| WO2013048872A1 (en) * | 2011-09-26 | 2013-04-04 | Applied Materials, Inc. | Pretreatment and improved dielectric coverage |
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