JPH0629410A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To make the detection of end points of etching easy when etching a silicon oxide film and a coating glass, to suppress the diffusion of impurity in the coating glass, and to suppress the generation of voids in a passivation film by forming a silicon nitride film between the silicon oxide film and the coating glass. CONSTITUTION:A silicon oxide film 5 having been treated for gaseous phase growth is formed on a wiring layer. Next, silicon nitride film 11 is multi-layered, and organic or inorganic coating glass 9 is spin-coated for annealing. Then, the spin-coated glass is collected in a flat, stepped, or grooved section on a metallic wiring area, and then the wiring area is dry-etched to remove the spin-coated glass from the wiring area. In this case, since the silicon nitride film 11 is multi-layered between the coating glass 9 and the silicon oxide film 5, end points of the etching can be discriminated by monitoring a plasma emitting wavelength. Accordingly, flattening of the metallic wiring layer insulating film 5 can be well reproduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to improving the flatness of an insulating film on wiring, the reproducibility of flattening, and the improvement of electrical characteristics and moisture resistance. is there.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device will be described with reference to FIG. 5. For example, a CM having a two-layer wiring structure using an Al alloy.
The OS-LSI is made of an Al alloy or the like by forming a contact hole in a field insulating film 1 in which a silicon oxide film is laminated by selective oxidation or vapor phase growth of a silicon substrate surface on which semiconductor elements such as MOS transistors and resistors are formed. First
The metal wiring 2 is applied. Next, as an interlayer insulating film, SiH ₄
500 nm to 800 nm of the first silicon oxide film 5 which is obtained by plasma-reacting an oxidizing gas such as O ₂ and N ₂ O with plasma.
From the necessity of flattening in a vapor phase growth and further in the miniaturization structure, a coating glass 9 in which silanol and P ₂ O ₅ etc. are dissolved in an alcohol is spin-coated to cause no problem in the first metal wiring. Anneal at temperature. At this time, P ₂ O ₅ mixed in the coated glass has a concentration of 1 to ₅ mol% in order to improve the stress relaxation and the crack resistance effect of the coated glass thin film. Next, a high frequency bias is applied to dry-etch the coated glass to remove at least the first coated glass on the first metal wiring region. If the coated glass remains on the first metal wiring, the coated glass is etched at a high rate by the wet etching for opening the through holes because the coated glass has a high etch rate, and side etching occurs. is there. Further, since the coated glass contains P ₂ O ₅ , corrosion will be a problem if it directly contacts the metal wiring. Therefore, after vapor-depositing the second silicon oxide film 6 to a thickness of about 150 nm, The silicon oxide film on the first metal wiring is anisotropically dry-etched using CHF ₃ , CF ₄ and He gas to form through holes, and then the second metal wiring 3 of Al alloy is formed. , And SiH ₄
By plasma-reacting NH ₃ and NH ₃ with N 2 carrier, a plasma silicon nitride film having a thickness of about 1000 nm is vapor-phase grown as the passivation film 12, and finally a bonding pad portion is opened to take out the electrode to the outside.

[0003]

However, in the prior art, first, when the coating glass 9 and the first silicon oxide film 5 are etched back by a predetermined amount, both compositions are SiO _2. It is difficult to detect the end point, and the etching amount has been controlled only by time.However, when the end point is controlled by time, the etching rate of the coated glass is considerably higher than that of the vapor-phase grown silicon oxide film, so the etching back amount, It is difficult to obtain flatness with good reproducibility, which has been a problem in securing stable supply and reliability of the semiconductor device. Secondly, in the structure of the semiconductor device according to the prior art, the impurities in the coated glass diffuse into the element region and the wiring region through the oxide film, resulting in instability of electrical characteristics and corrosion of the wiring. Was a problem. Third, even in the passivation film 12, the second
Since the step due to the metal wiring is large, the void 13 is generated, and the passivation film is extremely thin in the void, which is a problem in terms of moisture resistance.

However, the present invention solves the above problems, and it is easy to detect the end point when the silicon oxide film and the coated glass are etched back by forming a silicon nitride film between the silicon oxide film and the coated glass. At the same time, it is intended to suppress the diffusion of impurities in the coated glass and the generation of voids in the passivation film, and to stably supply the semiconductor device and improve the reliability.

[0005]

According to a method of manufacturing a semiconductor device of the present invention, in a semiconductor device having a multilayer wiring structure, at least a step of forming a vapor-phase reacted silicon oxide film on a wiring layer, The method is characterized by comprising a step of forming a nitride film, a step of spin-coating coated glass, and a step of etching back a predetermined thickness of the laminated insulating film.

Further, in a semiconductor device having a multilayer wiring structure, (a) a vapor-phase-reacted first silicon oxide film, (b) a silicon nitride film, at least on the first wiring layer,
(C) coated glass, (d) second silicon oxide film, second
The wiring layers are sequentially stacked.

Further, in a semiconductor device having a multi-layer wiring structure, (a) a first silicon oxide film, (b) a silicon nitride film, (c) coated glass, on at least a metal wiring layer,
(D) A silicon nitride film is sequentially laminated.

[0008]

1 (a) to 1 (c) are schematic cross-sectional views of processes for explaining one embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. When applied to a Si gate CMOS-LSI having a two-layer wiring structure using an Al alloy, M
A contact hole is formed in the field insulating film 1 in which a silicon oxide film is laminated by selective oxidation or vapor phase growth on the surface of a silicon substrate on which semiconductor elements such as OS transistors and resistors are formed, and a barrier metal and 0.5% Cu are formed. Including Al
The alloy 2 and TiN to be the antireflection film 4 are laminated by sputtering, and then the laminated film is selectively etched by a dry etcher using Cl ₂ and BCl ₃ gas so that the total thickness is 700 nm.
The first metal wiring of Next, as an interlayer insulating film, first, TEOS [Si (OC ₂ H ₅ ) ₄ ] and O 2 were subjected to plasma vapor phase reaction at 380 ° C. and about 9 torr to form a first silicon oxide film 5 of 550 nm. Next, SiH ₄ and NH ₃
Was subjected to a plasma reaction at 360 ° C. at about 6 torr, and a silicon nitride film 11 having a thickness of 50 nm was laminated. Subsequently, spin coating of the organic or inorganic coated glass 9 followed by annealing for 30 minutes in an N ₂ atmosphere at about 450 ° C., a flat portion on the first metal wiring region of about 5 nm to 70 nm, a step portion or a step portion. The coated glass having a thickness of about 300 nm is accumulated in the groove.
Next, in a Ar atmosphere of about 200 mtorr, a C ₂ F ₆ gas is used and a high frequency bias of 800 W is applied to perform dry etching to remove at least the first coated glass on the first metal wiring region. In the step of removing the coated glass 9, since the silicon nitride film 11 is laminated between the coated glass 9 and the first silicon oxide film 5, the end point can be determined by monitoring the plasma emission wavelength. It will be possible. At this time, the silicon nitride film on the flat portion of the step is removed at the same time, but it may be left as it is. Then 15
After vapor-depositing the second silicon oxide film 6 with a thickness of 0 nm, CHF ₃ , CF ₄ and He gas are used to 300 mto.
The silicon oxide film on the first metal wiring was anisotropically dry-etched by a pressure of rr to form a 0.5 μm square through hole, and at the same time, the antireflection film in the hole was also removed.
Then, the same Al alloy 3 as the first metal wiring is deposited to 800 nm.
Then, TiN is sputter-grown at a thickness of 50 nm as the antireflection film 4, the laminated film is selectively etched to form a second metal wiring, and SiH ₄ and N are formed as a passivation film 12.
H ₃ was plasma-reacted with N ₂ carrier to form a plasma nitride film having a thickness of 1000 nm, and finally a bonding pad portion was opened to take out the electrode to the outside.

In the semiconductor device thus manufactured, the flattening of the metal wiring interlayer insulating film can be performed with good reproducibility, and as a result, the covering property of the second metal wiring is stable, and the electrical characteristics and long-term reliability are improved. It was possible to improve the sex. Further, this manufacturing method can be applied not only to the metal wiring layers but also to the polysilicon wiring layers, the polysilicon wiring-metal wiring layers, and the passivation structure, and the same effect can be obtained. Furthermore, FIG. 1 (C)
In the semiconductor device having the structure like the above, since the silicon nitride film is interposed between the coated glass and the silicon oxide film, the diffusion of impurities in the coated glass can be prevented, so that the electrical characteristics are stable and the long-term The reliability was improved. Such a wiring interlayer structure can be applied not only to the metal wiring layers but also to the polysilicon wiring layers and the polysilicon-metal wiring layers, and the same effect can be obtained.

Next, another embodiment of another semiconductor device according to the present invention will be described with reference to FIG. The structure as shown in FIG. 2 is manufactured by the following steps. A contact hole is formed in the field insulating film 1 in which a silicon oxide film is stacked by selective oxidation or vapor phase growth on the surface of a silicon substrate on which semiconductor elements such as MOS transistors and resistors are formed, and a barrier metal and 0.5% Cu are formed. The Al alloy 2 containing and TiN to be the antireflection film 4 are laminated by sputtering, and then the laminated film is selectively etched by a dry etcher using Cl ₂ and BCl ₃ gas to form a first film having a total thickness of 700 nm.
The metal wiring of. Next, as an interlayer insulating film, SiH ₄
500 nm to 800 nm of the first silicon oxide film 5 which is obtained by plasma-reacting an oxidizing gas such as O ₂ and N ₂ O with plasma.
Vapor phase growth to a certain extent, and further, the necessity of flattening in a fine structure, or spin coating of organic or inorganic coated glass 9,
Anneal at a temperature that does not interfere with the first metal wiring. Subsequently, a C ₂ F ₆ gas was used in an Ar atmosphere, and a high frequency bias of 800 W was applied to perform dry etching to remove at least the first coated glass on the first metal wiring region. next,
After vapor-depositing the second silicon oxide film 6 to a thickness of 150 nm, CHF ₃ , CF ₄ and He gas are used for 300 m.
The silicon oxide film on the first metal wiring was anisotropically dry-etched under a pressure of torr to form a 0.5 μm square through hole, and at the same time, the antireflection film in the hole was also removed. Then, the same Al alloy 3 as the first metal wiring is applied to 800
and TiN as the antireflection film 4 with a thickness of 50 nm by sputtering, the laminated film was selectively etched to form a second metal wiring. Next, in order to planarize the second metal wiring, first, TEOS [Si (OC ₂ H ₅ ) ₄ ] and O ₂ are mixed with 380
The third silicon oxide film 7 was formed in a thickness of 550 nm by performing a plasma gas phase reaction at a temperature of about 9 torr. Next, SiH ₄
And NH ₃ were plasma-reacted at 360 ° C. at about 6 torr, and a silicon nitride film 11 was laminated to a thickness of 50 nm. Then, the second coated glass 10 is spin-coated for about 450
When annealing is performed for 30 minutes in a N ₂ atmosphere at a temperature of about 50 to 700 Å on the flat portion on the second metal wiring region, and a coating glass of about 300 nm is accumulated on the stepped portion and the groove portion even though it is thick. Next, in an Ar atmosphere of about 200 mtorr, C ₂
Dry etching is performed by applying a high frequency bias of 800 W using F ₆ gas to remove at least the first coated glass on the second metal wiring region. This second coated glass 1
In the step of removing 0, since the silicon nitride film 11 is laminated between the coating glass 10 and the third silicon oxide film 7, the end point can be determined by monitoring the plasma emission wavelength. . At this time, the silicon nitride film on the flat portion of the step is removed at the same time, but it may be left as it is. Next, SiH ₄ and NH ₃ were plasma-reacted with O ₂ carrier to vapor-deposit a silicon nitride film as the passivation film 12, and finally a bonding pad portion was opened to take out the electrode to the outside. In the semiconductor device having such a structure, since the step due to the second metal wiring is relaxed, voids are not generated in the passivation film, the problem of moisture resistance is eliminated, and the long-term reliability is improved. It was

Next, FIGS. 3A to 3C are process sectional views for explaining another embodiment of the semiconductor device and the manufacturing method thereof according to the present invention. In a Si gate CMOS-LSI having a two-layer wiring structure using an Al alloy, first, TEOS [Si is used as an interlayer insulating film on the first metal wiring layer.
(OC ₂ H ₅ ) ₄ ] and O ₂ are reacted in a plasma gas phase at 380 ° C. and about 9 torr to form the first silicon oxide film 5 at 550 n.
m, O ₂ carrier 60 to 100 tor of O ₃ and TEOS
A second silicon oxide film 6 having a thickness of 400 nm was formed by thermal reaction under reduced pressure at r and 380 ° C. Then CHF ₃ , CF ₄ and A
Anisotropic etch back of about 450 nm is performed by a plasma etcher using r or the like, the flat portion of the second silicon oxide film is entirely removed, and the side wall is left in the space of the first metal wiring. Next, SiH ₄ and NH ₃ are added at 360 ° C. at about 6 torr.
Then, the silicon nitride film 11 was laminated to a thickness of 50 nm. Subsequently, the organic or inorganic coated glass 9 is spin-coated and then annealed for 30 minutes in an N ₂ atmosphere at about 450 ° C. Next, in a Ar atmosphere of about 200 mtorr, a C ₂ F ₆ gas is used and a high frequency bias of 800 W is applied to perform dry etching to remove at least the first coated glass on the first metal wiring region. This coated glass 9
Also in the step of removing the film, since the silicon nitride film 11 is laminated between the coating glass 9 and the first silicon oxide film 6 as in the previous embodiment, the plasma emission wavelength can be monitored. It becomes possible to determine the end point. At this time, the silicon nitride film on the flat portion of the step is removed at the same time, but it may be left as it is. Next, after vapor-depositing a third silicon oxide film 7 with a thickness of 150 nm, CHF ₃ ,
First using CF ₄ and He gas at a pressure of 300 mtorr
The silicon oxide film on the metal wiring was anisotropically dry-etched to form a 0.5 μm square through hole, and at the same time, the antireflection film in the hole was also removed. Subsequently, the same Al alloy 3 as that of the first metal wiring and 800 nm and TiN as the antireflection film 4 are grown by sputtering to a thickness of 500 Å, and then the laminated film is selectively etched to form the second metal wiring and further as the passivation film 12. SiH ₄ and NH ₃ were plasma-reacted with N ₂ carrier to form a plasma nitride film having a thickness of 1000 nm, and finally a bonding pad portion was opened to take out an electrode to the outside. In the semiconductor device manufactured in this manner, the flattening of the metal wiring interlayer insulating film can be performed with good reproducibility, and as a result, the covering property of the second metal wiring is stable, and the electrical characteristics and long-term reliability are improved. Was achieved. Further, this manufacturing method can be applied not only to the metal wiring layers but also to the polysilicon wiring layers, the polysilicon wiring-metal wiring layers, and the passivation structure, and the same effect can be obtained. Furthermore,
In the semiconductor device having the structure as shown in FIG. 3C, the diffusion of impurities in the coated glass can be prevented by interposing the silicon nitride film between the coated glass and the silicon oxide film. Was stable and long-term reliability was improved.
Such a wiring interlayer structure can be applied not only to the metal wiring layers but also to the polysilicon wiring layers and the polysilicon-metal wiring layers, and the same effect can be obtained.

Finally, another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. The semiconductor device having the structure as shown in FIG. 4 is manufactured by the following embodiment, for example. In a Si gate CMOS-LSI having a two-layer wiring structure using an Al alloy, field insulation in which a silicon oxide film is laminated by selective oxidation or vapor phase growth of a silicon substrate surface on which semiconductor elements such as MOS transistors and resistors are formed. A contact hole is formed in the film 1, a barrier metal, an Al alloy 2 containing 0.5% Cu, and TiN to be the antireflection film 4 are laminated by sputtering, and then Cl ₂ and BC are added.
The laminated film was selectively etched by a dry etcher using l ₃ gas to form a first metal wiring having a total thickness of 700 nm. Next, as an interlayer insulating film, SiH ₄ and O ₂ or N ₂ O
The first silicon oxide film, which has been subjected to plasma reaction or thermal reaction with an oxidizing gas such as the above, is vapor-grown at a thickness of about 500 nm to 800 nm, and the organic or inorganic coated glass 9 is spun from the necessity of flattening in the fine structure. It is coated and annealed at a temperature that does not interfere with the first metal wiring. Subsequently, a C ₂ F ₆ gas was used in an Ar atmosphere, and a high frequency bias of 800 W was applied to perform dry etching to remove at least the first coated glass on the first metal wiring region. Next, 150 nm
Of the second silicon oxide film 6 with a thickness of
CHF ₃ , CF ₄ and He gas are used to anisotropically dry-etch the silicon oxide film on the first metal wiring at a pressure of 300 mtorr to open a 0.5 μm square through hole, and at the same time, reflect in the hole. The barrier film was also removed. Subsequently, the same Al alloy 3 as the first metal wiring and 800 nm and TiN as the antireflection film 4 with a thickness of 50 nm were sputter-grown, and then the laminated film was selectively etched to form a second metal wiring. In order to flatten the step on the second metal wiring, first, TEOS [Si (OC ₂ H ₅ ) ₄ ] and O ₂ are added at 380 ° C. at about 9 ° C.
Plasma vapor phase reaction is performed at torr to form a third silicon oxide film 7 at 550 nm, and O ₃ and TEOS are made 60 by O ₂ carrier.
400n at 380 ° C under reduced pressure thermal reaction
m fourth silicon oxide film 8 was formed. Then CHF
Approximately 45 with plasma etcher using ₃ , CF ₄ and Ar
Anisotropic etching back of 0 nm is performed, the flat portion of the fourth silicon oxide film is entirely removed, and the side wall is left in the space of the second metal wiring. Then, SiH ₄ and NH ₃ are added to 360
A plasma reaction was performed at a temperature of about 6 torr and a silicon nitride film 11 of 500 Å was laminated. Subsequently, spin coating of the organic or inorganic second coated glass 10 is performed at about 450 ° C.
Anneal for 30 minutes in N ₂ atmosphere. Then 200
Using C ₂ F ₆ gas in an Ar atmosphere of about mtorr,
Applying a high frequency bias of 00W for dry etching,
At least the second coated glass on the second metal wiring region is removed. At this time, the silicon nitride film on the flat portion of the step is removed at the same time, but it may be left as it is. Next, as a passivation film 12, SiH ₄ and NH ₃ were plasma-reacted with N ₂ carrier to form a plasma nitride film of 1000 nm, and finally a bonding pad portion was opened to take out an electrode to the outside.

In the semiconductor device having such a structure, since the step due to the second metal wiring is relaxed, voids are not generated in the passivation film, the problem of moisture resistance is eliminated, and long-term reliability is improved. I was able to improve.

[0014]

As described above, according to the present invention, the flatness of the wiring interlayer film, the passivation film, and the field interlayer film and the reproducibility of the planarization are improved, and at the same time, the coating is performed especially in an integrated circuit having a multilayer wiring structure. By suppressing the diffusion of impurities in the glass and the generation of voids in the passivation film, electrical characteristics and moisture resistance can be improved, and stable supply of high-quality fine semiconductor devices can be achieved.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a semiconductor device and a method for manufacturing the same according to the present invention.

FIG. 2 is a sectional view of a semiconductor device according to the present invention.

FIG. 3 is a process sectional view showing a semiconductor device and a method for manufacturing the same according to the present invention.

FIG. 4 is a sectional view of a semiconductor device according to the present invention.

FIG. 5 is a process sectional view relating to a conventional semiconductor manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 field insulating film 2 first metal wiring 3 second metal wiring 4 antireflection film 5 first silicon oxide film 6 second silicon oxide film 7 third silicon oxide film 8 fourth silicon oxide film 9 1 coated glass 10 2nd coated glass 11 Silicon nitride film 12 Passivation film 13 Void

Claims (6)

[Claims] 1. In a semiconductor device having a multi-layer wiring structure, at least (a) a first gas phase reaction on the wiring layer.
The step of forming a silicon oxide film, (b) the step of forming a silicon nitride film, (c) the step of spin-coating a coated glass, and (d) the step of etching back a predetermined thickness of said laminated insulating film. A method of manufacturing a semiconductor device, comprising: 2. A semiconductor device having a multilayer wiring structure,
At least on the first wiring layer, (a) a first gas phase reaction
A silicon oxide film, (b) silicon nitride film, (c) coated glass, (d) second silicon oxide film, and second wiring layer are sequentially stacked. 3. A semiconductor device having a multilayer wiring structure,
A semiconductor device in which (a) a first silicon oxide film, (b) a silicon nitride film, (c) a coated glass, and (d) a silicon nitride film are sequentially stacked on at least a metal wiring layer. 4. A semiconductor device having a multilayer wiring structure,
At least (a) a step of forming a first silicon oxide film on the wiring layer, (b) a step of forming a second silicon oxide film, and (c) a step of etching back a desired film thickness of the laminated insulating film. , (D) a step of forming a silicon nitride film,
A method of manufacturing a semiconductor device, comprising: (e) a step of spin-coating a coated glass; and (f) a step of etching back a predetermined thickness of the laminated insulating film. 5. A semiconductor device having a multilayer wiring structure,
At least on the first wiring layer, (a) a first gas phase reaction
Silicon oxide film, (b) second silicon oxide film,
(C) Silicon nitride film, (d) coated glass, (e) third
A semiconductor oxide film, and (f) a second wiring layer are sequentially stacked. 6. A semiconductor device having a multilayer wiring structure,
(A) A first silicon oxide film, (b) a second silicon oxide film, (c) a silicon nitride film, (d) coated glass, and (e) a silicon nitride film were sequentially stacked on at least a metal wiring layer. A semiconductor device characterized by the above.