JPH07281889A - Instruction execution device - Google Patents

Abstract

PURPOSE:To make, for example, a microcontroller unit, which executes instructions to plural modules decentralizing by a central processing part, adapt to the addition of a module. CONSTITUTION:When a CPU 2 outputs the address of an instruction to a ROM, an instruction load cycle signal is outputted to an instruction load cycle signal line 5 at the same time. Each module (e.g. M1-M4) is provided with a stand-by process part 7 to monitor, for example, the high-order 8 bits of 16 bits where an operator code is read out and the low-order 8 bits where an operand is read out and also monitor whether the instruction load cycle signal is present or not. When the instruction load cycle signal is outputted and the high-order 8 bits are a code corresponding to a stand-by instruction, the instruction at this time is the stand-by instruction, so an internal clock signal is stopped if a module which should stand by, corresponds to the instruction itself among the low-order 8 bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, an MCU (micro
The present invention relates to an instruction execution device such as a controller unit) and, more particularly, to an instruction execution device characterized by a portion for stopping (or canceling supply stop) of a clock signal in a module that does not execute an instruction.

[0002]

2. Description of the Related Art Generally, an instruction read from a memory by a central processing unit may be distributed to and executed by a plurality of modules connected to a bus. For example, the MCU of a communication device includes modules such as an A / D converter, a D / A converter, a pulse width modulator, a timer, a serial high-speed communication unit, and a pulse counter, and the CPU decodes a group of instructions for transmission and reception. Then, the instructions are distributed to each module and executed. In this case, the processing of each module is performed in synchronization with the clock signal from the CPU, but it is a good idea to stop the clock signal for the module not related to the instruction at that time in order to save power consumption. .

A conventional method for stopping the clock signal will be described below with reference to FIG.
10A is an address bus, 10B is a data bus, M1 to M
4 is a module. First, the CPU 1 outputs the address to, for example, the ROM corresponding to the module M1, and the ROM
The instruction is read out from the CPU, the operation code of the instruction is monitored by the operation code decoder 11 in the CPU 1, and if the operation code is a code corresponding to the standby instruction, the operand decoder 12 decodes the operand of the instruction. In the operand of the wait instruction, the number of the module that should stop the internal clock signal is written, and the CPU 1
Based on the decoding result of the operand decoder 12, a standby command is output to the corresponding module through the dedicated standby command signal path 13. On the other hand, the CPU 1 sends a clock signal to each module through the clock signal line 14, and the module receiving the standby command closes the input gate of the clock signal and stops the internal clock signal.

[0004]

By the way, there are cases where a module is added by expanding the system after manufacturing the MCU and incorporating it into the system. Here, it is practically difficult to assume the number of modules to be added in the future when the MCU is manufactured. In the conventional MCU, when the internal clock signal of the module is stopped as described above, the CPU 1 issues an instruction by the internal decoder. The number of the module to be read is grasped by decoding, and the standby command is output through the dedicated standby command signal path 13 for each module. Therefore, when adding a module, the CPU 1
The inside of must be changed. However CPU
When the inside of 1 is changed, the debug tool (development software and hardware) necessary for developing the software of the MCU using the CPU needs to be changed.

Further, the software previously created for the MCU using the CPU before the change is the CPU after the change.
There is a risk that it cannot be used with an MCU that uses. Since the development of software programs takes a lot of time and effort, it is very disadvantageous to break the compatibility of software.

The present invention has been made under such circumstances, and an object thereof is to easily add a module in a device in which a central processing unit distributes and executes instructions to a plurality of modules. It is to provide an instruction execution device capable of handling.

[0007]

According to a first aspect of the present invention, a central processing unit and a plurality of modules are connected to a bus, and instructions read from a memory are distributed to the plurality of modules and executed by the central processing unit. In an instruction execution device for stopping a clock signal from a central processing unit for a module designated as an operand of a standby instruction, the instruction processing unit is provided in the central processing unit and outputs an instruction load cycle signal when reading an operation code of an instruction. An output unit, a signal path for transmitting an instruction load cycle signal from the output unit to each module, and a standby processing unit provided for each module, and the standby processing unit is provided with the instruction load cycle signal The signal path, the signal path from which the opcode of the instruction is read out and the signal path from which the operand of the instruction is read out of the bus are monitored, and From the signal path to the instruction load cycle signal, the signal corresponding to the standby instruction, and the signal corresponding to its own module, respectively, a monitoring unit that outputs a clock stop signal, and a clock stop output from this monitoring unit. And a clock stop circuit for stopping the clock signal from the central processing unit to be taken into its own module by a signal.

According to a second aspect of the present invention, the central processing unit and a plurality of modules are connected to a bus so that the instructions read from the memory are distributed to the plurality of modules and executed by the central processing unit, while the operand of the wait release instruction is executed. In the instruction execution device for canceling the supply stop of the clock signal from the central processing unit to the module specified in, the output unit which is provided in the central processing unit and outputs the instruction load cycle signal when the operation code of the instruction is read. A signal path for transmitting an instruction load cycle signal from the output section to each module, a standby release processing section provided for each module,
The standby release processing unit monitors a signal path of the instruction load cycle signal, a signal path of the bus from which an operation code of an instruction is read and a signal path of an operand of an instruction to be read, and When the signals are the instruction load cycle signal, the signal corresponding to the wait release instruction, and the signal corresponding to its own module, respectively, a monitoring unit that outputs a clock stop release signal, and a clock stop release signal output from this monitoring unit And a clock stop canceling circuit for canceling the supply stop of the clock signal taken in by the central processing unit into its own module.

[0009]

When the module fetches the instruction load cycle signal output from the central processing unit, the module side can grasp the read time of the operation code, and the module side monitors the operation code and operand. It is possible to know whether or not the module to wait is its own module. Therefore, when a module is added, it is possible to deal with the CPU without changing it by simply providing a circuit for fetching the operation code, the instruction load cycle signal and the operand in the module and attaching the circuit, so that it is easy to improve the performance. .

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 2 is a CPU which is a central processing unit, for example, 1
It is connected to a 6-bit data bus 3 and a 16-bit address bus 4. The CPU 2 decodes the operation code of the instruction and grasps the type and the number of lines of the instruction, and the RO for reading the instruction.
An output unit 22 for outputting an instruction load cycle signal (LIC [Load Instruction Cycle]) when outputting an address to M is provided.

The data bus 3 and the address bus 4 have a plurality of modules M1 to M4 (four modules in the illustrated example).
For example, these modules are detachably connected, and these modules include a ROM, a RAM, a synchronous high-speed serial communication port,
Asynchronous high-speed serial communication port, timer, digital /
An analog converter, an analog / digital converter, a pulse counter, etc. correspond. In the CPU 2, an instruction load cycle signal line 5 for outputting the instruction load cycle signal from the instruction load cycle signal output unit 22 to the outside of the CPU 2 and a clock signal (C) to each of the modules M1 to M4.
A clock signal line 6 for sending LK) is connected.

On the other hand, of the instruction group stored in the ROM (module M1), the module wait instruction (Wai)
In t), as shown in FIG. 3, the operation code is stored in the upper 8 bits (D15 to D08) of the data bus 3 and the lower 8 bits (D15).
07 to D00), and in this example, each bit of the lower 8 bits is associated with the module number. For example, when the module M1 is made to wait, the lower first bit D07 is set as shown in FIG. Set "1",
The second bit D06 when waiting for the module M2
The opcode is configured such that "1" is set to "".

The modules M1 to M4 include
A standby processing unit 7 is provided, and this standby processing unit 7 is
As shown in FIG. 3, for example, the signal of the upper 8-bit bit line of the data bus 3 and the signal of the instruction load cycle signal line 5 are monitored, and the instruction load cycle signal line 5 outputs the instruction load cycle signal, for example, logic "1". Signal is input and the upper 8 bits are a code corresponding to an operation code of the type in which the module must monitor the operand, a recognition signal of, for example, a logical "1" for recognizing the wait instruction is output. The operation code monitoring unit 71 is provided.

Further, the standby processing section 7 is provided with an operand monitoring section 72 and a clock stop circuit 73 for stopping a clock signal at a stage subsequent to the operation code monitoring section 71. The operand monitoring unit 72 monitors the operand of the instruction and determines whether or not the content of the operation code of the standby instruction makes the module of its own stand by. The operand monitoring unit 72 is, for example, an AND circuit. A signal of a bit assigned to its own module among the lower 8 bits of the bus 3, that is, a bit for which "1" is set when the module of its own is made to stand by is input to one input end of the operand monitoring unit 72. At the same time, the output end of the operation code monitor 71 is input to the other input end of the operand monitor 72.

The clock stop circuit 73 takes in a clock signal from the clock signal line 6 and inputs the output signal of the operand monitoring section 72, and the operand monitoring section 72.
When the output signal of is a logic "0", the clock signal is output to the internal circuit of the module, and when the output signal of the operand monitoring unit 72 changes from "0" to "1", the falling of the clock signal It has a function of stopping the output of the clock signal at a timing, that is, stopping the clock signal in synchronization with the clock signal.

Next, the operation of the above embodiment will be described. Now, assuming that the address is output from the CPU 2 and the instruction corresponding to the address is read from the ROM (M1),
The CPU 2 outputs an instruction load cycle signal from the output unit 22 to the instruction load cycle signal line 5 when outputting the address. If this instruction is, for example, a wait instruction for causing the module M2 to wait, the upper 8 bits of the data bus 3 are an operation code indicating that it is a wait instruction, and the lower 8 bits indicate that the module to wait is M2. This is the indicated operand. That is, in this example, only the second bit (D06) of the lower 8 bits (D07 to D00) is "1".
Is standing.

The operation code monitoring section 71 of each of the modules M1 to M4 recognizes that the upper 8 bits of the data bus 3 at that time is an operation code because the instruction load cycle signal is input, and the operation code becomes a standby instruction. Since it is the corresponding code, the operation code monitoring unit 71 outputs a recognition signal of logic “1” to the operand monitoring unit 72. In the modules M1, M3, and M4, the bits of the data bus 3 input to the operand monitoring unit 72 are lower 1 respectively.
Since it is the bit D07, the third bit D05, and the fourth bit D04, it is "0", and the output of the operand monitoring unit 72 is a logical "0".

Therefore, these modules M1, M3, M4
In the clock stop circuit 73, the clock signal from the clock signal line 6 is output to the internal circuit without stopping. On the other hand, in the module M2, since the bit of the data bus 3 input to the operand monitoring unit 72 is the lower second bit D06, it is "1", and the operand monitoring unit 7
The output of 2 becomes logic "1" and the clock signal from the clock signal line 6 is stopped by the clock stop circuit 73.

The above description of the operation is the cycle when the standby instruction is read. In the next cycle, the instruction for the CPU to issue the instruction to the modules M3 and M4 is read from the ROM (M1). In this cycle, since the operation code is not the code corresponding to the wait instruction, no recognition signal is output from the operation code monitoring unit 71 of each module, and when the CPU reads the operand, the code of the data bus 3 happens to be the operation code and the operand of the wait instruction. Even if the combination is the same, the instruction load cycle signal line 5 does not output the instruction load cycle signal at that time, so that the operation code monitoring unit 71 of each module does not output the recognition signal and the clock stop circuit. It does not affect 73.

FIG. 4 conceptually shows such an operation as a flow chart. The clock stop circuit 73 does not have a function of once again stopping the clock signal and then generating it again. Therefore, in order to generate the internal clock signals of all the modules M1 to M4, for example, a wakeup signal from the outside is not shown. To the clock stop circuit 73, and to stop the internal clocks for some of the modules M1-M4, a wait instruction will be read from the ROM.

According to the above-described embodiment, when a module is added, a circuit for fetching an opcode, an instruction load cycle signal and an operand is simply provided in the module and attached thereto, and the CPU can be dealt with without any change. Therefore, it is not necessary to change the debug tool necessary for developing the software, and there is no fear of compromising the compatibility of the software, so that the performance of the MCU can be easily improved. Further, as for the operand decoder, the 8-bit operand decoder in the conventional CPU becomes unnecessary, and it suffices to provide the 1-bit operand decoder in each module, so that the CPU silicon space can be reduced. Also C
Even when wiring a dedicated signal line related to the execution of a standby instruction from the PU, it is sufficient to provide one instruction load cycle signal line instead of using as many standby instruction signal lines as there are modules. .

In the above, the data bus 3 is not limited to 16 bits but may be, for example, 8 bits. In this case, the operation code is read in the first cycle and the operand is read in the second cycle. Since the read processing is performed, the standby processing unit 7 has the operation code monitoring unit 7
This can be dealt with by providing a latch circuit for latching the output of 1.

Further, in the present invention, instead of validating the internal clock signals of all the modules and invalidating the internal clock signals of a predetermined module by the standby instruction as described above, the internal clock signals are validated in reverse. A standby release instruction in which the number of the module to be written is written in the operand is stored in the ROM, and a standby release processing unit similar to the standby processing unit is provided in each module (however, the clock stop circuit 73 becomes a clock signal stop release circuit). ) May be provided to stop the internal clock signals of all the modules and then generate (validate) the internal clock signals of the module designated by the standby release instruction.

[0024]

As described above, according to the present invention, when the clock signal is stopped (or released from the stop) for some of the modules, the module monitors and processes the instruction. MC does not have to change the inside of the central processing unit when adding modules
It is possible to easily improve the performance of U and the like.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a standby instruction.

FIG. 3 is a circuit diagram showing an example of a standby processing unit in the module according to the embodiment of the present invention.

FIG. 4 is a flow chart schematically showing the operation of the embodiment of the present invention.

FIG. 5 is a block circuit diagram showing a configuration of a conventional MCU.

[Explanation of symbols]

 2 CPU M1 to M4 modules 3 data bus 4 address bus 5 instruction load cycle signal line 6 clock signal line 7 standby processing unit 71 monitoring unit 72 operand monitoring unit 73 clock stop circuit

Claims (2)

[Claims] 1. A central processing unit and a plurality of modules are connected to a bus so that an instruction read from a memory is distributed to a plurality of modules and executed by the central processing unit, while being designated as an operand of a standby instruction. For modules,
In an instruction execution device that stops a clock signal from a central processing unit, an output unit that is provided in the central processing unit and outputs an instruction load cycle signal when reading an operation code of an instruction, and an instruction load cycle signal from the output unit A signal path for transmission to each module and a standby processing section provided for each module are provided, and the standby processing section reads out the signal path of the instruction load cycle signal and the operation code of the instruction from the bus. A signal for monitoring the signal path and the signal path from which the operand of the instruction is read, and when the signal on the signal path is a signal corresponding to an instruction load cycle signal, a signal corresponding to a wait instruction, or a signal corresponding to its own module, a clock stop signal And the clock stop signal output from this monitoring unit And a clock stop circuit for stopping a clock signal taken into a module. 2. A central processing unit and a plurality of modules are connected to a bus so that an instruction read from a memory is distributed to a plurality of modules and executed by the central processing unit while being designated as an operand of a wait release instruction. In the instruction execution device for canceling the supply stop of the clock signal from the central processing unit to the module, an output unit which is provided in the central processing unit, and which outputs an instruction load cycle signal when the operation code of the instruction is read, A signal path for transmitting an instruction load cycle signal from the output section to each module, and a standby release processing section provided for each module, wherein the standby release processing section is a signal path for the instruction load cycle signal. Monitoring the signal path from which the opcode of the instruction is read and the signal path from which the operand of the instruction is read, When the signal on the signal path is the signal corresponding to the instruction load cycle signal, the signal corresponding to the wait release instruction, and the signal corresponding to its own module, the monitoring unit that outputs the clock stop release signal, and the clock output from this monitoring unit An instruction execution device, comprising: a clock stop canceling circuit for canceling the supply stop of the clock signal taken into the own module from the central processing unit by the stop canceling signal.