JPH07306798A - Microcomputer device - Google Patents

Abstract

PURPOSE:To test the operation of an instruction PLA of the microcomputer device. CONSTITUTION:A data selector 12, a CPU control signal control part 22, a shift register part 18, and a PC control part 21 are newly added to the microcomputer device; and then a regular output signal from a program counter 9 which increases, one by one, is used as an input signal to the instruction PLA 14 with a mode selection signal 13 and the output signal can be converted into serial data and outputted to the outside. Consequently, the operation test of the instruction PLA is conducted for all input signals to enable recognize results directly, and the number of terminals for the confirmation can be minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device.

[0002]

2. Description of the Related Art In recent years, the use of microcomputer devices for various control of electrical equipment has become an indispensable element. Along with this, demands for functions and performances of microcomputer devices are becoming more sophisticated and complicated day by day. On the other hand, the demand for development period and price is shorter and cheaper. Therefore, it is becoming important to test the function of the microcomputer device faster, easier, and not fail.

A conventional microcomputer device will be described below. FIG. 2 is an example of a block diagram of a conventional microcomputer device. In FIG. 2, reference numeral 1 is a program counter that counts up an address address for executing a program by a PC control signal 2 in a microcomputer device, 3 is an instruction register for storing instruction data for operating the microcomputer device, and 4 is an instruction register. Instruction PLA 5 which decodes the data from the instruction register 3 and outputs the control signal for controlling the internal operation of the microcomputer device stores the output of the instruction PLA 4 by the data latch signal 6 and the data output control signal 7. It is a PLA output control unit that outputs the data that has been processed as a CPU control signal 8 for controlling each control block operation of the microcomputer device.

The operation of the microcomputer device configured as described above will be described below. The operation of the microcomputer device depends on the instruction data stored in the instruction register 3. The instruction data is stored in the memory both inside and outside the microcomputer device. Then, the program counter 1 performs a count-up operation by the PC control signal 2 determined by the CPU control signal 8, the memory access is performed by the output signal of the program counter 1, and the instruction data is stored in the instruction register 3. Instruction P of microcomputer device
When the operation test of the LA 4 is performed, instruction data determined by the output signal of the program counter 1 is input from the outside of the microcomputer device. Instruction data that determines the operation of the microcomputer device is output from the instruction register 3 to the instruction PLA4, is decoded inside the instruction PLA4, and is a signal for operating each control block of the microcomputer device necessary for executing the instruction. Is PLA
It is output to the output control unit 5. The PLA output control unit 5 stores the input data by the data latch signal 6 and uses the data stored by the data output control signal 7 as a CPU control signal 8 for operating each control block of the microcomputer apparatus. Output to each internal block of the device. Therefore, the operation test of the instruction PLA 4 can be performed by executing all the instructions of the microcomputer device and confirming the operation state of the microcomputer device at that time.

[0005]

However, in order to perform the operation test of the instruction PLA of the microcomputer device with the above-mentioned conventional configuration, it is necessary to give an input signal of the instruction PLA arbitrarily.
Since it is not possible to give a regular signal such as incrementing the input signal one by one, and further it is not possible to directly confirm the output signal of the instruction PLA, all commands of the microcomputer device are input from the outside, and as a result, However, there is a problem that it can be confirmed only by an indirect method of confirming with the operating state of the microcomputer device.

The present invention solves the above-mentioned problems of the prior art.
Instruction P is used to test the operation of the LA.
It is an object of the present invention to provide a microcomputer device which can give a regular signal as an LA input signal and directly check its output signal.

[0007]

To achieve this object, a microcomputer device of the present invention comprises a data selector for switching an input signal of an instruction PLA from an output signal of an instruction register to an output signal of a program counter, and a program. PC control unit for controlling the operation of the counter and instruction PLA
And a CPU control signal control unit for processing the output signal from the instruction PLA and controlling the output signal by processing the output signal from the instruction PLA into each control block of the microcomputer device. .

[0008]

With this structure, the microcomputer device can output a regular signal, which is incremented by one, from the program counter as an input signal of the instruction PLA. Then, the output signal of the instruction PLA can be converted into serial data by the shift register unit and output to the outside of the microcomputer device. Therefore, instruction PL
The operation test of A can be tested for all input signals, and by outputting the result as serial data by data conversion, it is possible to directly check the result and minimize the number of terminals for checking the result. be able to.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a microcomputer device according to an embodiment of the present invention. In FIG. 1, 9 is a program counter that counts up an address address for executing a program by a PC control signal 10 in a microcomputer device, 11 is an instruction register in which instruction data for operating the microcomputer device is stored, 1
Reference numeral 2 is a data selector for switching between the output signal of the program counter 9 and the output signal of the instruction register 11 according to the mode selection signal 13 for output, and 14 is for decoding the data from the data selector 12 and controlling the internal operation of the microcomputer device. The instruction PLA, 15 which outputs the control signal of the above, stores the output of the instruction PLA 15 by the data latch signal 16,
The PLA output control unit outputs the stored data by the data output control signal 17. 18 is a mode selection signal 13
With the shift register unit that converts parallel data into serial data at the cycle of the system clock 19 which is the reference clock and outputs as serial data output 20, after converting all the data to serial data, a pulse signal for one cycle is converted. It is output as the end signal 21. 22 is a CPU control signal for controlling the operation of the microcomputer device by using the output signal of the PLA output controller 15
Is output to each control block as well as to the shift register unit 18, and is processed by the mode selection signal 13 as the CPU control signal 23 without executing anything as the operation of the microcomputer device. A control signal of an instruction that consumes one cycle is output to the microcomputer device. 24 controls the original PC control signal 25 by the mode selection signal 13 and the conversion end signal 21 from the shift register section 18 to newly add the program counter 9
It is a PC control unit that outputs a PC control signal 10 to.

The operation of the microcomputer device of this embodiment constructed as described above will be described below. First, the operation when the mode selection signal 13 is an inactive signal output will be described. At this time, the PC control unit 24
Original PC control signal 25 determined by CPU control signal 23
Is output to the program counter 9 as it is. Therefore, the operation of the program counter 9 is the same as that of a normal microcomputer device. Then, the data selector 12 outputs the output signal of the instruction register 11. Therefore, instruction PLA14
Command data is input from the data selector 12.
The instruction PLA 14 decodes the instruction data and outputs an output signal as a result to the PLA output control unit 15. The PLA output control unit 15 stores the input data by the data latch signal 16 and outputs the stored data by the data output control signal 17 to the CPU control signal control unit 22. The CPU control signal control unit 22 outputs the output signal of the PLA output control unit 15 as it is as the CPU control signal 23 to each control block of the microcomputer device. The CPU control signal control unit 22 also outputs the output signal of the PLA output control unit 15 to the shift register unit 18 as a CPU control signal 23. At this time, the shift register unit 18 inhibits the input of the system clock 19 to inhibit the conversion of the input data, and inhibits the output of the serial data output signal 20. Therefore, the mode selection signal 13
Is in the inactive state, the normal operation state in which the operation of the microcomputer device is determined by the instruction data of the instruction register 11 is established.

Next, the operation when the mode selection signal 13 is an active signal output will be described. At this time, the PC control unit 24
Does not output the original PC control signal 25 determined by the CPU control signal 23 to the program counter 9, but does not output the PC by the conversion end signal 21 output from the shift register unit 18.
The control signal 10 will be output. The PC control signal 10 prohibits the count-up operation of the program counter 9 and causes the count-up operation after the pulse output until the shift register 18 outputs a pulse for one cycle as the conversion end signal 21. Therefore, the program counter 9 does not count up until the conversion of the shift register unit 18 is completed, and continues to output a constant signal. That is, the program counter 9 counts up each time the data conversion of the shift register unit 18 is completed. At this time, the data selector 12 outputs the output signal of the program counter 9 instead of the output signal of the instruction register 11. Therefore, the shift register unit 18 is sent to the instruction PLA 14.
The output signal of the program counter 9 which is incremented each time the data conversion of is completed is input. The instruction PLA 14 decodes the input data and outputs the resulting output signal to the PLA output control unit 15.
The PLA output control unit 15 stores the input data by the data latch signal 16 and outputs the stored data by the data output control signal 17 to the CPU control signal control unit 22.

The CPU control signal control unit 22 does not output the output signal of the PLA output control unit 15 as it is as the CPU control signal 23, and as the operation of the microcomputer device, it does not execute any operation and consumes one cycle of an instruction. The control signal is output to each control block of the microcomputer device. Therefore, as the internal state of the microcomputer device, a state is created in which the next instruction is taken in without executing any instruction. At this time, the control of the program counter 9 is
It operates independently of the CPU control signal 23, and the instruction data from the instruction register 11 is controlled by the data selector 12 to control the instruction PLA1.
There is no input to 4. That is, the microcomputer device outputs a signal as a normal operation as the CPU control signal 23 to each control block, but the operation state is a special operation state in which the output signal of the program counter is decoded by the instruction PLA 14 and the result is output. Becomes

At this time, the CPU control signal control unit 22 also outputs the CPU control signal 23 to the shift register unit 18. Since the operation state of the shift register section 18 is determined by the mode selection signal 13, it operates regardless of the CPU control signal 23. The shift register unit 18 sets the input CPU control signal 23 to 1 at the cycle of the system clock 19.
Output bit by bit. Therefore, the CPU control signal 23 having a plurality of bit widths can be output to the outside as the serial data output 20 which is a 1-bit width signal.

After the conversion of the CPU control signal 23 into serial data is completed, the conversion end signal 21 is output to the PC control unit 24. Therefore, when the mode selection signal 13 is in the active state, the output result of the program counter 9 can be decoded by the instruction PLA 14, and the result can be converted into 1-bit serial data at the cycle of the system clock 19 and output to the outside. It will be possible. The count-up operation of the program counter 9 at this time is 1
Instruction PLA14 for one input data
It is performed after all the decoding results of are converted into serial data. By repeating the count-up operation of the program counter 9, the operation of the instruction PLA 14 is confirmed for all combinations of input signals, and
Since the output of the result is converted into serial data, the number of terminals required for confirming the result can be reduced to one.

As described above, according to the present embodiment, the operation test of the instruction PLA 14 of the microcomputer device is performed without exception for all the states of the input signals by the mode selection signal 13, and the decoding result of the instruction PLA 14 is set to 1. It can be output from the terminal.

[0016]

As described above, according to the present invention, by adding the PC control unit, the data selector, the shift register unit, and the CPU control signal control unit to the conventional microcomputer device, the instruction PLA of the microcomputer device can be realized. It is possible to realize an excellent microcomputer device capable of performing an operation test for all input signals without fail and directly confirming the result and minimizing the number of terminals for confirming the result.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional microcomputer device.

[Explanation of symbols]

 9 program counter 10 PC control signal 11 instruction register 12 data selector 13 mode selection signal 14 instruction PLA 15 PLA output control section 16 data latch signal 17 data output control signal 18 shift register section 19 system clock 20 serial data output 21 conversion end signal 22 CPU control signal control unit 23 CPU control signal 24 PC control unit 25 Original PC control signal

Claims (1)

[Claims] 1. A data selector for switching an input signal of an instruction PLA from an output signal of an instruction register to an output signal of a program counter, a PC control section for controlling operation of the program counter, and an output signal from the instruction PLA. And a CPU control signal control section for processing the output signal from the instruction PLA into the shift register section and each control block of the microcomputer apparatus for output control. .