JPH06131150A - Encoder - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a memory, and to save the memory by providing a decoding memory table to deal with decoding in which a variable length code bit string and a fixed length code bit string are made a pair, and outputting the fixed length code bit string of the memory table at the time of the coincidence of it with the variable length code bit string as a decoded value. CONSTITUTION:The values of code table RAMs 440 to 443 are evaluated at a time for the value of a register 460. Then, by switching multiplexers 451 to 452, encoding/decoding is dealt with. When one of comparators makes a hit while increasing gradually the value of an address counter 433, the address counter 433 is stopped immediately, and the multiplexer 455 is controlled by a select control circuit 461 so as to output the correct encoded value/decoded value and code length to code output 465 and code length output 466 respectively. By arranging four set, for instance, of encoding/decoding circuits in this way, and operating them in parallel, the four times higher speed of the encoding/ decoding can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for constructing an encoding device.

[0002]

2. Description of the Related Art A conventional variable length code encoding / decoding apparatus will be described. A conventional example is a direct mapping method.

The direct mapping method in decoding uses a variable length code input as an address and obtains a decoded value from corresponding data. Further, in the direct mapping method in encoding, a variable value code that is input is used as an address and a decoded value is obtained from corresponding data.

One of the merits of the direct mapping method is that encoding and decoding can be performed at high speed. The processing time in the direct mapping method is equal to the time from when the memory address is specified to when it is read,
In many cases, encoding / decoding with one system clock is possible.

[0005]

However, in the above-mentioned prior art, since the address of the decoding table is required for the maximum code length of the input Huffman code, the table capacity becomes very large and is not effectively used. It is possible to create a table area. For example, in Figure 5,
It is a diagram showing the data contents of the code table RAM used in the present embodiment, a variable length code table similar to this,
When created by the direct mapping method, the maximum code length is 11 bits, so 11 bits are required for the address.
We need a table of 2048 words in the 11th power of. On the other hand, since it is 33 words in FIG. 5, it can be seen how large it is.

Further, in decoding, a variable length code to be decoded is assigned as a table address, and in coding, fixed length data to be encoded is assigned as a table address. Wrong. Therefore, the table cannot be shared between encoding and decoding.

That is, the conventional technique has a problem that a very large memory capacity and a table having a separate structure for encoding / decoding are required.

Therefore, in order to solve such a problem,
According to the configuration of claim 1 of the present invention, since one code can be stored in one word, it is an object of the present invention to improve the memory usage efficiency and save the memory. Another object of the present invention is to arrange the data in the table in the order of the code having the highest frequency of occurrence and to evaluate the data in order to extremely shorten the decoding time.

According to the second aspect of the present invention, it is an object of the present invention to perform encoding using the same code table as the decoding table.

According to the third aspect of the present invention, it is an object of the present invention to perform encoding using the same code table as the decoding table, and to perform decoding and encoding using the same circuit. .

According to the structure of claim 4 of the present invention, it is an object to realize a high-speed encoding / decoding by incorporating a plurality of sets of encoding / decoding circuits and operating them in parallel.

[0012]

According to a first aspect of the present invention, there is provided a variable length decoding device for decoding an input variable length code bit string into a fixed length code bit string by referring to a memory table. A variable-length code bit string and a fixed-length code bit string corresponding to decoding are arranged in pairs, and a decoding memory table is further provided, and an output of the memory table and a comparator for comparing the input variable-length code bit string are provided, It is characterized in that the comparator outputs the fixed-length code bit string of the memory table as a decoded value when the variable-length code bit string matches.

According to a second aspect of the present invention, an encoding device refers to an input fixed length code bit string while referring to a memory table,
In a variable-length coding device for coding into a variable-length code bit string, a coding memory table in which a fixed-length code bit string and a variable-length code bit string corresponding to coding are arranged in pairs, and the output of the memory table And a comparator for comparing the input fixed-length code bit strings, and when the fixed-length code bit strings match in the comparator, the variable-length code bit string of the memory table is output as an encoded value.

According to a third aspect of the present invention, in the encoding apparatus according to the first and second aspects, the fixed length code bit string and the variable length code bit string of the memory table are selected and input to the comparator. It has a selector,
It is characterized in that a fixed length code bit string and a variable length code bit string of the memory table input to the comparator can be switched.

An encoding apparatus according to a fourth aspect of the present invention is characterized in that, in the encoding apparatus according to the first, second and third aspects, a memory table and a plurality of sets of comparators are mounted.

[0016]

The details of the present invention will be described below with reference to Examples.

(Embodiment 1) This embodiment relates to claim 1 of the claims.

FIG. 2 is a block diagram showing the configuration of this embodiment. In the code table RAM (510), fixed length data (511) and variable length code (512) are written in pairs at the same address.

Further, the code length (513) corresponding to the variable length code (512) is also written in pairs at the same address.

If a variable length code corresponding to fixed length data and its code length are written in the code table in advance,
When a certain address is designated, a certain fixed length data, a variable length code corresponding to it, and a code length are obtained.

FIG. 5 is a diagram showing the data contents of the code table RAM used in this embodiment. For example, when address 4 is specified, fixed length data 5 (decimal display)
And a variable length code 0010 (binary display) and a code length 4 (decimal display) corresponding thereto are obtained.

Alternatively, when the address 27 is designated, the fixed length data 28 (decimal display) and the corresponding variable length code 0000 0011 101 (binary display) and the code length 11 (decimal display) are displayed. Will be obtained.

By downloading these data to the (510) code table RAM from the (501) download data bus, various variable length code tables can be supported.

Further, as long as the RAM capacity allows, a plurality of tables can be downloaded at once and used properly.

Since this embodiment relates to decoding of variable length codes, the decoding operation will be described.

(508) The address counter is (51
0) It is connected to the address input of the code table RAM and specifies the address of the code table RAM.

First, the start address of the code table to be decoded is set to (50) from the (503) set address bus.
8) Load to the address counter.

On the other hand, the bit string of the variable length code to be decoded is input from the (507) code input. This bit string is held in the (514) code input register.

(514) The code input register is a shift register and can shift an arbitrary number of bits. The variable length code held in the (514) code input register and the (512) variable length code output from the (510) code table RAM are respectively input to the (515) comparator. Here, the value of the (508) address counter is increased, and (510) the code table RAM.
The (512) variable-length code that is the output of the above is compared word by word from the head of the table by the (515) comparator. If a match between the values of the (510) code table RAM and the (514) code input register is detected by the (515) comparator, it means that the value of the (511) fixed length data at that time is the decoded value. become.

Therefore, at the output of the (515) comparator,
(516) The fixed length data output register is activated, (511) the fixed length data is held, and (51)
6) The value of the fixed length data output register is used as the decoded value.

At the same time, the output of the (515) comparator is
17) Activate the code length output register and set (51
3) Hold the code length.

This value is given to the (514) code input register as the number of shift bits, and the input variable length code of the (514) code input register is shifted by the number of bits of the decoded code. This is to set a new input variable length code and prepare for the next decoding.

With the above, one decoding is completed.
The same cycle is repeated as long as the variable length code continues.

FIG. 6 is a state transition diagram of the configuration of the first embodiment of the present invention in which the above operations are arranged.

In the present embodiment, when the encoding table of FIG. 5 is installed, the required memory amount is 33 words (depth 32 bits), which is 1056 bits. Further, since one code is stored in one word, it can be seen that there is no waste in using the memory. Therefore,
We were able to improve memory usage efficiency and save memory.

Further, since the fixed length data is written together with the variable length code, the arrangement order of the codes does not depend on the address and can be freely arranged. In this way, the codes can be arranged in the order of occurrence frequency as shown in FIG. At the time of decoding, since the evaluation is performed from the head of the table, it is possible to evaluate in the order of the code with the highest occurrence frequency, and the decoding time can be shortened extremely reasonably.

(Embodiment 2) This embodiment relates to claim 2 of the claims.

FIG. 3 is a block diagram showing the configuration of this embodiment.

Similar to (Example 1), the code table RA
In M (610), fixed length data (611) and variable length code (612) are written in pairs at the same address.

Further, the code length (613) corresponding to the variable length code (612) is also written in pairs at the same address.

FIG. 5 is a diagram showing the data contents of the code table RAM used in this embodiment as in the case of the first embodiment.

(610) By downloading these data to the code table RAM from the (601) download data bus, various variable length code tables can be supported.

Also, as long as the RAM capacity allows, a plurality of tables can be downloaded at once and used differently as in the case of the first embodiment.

Since the present embodiment relates to the coding of variable length codes, the coding operation will be described.

(608) The address counter is (61)
0) It is connected to the address input of the code table RAM and specifies the address of the code table RAM.

First, from the (603) set address bus, the start address of the code table to be decoded is (60
8) Load to the address counter.

On the other hand, from (607) code input, a bit string of fixed length data to be encoded is input. This bit string is held in the (614) data input register.

(614) The variable length code held in the data input register and (610) the fixed length data output from the code table RAM are (61)
5) Input to the comparator. Here, the value of the (608) address counter is increased, and (610) the fixed-length data output from the code table RAM (611) is compared word by word from the head of the table with a (615) comparator. To go.

If (610) code table RAM,
(614) If the values in the data input register match (615)
If detected by the comparator, the (612) variable-length code at that time is the encoded value.

Therefore, at the output of the (615) comparator,
(616) Activate the variable length code output register,
(612) Holds the variable length code, and further sets the value of the (616) variable length code output register as the encoded value.

At the same time, the output of the (615) comparator is
17) Activate the code length output register, and
3) Hold the code length. This value is given as the number of shift bits to the data buffer in the subsequent stage of the (618) variable length code output register. The above is one decoding, and the same cycle is repeated as long as the variable length code continues.

A summary of the above operation is a state transition diagram of the configuration of the second embodiment of the present invention in FIG.

In this embodiment, the encoding table shown in FIG. 5 can be mounted, which is exactly the same as the table structure of (Embodiment 1).

With the configuration of this embodiment, it was possible to perform encoding with the same code table as the decoding table.

(Embodiment 3) This embodiment relates to claim 3 of the claims.

FIG. 4 is a block diagram showing the configuration of this embodiment.

Similar to (Embodiment 1) and (Embodiment 2), fixed length data (711) and variable length code (712) are written in pairs at the same address in the code table RAM (710). There is. Furthermore, a variable length code (71
The code length (713) corresponding to 2) is also written in pairs at the same address.

FIG. 5 shows (Example 1) and (Example 2).
FIG. 7 is a diagram showing data contents of a code table RAM used in the present embodiment similarly to FIG.

First, the decoding operation of the variable length code will be described.

(720) The output of the multiplexer is changed to (7
12) If the variable length code is selected and the output of the (721) multiplexer is selected as the (711) fixed length data, the circuit configuration becomes similar to that of the first embodiment, and the decoding operation becomes possible.

Next, the encoding operation for the variable length code will be described.

(720) The output of the multiplexer is changed to (7
11) If fixed length data is selected and the output of the (721) multiplexer is selected as (712) variable length code, the circuit configuration becomes similar to that of the second embodiment, and the encoding operation becomes possible. .

As described above, in this embodiment, the coding table shown in FIG. 5 can be commonly used for decoding and coding, and decoding and coding can be performed by the same circuit.

(Embodiment 4) This embodiment relates to claim 4 of the claims.

FIG. 1 is a block diagram showing the configuration of this embodiment.

The (710) code table RAM used in the third embodiment and four sets of peripheral circuits such as the (715) comparator, the (720) multiplexer, and the (721) multiplexer are provided, and the encoding in the (715) comparator is performed. The decoding process is performed in parallel every 4 words. FIG. 8 is a diagram showing the data contents of the code table RAM used in this embodiment. The data contents of the code table RAM of FIG. 5 are distributed from the head to four tables.

Further, since the table is divided into four, the total amount of the table does not change.

With respect to the value of the (460) register, (44
0) code table RAM0, (441) code table R
AM1, (442) code table RAM2 and (44)
3) Evaluate the values in the code table RAM3 at once.

Coding / decoding is supported by switching the (451) multiplexer and (452) multiplexer in the same manner as in the third embodiment.

(433) When the value of the address counter is increased and one of the (715) comparators hits, the address counter is stopped, and (46)
1) The select control circuit controls the (454) multiplexer and the (455) multiplexer to output the correct encoded value / decoded value to the (465) code output and the code length to the (466) code length output.

As described above, in this embodiment,
Incorporating 4 sets of encoding / decoding circuits described in 3),
By operating in parallel, it was possible to realize four times faster speed than encoding / decoding.

Further, with the above configuration of the present invention, any number of sets of encoding / decoding circuits can be incorporated, and the speed can be increased by the number of sets.

[0073]

According to claim 1 of the present invention, since one code can be stored in one word, waste of memory usage can be eliminated and memory usage efficiency can be improved. I was able to save memory.

Further, since the fixed-length data is written together with the variable-length code, the code can be arranged freely without depending on the address, and the codes can be arranged in the order of occurrence frequency. Therefore, at the time of decoding, since the evaluation is performed from the head of the table, it is possible to evaluate in the order of the code having the highest occurrence frequency, and the decoding time can be shortened extremely reasonably.

According to the configuration of claim 2 of the present invention, the encoding can be performed by the same code table as the decoding table.

According to the configuration of claim 3 of the present invention, it is possible to perform encoding with the same code table as the decoding table, and to perform decoding with the same circuit, The encoding could be done.

According to the structure of claim 4 of the present invention, four sets of encoding / decoding circuits are incorporated,
By operating in parallel, it was possible to realize four times faster speed than encoding / decoding. Further, with the above configuration of the present invention, any number of sets of encoding / decoding circuits can be incorporated, and the speed can be increased by the number of sets.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a fourth embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a third embodiment of the present invention.

FIG. 5 is a diagram showing data contents of a code table RAM according to the first, second and third embodiments of the present invention.

FIG. 6 is a state transition diagram of the configuration of the first embodiment of the present invention.

FIG. 7 is a state transition diagram of the configuration of the second embodiment of the present invention.

FIG. 8 is a diagram showing data contents of a code table RAM according to a fourth embodiment of the present invention.

[Explanation of symbols]

60 Wait / Address Counter Clear State 61 Address Increment / Compare State 62 Register (516) (517) Latch State 63 Register (514) Value Shift State 70 Standby / Address Counter Clear State 71 Address Increment / Compare State 72 Register (616 ) (617) Latch state 73 Value input state to data buffer 401 Data bus for download 402 Write enable 403 Address bus for set 404 Counter enable 405 Counter load 406 Counter clear 407 Encoding / decoding selection 408 Code input 409 Forced selection 410 Ignore data 431 Write control 432 Write enable 433 Address counter 434 Address bus 435 Read enable 440 Code test Bull RAM0 441 Code table RAM1 442 Code table RAM2 443 Code table RAM3 451 Multiplexer 452 Multiplexer 453 Comparator 454 Multiplexer 455 Multiplexer 460 Register 461 Select control circuit 465 Code output 466 Code length output 501 Download data bus 502 Write enable 503 Set address Bus 504 Counter enable 505 Counter load 506 Counter clear 507 Code input 508 Address counter 509 Read enable 510 Code table RAM 511 Fixed length data 512 Variable length code 513 Code length 514 Code input register 515 Comparator 516 Fixed length data output register 517 Code length Output register 518 fixed Data output 601 Download data bus 602 Write enable 603 Set address bus 604 Counter enable 605 Counter load 606 Counter clear 607 Code input 608 Address counter 609 Read enable 610 Code table RAM 611 Fixed length data 612 Variable length code 613 Code length 614 Code Input register 615 Comparator 616 Variable length code output register 617 Code length output register 618 Variable length code output 619 Code length output 701 Download data bus 702 Write enable 703 Set address bus 704 Counter enable 705 Counter load 706 Counter clear 707 Code input 708 address counter 709 read enable 710 code table RAM 11 fixed length data 712 variable-length code 713 code length 714 code input register 715 comparator 716 variable-length code output registers 717 code length output register 718 variable-length code output 719 code length output 720 multiplexer 721 multiplexer

Claims (4)

[Claims] 1. A variable-length decoding device for decoding an input variable-length code bit string into a fixed-length code bit string with reference to a memory table, wherein the variable-length code bit string and the fixed-length code bit string corresponding to decoding are: Decoding memory tables arranged in pairs, further having a comparator for comparing the output of the memory table and the input variable length code bit string, and the memory table when the variable length code bit strings match in the comparator A fixed-length coded bit string of is output as a decoded value. 2. A variable-length coding device for coding an input fixed-length code bit string into a variable-length code bit string with reference to a memory table, wherein the fixed-length code bit string and the variable-length code bit string corresponding to coding are: A memory table having a pair of coded memory tables and a comparator for comparing the output of the memory table and the input fixed-length code bit string, and when the fixed-length code bit string matches in the comparator An encoding device which outputs the variable-length code bit string of 1 as an encoded value. 3. The encoding device according to claim 1 or 2, further comprising a selector for selecting a fixed length code bit string and a variable length code bit string of a memory table and inputting them to a comparator. An encoding device capable of switching between a fixed-length code bit string and a variable-length code bit string of a memory table to be input to the device. 4. The claim 1, claim 2 and claim 3.
The encoding device of claim 1, wherein a plurality of sets of memory tables and comparators are mounted.