KR20030071039A - System for data communication - Google Patents

Abstract

PURPOSE: A data communication system is provided to eliminate a load generated at a processor of a system controller by using a clock signal, which is used for a synchronization at a control instructor, as an operating signal, and to speedily check a wrong operation or an abnormal state. CONSTITUTION: The system comprises an interface logic circuit(21), the first shift register(25), the second shift register(27), and a counter(23). The interface logic circuit(21) includes a PPD(Pulse Position Data) terminal which converts a serial control signal and a parallel state signal, and transmits or receives the converted signals, and also includes a clock terminal which receives a clock signal. The first shift register(25) converts a parallel state signal into a serial state signal, and the second register(27) converts a serial control signal into a parallel state signal. The counter(23) counts a communication frequency of the control signal and the state signal.

Description

Data Communication System {SYSTEM FOR DATA COMMUNICATION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system, and more particularly, to a data communication system capable of preventing load on a processor arranged in a system by configuring hardware by EPLD.

In general, when a system arranged in one direction and a system arranged in another direction connected by a serial communication line transmit and receive data in both directions, the data to be transmitted and the received data are determined and transmitted through the serial communication line.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining a signal transmission relationship of a serial communication system used according to the prior art.

As shown in FIG. 1, a control indicator 1 confirms a state by a user and transmits a plurality of control signals, and transmits a state data signal applied from an external device to the control indicator 1, or controls the control indicator 1. Analyzing and controlling an interface 3 for receiving a control data signal generated by the indicator 1 and a signal applied to the control indicator 1 or a signal applied to the external device through the interface 3. It consists of the processor 5.

In the signal processing of the serial communication system having the above configuration, first, the system control signal generated from the control indicator 1 is the interface 3 which is a component of the system controller 10 in the form of Pulse Position Data (PPD). In this case, a clock signal is also applied to synchronize the signals. In the interface 3, the analog control signal is converted to digital, the processor 5 analyzes the control signal, and then applies a signal for controlling the external device.

The external device receiving the control signal generated from the control indicator 1 is controlled according to a control signal, and then applies a signal indicating the state to the processor 5, and the processor 5 analyzes the state signal. Then, transfer to the interface (3).

The status signal transmitted to the interface 3 is transferred from the analog form to the digital form and then transmitted to the control indicator 1.

As described above, a signal is transmitted and received between the control indicator 1 and the system controller 10 through a PPD, and the PPD has a total of 256 cycles in the form of a sine wave. The control signal generated in 1) is transmitted, and the status signal of the external device is transmitted to the control indicator 1 in the section after 17 cycles.

2 is a block diagram illustrating a signal processing process of a data communication system according to the prior art.

As shown in FIG. 2, a communication system that performs a signal interface of a system for serial data transmission and reception includes an interface logic circuit 11 for converting an analog signal into a digital signal and an external device applied to the interface (not shown). After converting the state data signal and the control signal applied from the control indicator (not shown), the CPU 13 for controlling the transmission range and the count signal and the state data signal of the external device is received and buffered or And a first buffer unit 17 for buffering the control signal of the control indicator to the external device, and a second buffer for buffering the control signal generated from the control indicator or the status data signal of the external device. Timing unit 19, the interface logic circuit 11, the first buffer unit 17 and the second buffer unit 19 It consists of the control signal to Tycho further 15 to be applied.

First, when a state data signal is input from the first buffer unit 17, the first buffer unit 17 transmits a state signal to the interface logic circuit 11. The interface logic circuit 11 converts a state signal into a digital signal under the control of the CPU 13, adjusts the counting time of the converted signals in the decoder 15, and then the second buffer unit 19. ) Is output to the control indicator. The control indicator displays the state of the external device to the user using an on / off lamp or the like.

Similarly, after the control signal generated from the control indicator is input to the second buffer unit 19, the control signal is transmitted to the first buffer unit 17 in the same manner as described above to transmit the control signal to the external device. Output

However, a communication system having a signal processing scheme as described above has a problem in that a separate CPU for controlling an input / output signal causes a large load on the processors used in the system controller, thereby lowering system efficiency and reliability.

In addition, when the input / output processor used in the interface of the system controller malfunctions or an error occurs, all of the status signals transmitted to the control indicator are blocked so that the user cannot know the state of the system controller in which the problem occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and is composed of EPLD by hardware independent of the system, and is generated in the processor of the system controller by using a clock signal used for synchronization in a control indicator as an operation signal. It is an object of the present invention to provide a data communication system capable of eliminating a load, and quickly checking for malfunctions and abnormalities.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining a signal transmission relationship of a serial communication system used according to the prior art.

2 is a block diagram illustrating a signal processing procedure of a data communication system according to the prior art.

3 is a block diagram illustrating a signal processing procedure of a data communication system according to the present invention.

4 illustrates a data communication system in accordance with the present invention.

5 is a graph showing signal waveforms generated in the data communication system according to the present invention;

* Description of the symbols for the main parts of the drawings *

21: interface logic circuit 23: counter

25: first shift register 27: second shift register

30: EPLD31: timing controller

32: first comparator 33: second comparator

34: third comparator

In order to achieve the above object, a data communication system according to the present invention,

An interface logic circuit having a PPD terminal for converting and transmitting a serial control signal and a parallel state signal and a clock terminal to which a clock signal is input;

A first shift register converting the parallel state signal into a serial state signal;

A second shift register converting the serial control signal into a parallel state signal; And

And a counter counting a transmission / reception period of the control signal and the status signal.

Here, the interface logic circuit includes a timing controller for controlling timing of an input clock signal;

A first comparator for applying a PPD control signal to the second shift register;

A second comparator for detecting a synchronous clock signal of the clock signal; And

And a third comparator for detecting a clock signal for detecting a frame start section of the serial control signal input to the PPD terminal.

According to the present invention, a signal processing circuit using EPLD is configured at an interface used for signal transmission between a control indicator and an external device, thereby removing the load generated from the processor, thereby improving the efficiency and reliability of the system.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a configuration of a data communication system according to the present invention.

As shown in FIG. 3, an interface logic circuit 21 for converting a control signal and a clock signal transmitted from a control indicator (not shown) and a status signal of an external device, and the interface logic circuit 21 and an external device. It is composed of an EPLD (30) for transmitting and receiving a state signal or a control signal of the control indicator.

The EPLD 30 includes a counter 23 to which a clock signal is applied and counted for signal synchronization, a first shift register 25 for converting and outputting a parallel state signal of the external device in series, and the control indicator. It consists of a second shift register 27 for converting the serial control signal generated by the parallel control signal to output.

4 is a detailed circuit diagram illustrating a configuration of a data communication system according to the present invention.

As shown in FIG. 4, the hardware configuration of the interface logic circuit 21 and the EPLD 30 is shown as a detailed circuit diagram of the block diagram shown in FIG. 3. The interface logic circuit includes a timing controller 31 for controlling a clock signal input while having the control indicator, a PPD terminal for transmitting and receiving a control signal and a status signal, and a clock terminal (CIU) for signal synchronization; It consists of comparators 32, 33, 34.

In addition, the EPLD 30 includes a first shift register 25 for converting a state parallel signal representing a state of an external device into a serial signal, and a parallel control signal for applying a serial control signal generated by the control indicator to the external device. And a second shift register 27 for converting to < RTI ID = 0.0 > < / RTI >

In the communication system having the above configuration, when the control signal is input from the PPD terminal, the second shift register 25 and the counter 23 are initialized via the third comparator 34. At this time, the counter starts counting by a clock signal applied from the control indicator. When the 16th clock appears, the timing controller 31 is switched on to operate the second shift register 27. You will receive the status signal of the external device. When the 80 th clock appears, the frame and signal are output from the counter 23, and the first and second registers 25 and 27 and the counter 23 are disabled.

When the first shift register 25 operates, the control signal generated by the control indicator is converted into a parallel data signal according to a clock signal. Similarly, when the second shift register 27 operates, the control signal is converted according to a clock signal. The parallel state signal generated by the external device is converted into a serial state signal.

Since the clock signal and the data signal have the same frequency and phase, when the data is read, the rising edge of the clock must be after the state change of the data, thereby sufficiently increasing the threshold voltage of the comparator. However, when writing data, lower the threshold voltage of the comparator so that the clock signal is not cut off.

5 is a graph illustrating signal waveforms generated in the data communication system according to the present invention.

As shown in FIG. 5, the signal waveform used in the circuit diagram of FIG. 4 is shown. When the clock signal is continuously input from the clock terminal of the interface, the control signal CIU PPD input from the PPD terminal is first displayed. The second shift register 27 converts a serial control signal into a parallel control signal together with a synchronous clock frame_sync for detecting a frame of input data, and outputs the serial control signal to an external device.

In the second shift register 27, the parallel state signal indicating the state of the external device is converted into a serial state signal by the clock signal described above, and is input to the control indicator through the PPD terminal.

As described in detail above, the present invention has the effect of removing the load generated on the processor by hardware configured according to the EPLD in the interface of the system controller in the serial communication system of the control indicator and the system controller.

In addition, it is displayed on the control indicator so that the user can recognize the malfunction and the process fault state occurring in the system controller can improve the efficiency and reliability of the system.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (2)

An interface logic circuit having a PPD terminal for converting and transmitting a serial control signal and a parallel state signal and a clock terminal to which a clock signal is input; A first shift register converting the parallel state signal into a serial state signal; A second shift register converting the serial control signal into a parallel state signal; And And a counter counting a transmission / reception period of the control signal and the status signal. The method of claim 1, The interface logic circuit includes a timing controller for controlling timing of an input clock signal; A first comparator for applying a PPD control signal to the second shift register; A second comparator for detecting a synchronous clock signal of the clock signal; And And a third comparator for detecting a clock signal for detecting a frame start section of a serial control signal input to the PPD terminal.