KR100200487B1 - A processor with a pipeline architecture - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit, and in particular, command storage means for inputting and storing a command, address storage means for storing a jump / call address by a jump / call command, and inputting the jump / call address to the program memory. If the instruction generated by the address generating means for generating the address signal and the instruction decoded by decoding the instruction is a jump / call instruction, the execution cycle number of the next fetched instruction is checked and the checked execution cycle jumps. Instruction decoding means for generating first to third control signals for holding execution of a call instruction, connected between said instruction storage means and instruction decoding means, and executing said fetched command in response to said first control signal; A first switching means, which is connected between said command storing means and said address storing means, Second switching means for extracting the jump / call address in response to a second control signal, and connected between the address storage means and an address generating means, and completion of execution of the fetched command in response to the third control signal And third switching means which are turned on later.

Description

Central processing unit with pipeline structure and jump / call execution method

The present invention relates to a central processing unit (CPU) having a pipelined structure and a jump / call execution method. In particular, the execution of an instruction having a multi-execution cycle fetched next upon execution of a jump / call instruction is performed. It relates to a central processing unit having a pipeline structure that can be performed and a jump / call execution method.

Jump / Call operations play an important role in executing programs on the CPU.

1A to 1F are timing diagrams for explaining a process of executing a program when a two-word jump / call instruction is generated in a conventional CPU having a three-stage pipeline structure. Figure 1b is a program address addr, 1c is a program fetch, 1d is a program decode, 1e is a program execution and 1f is a timing diagram representing a jump / call address, respectively. admit.

It is assumed that the process of executing instructions by the CPU consists of a three-stage pipeline structure of extract-decrypt-execute. At this time, when a jump / call instruction composed of two words occurs, the operation of the conventional CPU will be described as follows.

In step n of the program address shown in FIG. 1B, as shown in FIG. 1D, a jump / call command has occurred. As shown in FIG. 1d in step n + 1, the address at which the jump / call command is to be performed is momentarily loaded into a decoder (not shown). Then, the address shown in FIG. 1f generated by the jump / call instead of the step n + 3 shown in FIG. 1b that is sequentially returned after the jump / call command in which the instruction is performed is n steps is performed as a new program address. Loaded into the program address generator (not shown) of the CPU.

At this time, since the CPU has a pipelined structure, the processing operation of the program at the time of the jump / call does not occur until all the programs by the jump / call instruction are executed. Alternatively, a command that takes a plurality of cycles or consists of a plurality of words may not be performed after a jump / call operation. That is, if a number of cycles are required in the n + 2 step or a command of a word composed of a plurality of words is to be processed, a number of unprocessed steps in the program address n + 2 step by the jump / call instruction address coming in the next cycle There is a problem in that it takes several cycles or a command composed of a plurality of words is not continuously executed.

2a to 2f are timing diagrams for explaining a process of executing a program when a single word jump / call instruction is generated in a conventional CPU having a three-stage pipeline structure. FIG. 2a is a system clock. 2b is a program address addr, 2c is a program fetch, 2d is a program decode, 2e is a program execution and 2f is a timing diagram indicating a jump / call address, respectively. .

If a one word instruction / call instruction occurs, the following problems are encountered as in the case where a two word instruction / call instruction occurs.

For example, the same problem occurs when a command composed of all cycles or words is input except for the case where a command of two cycles or two words enters the program address n + 1 shown in FIG. 2B.

SUMMARY OF THE INVENTION An object of the present invention is to provide a central processing apparatus having a pipeline structure that can continuously process an instruction having a multi-execution cycle currently fetched when a jump / call operation occurs while executing a program in order to solve the conventional problems as described above. And a jump / call execution method.

In order to achieve the above object, the apparatus of the present invention is a central processing unit having a pipelined structure that executes in a pipelined manner by inputting a command from a program memory for storing a system program, the input is stored from the program memory Instruction storage means for performing; Address storage means for storing a jump / call address by a jump / call command; Address generating means for inputting the jump / call address to generate an address signal of the program memory; When the decoded instruction is a jump / call instruction, the instruction provided from the instruction storage means checks the execution cycle number of the next fetched instruction and holds the execution of the jump / call instruction by the checked execution cycle number. Command decoding means for generating first to third control signals; First switching means connected between the command storing means and the command decoding means, the first switching means being turned off during execution of the fetched command in response to the first control signal; Second switching means connected between the command storing means and the address storing means and extracting the jump / call address in response to the second control signal; And first switching means connected between the address storing means and the address generating means and turned on after completion of execution of the fetched command in response to the third control signal.

In addition, the method of the present invention includes a jump / call execution method of a CPU having a pipeline structure, the method comprising: checking whether a jump / call command is obtained by decrypting a fetched command; Storing a jump / call address in the case of the jump / call command; Decrypting the instruction fetched next to the jump / call instruction to check the number of execution cycles; Holding execution of a jump / call instruction by the checked execution cycle number and executing a decrypted instruction; And when the execution of the command is completed, reading the stored jump / call address to generate an address signal for designating an address to jump / call to the program memory.

1A to 1F are timing diagrams for explaining a process of executing an instruction when a two word jump / call instruction is generated in a conventional CPU.

2A to 2F are timing diagrams for explaining a process of executing an instruction when a jump / call instruction of one word occurs in a conventional CPU.

3 is a block diagram of a CPU according to the present invention.

4A to 4J are timing diagrams of respective parts and the switching signal of the apparatus shown in FIG.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the control device of the CPU according to the present invention and the program execution method performed in the control device will be described as follows.

3 is a schematic block diagram of a CPU control apparatus according to the present invention, which includes a command storage unit 202 for inputting and storing a command from a program memory 100, and an address storage unit 204 for storing a jump / call address. And an address generator 206 for inputting a jump / call address, generating an address signal, and outputting the address signal to the program memory 100, and program data stored in the instruction storage unit 202 in response to the first control signal S1. The first switching unit 208 for outputting the signal and the second switching unit 210 for outputting the jump / call address of the command storage unit 202 to the address storage unit 204 in response to the second control signal (S2). And from the third switching unit 212 and the first switching unit 208 outputting the jump / call address stored in the address storage unit 204 to the address generator 206 in response to the third control signal S3. Decode the command provided to output the system control signal (OUT), and in response to the cycle number and configuration number of words required to process the command consists of the first to third control signals (S1, S2 and S3), the command decoder 260 for outputting.

The command decryption unit 260 shown in FIG. 3 responds to the number of cycles required for processing the program data and the number of constituent words of the data decryption unit 214 and the data decryption unit 214, which decrypts the program data and outputs a control signal. And a jump / call holding control unit 216 for outputting the first to third control signals S1, S2, and S3.

4A to 4J are timing diagrams of respective parts and switching signals of the apparatus shown in FIG. 3, FIG. 4A is a system clock, FIG. 4B is a program address output from the address generator 206, and FIG. 4C is a command. Program extraction of the storage unit 202, FIG. 4d is the program decryption of the data decryption unit 214, FIG. 4e is the program execution, 4f is the second control signal (S2), 4g is the address storage unit 204 Command storage, FIG. 4h is a third switching signal S3, FIG. 4i is a timing diagram for explaining the counting operation of the jump / call holding controller 216, respectively.

First, FIG. 3 shows a control unit of the CPU showing an example in which an instruction requiring M cycles is performed after a jump / call instruction when the jump / call address has two words.

The control signal generator 216 shown in FIG. 3 inputs N bits of program data to determine how many cycles an instruction requires, and whether the instruction requires multiple cycles or multiple words. Determine whether it is made of. If an instruction requires multiple cycles or consists of multiple words, set the number of cycles required to process the instruction, reduce the count value, perform the instruction requiring multiple cycles, and count values. When this becomes 0, a third control signal is generated. That is, the third control signal S3 from the control signal generator 216 so that the address to which the jump / call command is to be performed after the program address n + 1 + M is transmitted from the address storage unit 204 to the address generator 206. Is output.

In addition, the jump / call holding control unit 216 generates the first control signal S1 so that the program data output from the command storage unit 202 is output to the data decoding unit 214. This means that, for example, if the command extracted by the program address n + 2 shown in FIG. 4B is a command consisting of a plurality of cycles or words taking M cycles, the program address n + 3 to the program address n + 1. The command embedded in the program memory 100 is extracted by the program address up to + M and input to the command storage unit 202, but the program data is controlled by the data decoding unit 214 by controlling the first control signal S1. This is to prevent entry. Therefore, the instruction generated by the program address n + 2 is held in the instruction storage unit 202.

In addition, the jump / call holding controller 216 generates a jump / call command in step n of the program address, and the address storage unit 204 causes the address value to jump by the second control signal S2 to be jumped by the jump / call command. Is loaded.

If the instruction fetched by the program address (n + 1) is a multi-cycle or multi-word that takes M cycles, the program memory is stored by the program address from the program address (n + 3) to the program address (n + 1 + M). The built-in command is fetched and output from the command storage unit 220, but the control signal S1 is not generated and thus is not input to the command decoder 260. Therefore, in the sanicle after (n + 1 + M) at the program address maintained in the instruction instruction decoder 260 generated by the program address (n + 2), the address where the jump / call is to be performed is the instruction decoder 260. Is output from the address storage section 204 to the address generation section 206 by the control signal S3 generated in the " The new program address continuously performs normal operation.

As described above, the CPU control apparatus and the program execution method executed by the control apparatus according to the present invention do not interrupt the program processing operation even if a jump / call instruction occurs during program execution, and the required cycle number or configuration of the program. By executing the program command being processed irrespective of the number of words, there is an effect of increasing the processing efficiency by preventing the central processing unit from stopping the operation.

Claims (3)

11. A central processing unit having a pipelined structure for inputting a command from a program memory for storing a system program to execute in a pipelined manner, comprising: command storage means for inputting and storing a command from the program memory; Address storage means for storing a jump / call address by a jump / call instruction; Address generating means for inputting the jump / call address to generate an address signal of the program memory; When the decoded instruction is a jump / call instruction, the instruction provided from the instruction storage means checks the execution cycle number of the next fetched instruction and holds the execution of the jump / call instruction by the checked execution cycle number. Command decoding means for generating first to third control signals; First switching means connected between the command storing means and the command decoding means, the first switching means being turned off during execution of the fetched command in response to the first control signal; Second switching means connected between the command storing means and the address storing means and extracting the jump / call address in response to the second control signal; And first switching means connected between the address storing means and the address generating means and turned on after completion of execution of the fetched command in response to the third control signal. Processing unit. 2. The apparatus of claim 1, wherein the command decrypting means comprises: data decrypting means for decrypting the command and outputting a corresponding system control signal; And jump / call holding control means for generating said first to third control signals in response to a system control signal of said data decryption means. CLAIMS 1. A jump / call execution method of a central processing unit having a pipeline structure, comprising: checking whether a jump / call command is obtained by decoding a fetched command; Storing a jump / call address in the case of the jump / call command; Decrypting the instruction fetched next to the jump / call instruction to check the number of execution cycles; Holding execution of a jump / call instruction by the checked execution cycle number and executing a decrypted instruction; And when the execution of the command is completed, reading the stored jump / call address and generating an address signal for designating an address to jump / call to a program memory.