JPH07263469A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07263469A JPH07263469A JP7946294A JP7946294A JPH07263469A JP H07263469 A JPH07263469 A JP H07263469A JP 7946294 A JP7946294 A JP 7946294A JP 7946294 A JP7946294 A JP 7946294A JP H07263469 A JPH07263469 A JP H07263469A
- Authority
- JP
- Japan
- Prior art keywords
- brazing material
- semiconductor chip
- semiconductor device
- chip
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体チップを金属又
は熱良伝導性のセラミック等の部材にろう付けする場
合、又は金属基板とセラミックとの間をろう付け時ろう
材層に発生するボイドを小さくし、熱の局部集中を抑制
する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a void generated in a brazing material layer when a semiconductor chip is brazed to a member such as a metal or a ceramic having good thermal conductivity, or between a metal substrate and the ceramic. The present invention relates to a semiconductor device in which the temperature is reduced and local concentration of heat is suppressed.
【0002】[0002]
【従来の技術】従来、この種の半導体チップと電極とな
る金属又は熱良伝導性のセラミック等の部材1との間を
ろう付けする半導体装置は、図4に示すような部材によ
り作られていた。すなわち、ベースとなる部材1上にペ
ーストを含まず半導体チップとほぼ同じ寸法でペレット
状に成形されたろう材2を搭載し、このろう材2上に半
導体チップ3を搭載し、位置決めした状態でろう材の融
点より数度〜数十度高い不活性雰囲気又は還元性雰囲気
中でろう材を溶着し、冷却固化されている。2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor chip of this type and a member 1 made of a metal or a ceramic having good thermal conductivity is used as an electrode is made of a member as shown in FIG. It was That is, a soldering material 2 which is formed into a pellet shape and has substantially the same size as a semiconductor chip without containing a paste is mounted on a member 1 serving as a base, and a semiconductor chip 3 is mounted on the soldering material 2 and the soldering state is maintained. The brazing material is welded in an inert atmosphere or a reducing atmosphere having a temperature of several degrees to several tens of degrees higher than the melting point of the material, and is cooled and solidified.
【0003】[0003]
【発明が解決しようとする課題】しかし、ペレット状に
形成されたろう材を用いた場合、リフロー工程におい
て、ろう材が溶ける際に半導体チップや部材表面とろう
材のなじみ性の微妙な差異によって図5に示すようにボ
イド4を含んだまま溶着される場合が多くみられた。こ
のボイドは、半導体チップと部材との間の機械的強度を
失うだけでなく、半導体装置の使用時において半導体チ
ップの熱がボイドによって放熱できず、熱が局部集中し
部分的加熱が生じ、許容電流を低減させなければ半導体
装置が破損するという問題があった。However, when a brazing filler metal formed into a pellet shape is used, when the brazing filler metal is melted in the reflow process, the difference in the compatibility between the semiconductor chip or member surface and the brazing filler metal causes As shown in Fig. 5, there were many cases where welding was performed with the void 4 included. This void not only loses the mechanical strength between the semiconductor chip and the member, but the heat of the semiconductor chip cannot be dissipated by the void when the semiconductor device is used, and the heat is locally concentrated and partial heating occurs, which is not allowed. There is a problem that the semiconductor device is damaged unless the current is reduced.
【0004】本発明はこの問題に留意し、ろう材形状を
改善してボイド発生を抑制しようとすものである。In view of this problem, the present invention intends to improve the shape of the brazing material and suppress the generation of voids.
【0005】[0005]
【課題を解決するための手段】すなわち、本発明は半導
体チップとこの半導体チップを固定する部材との間を第
1のろう材によって接続する半導体装置において、上記
ろう材が球状に成形されたろう材を使用したものであ
る。That is, according to the present invention, in a semiconductor device in which a semiconductor chip and a member for fixing the semiconductor chip are connected by a first brazing material, the brazing material in which the brazing material is formed into a spherical shape. Is used.
【0006】また、両面に金属層を有し、一方の面に半
導体チップがろう付けされたセラミックと、金属基板と
の間を第2のろう材によって接続する半導体装置におい
て、上記第2のろう材が球状に成形されたろう材を使用
したものである。Also, in the semiconductor device in which the ceramic having the metal layers on both surfaces and the semiconductor chip being brazed on one surface is connected to the metal substrate by the second brazing material, the second brazing material is used. The material is a brazing material formed into a spherical shape.
【0007】また、第2のろう材が表面にのみペースト
が設けられたろう材である。Further, the second brazing material is a brazing material in which the paste is provided only on the surface.
【0008】また、上記半導体チップのほぼ中央部に対
応する部材位置に第1のろう材の位置決め用凹部を設け
たものであり、また、上記金属基板又は上記セラミック
の少なくとも1つに上記第2のろう材の位置決め用凹部
を設けたものである。Also, a positioning recess for the first brazing material is provided at a member position corresponding to substantially the center of the semiconductor chip, and the second solder is provided on at least one of the metal substrate and the ceramic. The brazing material is provided with a positioning recess.
【0009】[0009]
【作用】半導体チップと部材との間に球状に成形された
ろう材を使用しているため、ろう材の溶融時、球状ろう
材と半導体チップ及び球状ろう材と部材とが接続する部
分から周囲にろう材が広がるので、ボイドの発生を抑制
することができる。[Function] Since the spherically shaped brazing filler metal is used between the semiconductor chip and the member, when the brazing filler metal is melted, the spherical brazing filler metal and the semiconductor chip and the spherical brazing filler metal and the member are connected to the surrounding area. Since the brazing material spreads, the generation of voids can be suppressed.
【0010】また、ろう付けされたセラミックと金属基
板との間に球状に成形されたろう材を使用しているた
め、ろう材の溶融時、球状ろう材とセラミック及び球状
ろう材と金属基板とが接する部分から周囲に広がるので
ボイドを抑制することができる。Further, since the spherically shaped brazing material is used between the brazed ceramic and the metal substrate, the spherical brazing material and the ceramic and the spherical brazing material and the metallic substrate are melted when the brazing material is melted. Since it spreads from the contacting part to the periphery, voids can be suppressed.
【0011】また、球状のろう材が表面のみペーストが
設けられているので、セラミックと金属基板の接着が容
易でペーストによるガスは球状ろう材が溶けるに従っ
て、外側に送り出されるのでボイドの発生が抑制され
る。Further, since the paste is provided only on the surface of the spherical brazing material, the ceramic and the metal substrate can be easily adhered, and the gas due to the paste is sent to the outside as the spherical brazing material melts, so that the generation of voids is suppressed. To be done.
【0012】部材,金属基板,セラミックのほぼ中央に
凹部を設け、球状ろう材の位置決めを行うことができ、
ろう材と接する部材は中央から周囲に広がるので、ろう
付けを均等に行うことができまた、ボイドの発生が抑制
される。By providing a recess in the center of the member, the metal substrate, and the ceramic, the spherical brazing material can be positioned.
Since the member in contact with the brazing material spreads from the center to the periphery, brazing can be performed uniformly and the generation of voids is suppressed.
【0013】[0013]
【実施例】以下、この発明を実施例を示した図1乃至図
3に基づいて説明する。図1において、3は半導体チッ
プ、1は電極となる金属、モリブデン・タングステン等
のような半導体チップと金属基板との熱緩衝用金属、両
面に金属層を有し半導体チップと金属基板を絶縁させる
熱良伝導性のセラミック等の部材であり、この半導体チ
ップ3のほぼ中央部に対応する部材位置に凹部6が設け
られている。5はサッカーボール又はラグビーボール等
の球状のろう材である。そして、ベースの部材1上の凹
部6に球状のろう材5を搭載し、このろう材の上部に半
導体チップ3を搭載する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. In FIG. 1, 3 is a semiconductor chip, 1 is a metal serving as an electrode, metal for heat buffering between a semiconductor chip and a metal substrate, such as molybdenum / tungsten, etc., having metal layers on both sides to insulate the semiconductor chip and the metal substrate. The member 6 is a member having good thermal conductivity such as ceramics, and the recess 6 is provided at a member position corresponding to substantially the center of the semiconductor chip 3. Reference numeral 5 is a spherical brazing material such as a soccer ball or a rugby ball. Then, the spherical brazing filler metal 5 is mounted in the recess 6 on the base member 1, and the semiconductor chip 3 is mounted on the upper portion of the brazing filler metal.
【0014】このようにして、図2(a)に示すように
位置決めした状態でろう材の融点より数度〜数十度高い
不活性雰囲気又は還元雰囲気中でろう材を加熱すると、
同図(b)に示すようにろう材の外側から溶解する。ろ
う材5全体が溶解すると同図(c)及び(d)に示すよ
うに部材1及び半導体チップ3と接触する部分は半導体
チップ3の下部の中央から周囲に広がり、ついには半導
体チップと部材の端部で表面張力によって安定する。そ
して、同図(e)に示すように半導体チップ全面に溶融
したろう材が行き渡り、冷却固定させる。In this way, when the brazing material is heated in an inert atmosphere or a reducing atmosphere, which is several degrees to several tens of degrees higher than the melting point of the brazing material in the state of being positioned as shown in FIG. 2A,
As shown in FIG. 3B, the brazing material melts from the outside. When the entire brazing filler metal 5 is melted, the portion contacting the member 1 and the semiconductor chip 3 spreads from the center of the lower portion of the semiconductor chip 3 to the periphery as shown in FIGS. Stabilizes at the edges by surface tension. Then, as shown in FIG. 3E, the molten brazing material is spread over the entire surface of the semiconductor chip and is cooled and fixed.
【0015】これによって、ろう材の溶融時球状ろう材
5と半導体チップ3及び球状ろう材5と部材1とが接す
る部分から周囲にろう材が広がるので、ボイドが抑制さ
れる。なお、球状ろう材3の量は半導体チップ3と部材
1とが十分な機械的接続が得られる厚みを持ち、かつ、
ろう材層の熱抵抗が小さい薄い厚みを有する量が選ばれ
る。As a result, when the brazing material is melted, the brazing material spreads from the portion where the spherical brazing material 5 contacts the semiconductor chip 3 and the spherical brazing material 5 and the member 1 to the surroundings, so that voids are suppressed. The amount of the spherical brazing filler metal 3 has such a thickness that the semiconductor chip 3 and the member 1 can have a sufficient mechanical connection, and
An amount is chosen that has a low thickness and a low thermal resistance of the braze material layer.
【0016】図3は他の実施例であり、図1のものと異
なる点は、球状のろう材5に金平糖のように角5aを設
けたものである。この角を有する球状ろう材は、半導体
チップ3,部材1の位置決めを容易にするとともに、半
導体チップ3を角5aによって支持することができる。
半導体チップと部材の位置決め後、加熱すると球状の角
も溶融する。この時、表面張力によって溶融された角は
球状ろう材本体に吸収され、角によるボイド発生はな
い。また、角を設けることにより、部材に位置決め用の
凹部を除くこともできる。FIG. 3 shows another embodiment, which is different from that shown in FIG. 1 in that a spherical brazing filler metal 5 is provided with corners 5a like Konpeito. The spherical brazing material having the corners facilitates the positioning of the semiconductor chip 3 and the member 1, and can support the semiconductor chip 3 by the corners 5a.
When the semiconductor chip and the member are positioned and heated, the spherical corners are also melted. At this time, the corner melted by the surface tension is absorbed by the spherical brazing filler metal body, and no void is generated by the corner. Further, by providing the corner, the concave portion for positioning can be removed from the member.
【0017】なお、上記実施例は、球状のろう材にはペ
ーストが含まれていないろう材であるが、球状のろう材
の表面にのみペーストを設けることもできる。これによ
ると、部材どうし例えば熱緩衝材とセラミック、セラミ
ックと金属基板のろう付けが容易になる。また、ペース
トによるガスは球状のろう材が溶融するに従って外側に
送り出されるので、ボイドの発生が抑制される。また、
上記実施例では金属又は両面に金属層を有するセラミッ
ク等の半導体チップを固定する部材と半導体チップの間
のろう付けについて説明したが、半導体チップを固定し
たセラミックとこれを支持する金属基板との間のろう付
けにも適用できる。また、上記実施例は半導体チップ1
つに対し、部材1について対応させていたが、1つの部
材に複数の半導体チップをろう付けすることもできる。In the above embodiment, the spherical brazing filler metal does not contain the paste, but the paste can be provided only on the surface of the spherical brazing filler metal. This facilitates the brazing of the members to each other, for example, the heat buffer material and the ceramic, and the ceramic and the metal substrate. Further, since the gas generated by the paste is sent to the outside as the spherical brazing material melts, the generation of voids is suppressed. Also,
In the above embodiment, the brazing between the semiconductor chip and a member for fixing the semiconductor chip such as metal or ceramic having metal layers on both sides has been described, but between the ceramic to which the semiconductor chip is fixed and the metal substrate supporting the same. It can also be applied to brazing. In addition, the above embodiment is the semiconductor chip 1.
On the other hand, although the member 1 is dealt with, a plurality of semiconductor chips can be brazed to one member.
【0018】[0018]
【発明の効果】この発明によれば、ろう材に球状に成形
されたろう材を使用することにより、ろう材と半導体チ
ップ及びろう材と部材とが接する部分から周囲にろう材
が広がりボイドの発生を抑制することができる。また、
球状ろう材の表面のみペーストが設けられているので、
セラミックと金属基板の接着が容易になり、ペーストに
よるガスが球状ろう材の溶けるに従い外部に送り出さ
れ、ボイドの発生が抑制される。また、部材に設けた凹
部にろう材を係合させることにより、半導体チップと部
材の位置決めが容易となる。According to the present invention, by using a spherically shaped brazing material as the brazing material, the brazing material spreads from the portion where the brazing material and the semiconductor chip and the brazing material and the member are in contact with each other to the occurrence of voids. Can be suppressed. Also,
Since the paste is provided only on the surface of the spherical brazing material,
The bonding between the ceramic and the metal substrate becomes easy, and the gas due to the paste is sent out as the spherical brazing material melts, and the generation of voids is suppressed. Further, by engaging the brazing material with the concave portion provided in the member, the semiconductor chip and the member can be easily positioned.
【図1】本発明の半導体装置の一実施例の概略斜視図で
ある。FIG. 1 is a schematic perspective view of an embodiment of a semiconductor device of the present invention.
【図2】(a)ないし(e)は、この発明の半導体装置
製造工程説明図である。2 (a) to (e) are explanatory views of a semiconductor device manufacturing process of the present invention.
【図3】本発明の半導体装置の他の実施例の概略斜視図
である。FIG. 3 is a schematic perspective view of another embodiment of the semiconductor device of the present invention.
【図4】従来の半導体装置の概略斜視図である。FIG. 4 is a schematic perspective view of a conventional semiconductor device.
【図5】従来の半導体装置ろう付け後の概略図である。FIG. 5 is a schematic view after brazing of a conventional semiconductor device.
1 部材 3 半導体チップ 5 球状ろう材 6 凹部 1 Member 3 Semiconductor Chip 5 Spherical Brazing Material 6 Recess
Claims (6)
する部材との間を第1のろう材によって接続する半導体
装置において、上記ろう材が球状に形成されたろう材を
使用したことを特徴とする半導体装置。1. A semiconductor device for connecting a semiconductor chip and a member for fixing the semiconductor chip by a first brazing material, wherein the brazing material is a spherical brazing material. apparatus.
るセラミックである請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the member is a metal or a ceramic having metal layers on both sides.
る部材位置に上記ろう材の位置決め用凹部を設けた請求
項1記載の半導体装置。3. The semiconductor device according to claim 1, wherein a positioning recess for the brazing material is provided at a member position corresponding to substantially the center of the semiconductor chip.
ップをろう付けされたセラミックと、金属基板との間を
第2のろう材によって接続する半導体装置において、上
記第2のろう材が球状に成形されたろう材を使用したこ
とを特徴とする半導体装置。4. A semiconductor device in which a ceramic having a metal layer on both sides and a semiconductor chip being brazed on one side is connected to a metal substrate by a second brazing material, wherein the second brazing material is used. A semiconductor device characterized in that a brazing material formed into a spherical shape is used.
が設けられたろう材である請求項4記載の半導体装置。5. The semiconductor device according to claim 4, wherein the second brazing material is a brazing material in which a paste is provided only on the surface.
くとも1つに上記第2のろう材の位置決め用凹部を設け
た請求項1記載の半導体装置。6. The semiconductor device according to claim 1, wherein at least one of the metal substrate and the ceramic is provided with a recess for positioning the second brazing material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7946294A JPH07263469A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7946294A JPH07263469A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07263469A true JPH07263469A (en) | 1995-10-13 |
Family
ID=13690556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7946294A Pending JPH07263469A (en) | 1994-03-24 | 1994-03-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07263469A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
WO2011010450A1 (en) * | 2009-07-24 | 2011-01-27 | パナソニック株式会社 | Semiconductor component, semiconductor wafer component, method for manufacturing semiconductor component, and method for manufacturing bonded structural body |
-
1994
- 1994-03-24 JP JP7946294A patent/JPH07263469A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7601625B2 (en) | 2004-04-20 | 2009-10-13 | Denso Corporation | Method for manufacturing semiconductor device having solder layer |
WO2011010450A1 (en) * | 2009-07-24 | 2011-01-27 | パナソニック株式会社 | Semiconductor component, semiconductor wafer component, method for manufacturing semiconductor component, and method for manufacturing bonded structural body |
CN102422403A (en) * | 2009-07-24 | 2012-04-18 | 松下电器产业株式会社 | Semiconductor component, semiconductor wafer component, method for manufacturing semiconductor component, and method for manufacturing bonded structural body |
JP5351267B2 (en) * | 2009-07-24 | 2013-11-27 | パナソニック株式会社 | Semiconductor component, semiconductor wafer component, semiconductor component manufacturing method, and junction structure manufacturing method |
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