JPH10321633A - Bump formation - Google Patents

Bump formation

Info

Publication number
JPH10321633A
JPH10321633A JP9132079A JP13207997A JPH10321633A JP H10321633 A JPH10321633 A JP H10321633A JP 9132079 A JP9132079 A JP 9132079A JP 13207997 A JP13207997 A JP 13207997A JP H10321633 A JPH10321633 A JP H10321633A
Authority
JP
Japan
Prior art keywords
bump
chip
copper
solder
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9132079A
Other languages
Japanese (ja)
Other versions
JP3564944B2 (en
Inventor
Tadahiko Sakai
忠彦 境
Hideki Nagafuku
秀喜 永福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13207997A priority Critical patent/JP3564944B2/en
Publication of JPH10321633A publication Critical patent/JPH10321633A/en
Application granted granted Critical
Publication of JP3564944B2 publication Critical patent/JP3564944B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a bump formation method which forms a high bump on an aluminum electrode of a chip, without reducing junctional strength of the chip after soldering. SOLUTION: A copper bump 4 is formed by wire bonding on an aluminum electrode 2 of a chip 1, and a distal end of the copper bump 4 is pressed to have a flat surface. A gold bump 7 is formed by wire bonding on the flat surface. When the bump comprising the copper bump 4 and the gold bump 7 is soldered to an electrode 12 of a substrate 11, the content of solder 13 such as tin which diffuses in the gold bump 7 is blocked by the copper 4 and it does not reach the aluminum electrode 2. Accordingly, formation of alloy layer of aluminum and tin which may deteriorate the junctional strength is avoided. Further, as the solder 13 is prevented by an oxide film on the surface of the copper bump 4 and it does not reach the electrode 2, corrosion due to the solder 13 does not occur in the aluminum electrode 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、チップのアルミ電
極上にバンプを形成するバンプの形成方法に関する。The present invention relates to a bump forming method for forming a bump on an aluminum electrode of a chip.

【０００２】[0002]

【従来の技術】フリップチップなどのチップを基板に接
合するために、チップの電極上にバンプを形成する方法
が知られている。そしてチップを基板に実装する際に
は、このバンプは基板の電極に半田付けされる。従来、
チップの電極としてはアルミ電極が多用されており、ま
たバンプとしては金バンプが多用されている。2. Description of the Related Art In order to join a chip such as a flip chip to a substrate, there is known a method of forming a bump on an electrode of the chip. When mounting the chip on the substrate, the bumps are soldered to the electrodes of the substrate. Conventionally,
Aluminum electrodes are frequently used as chip electrodes, and gold bumps are frequently used as bumps.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、アルミ
電極上に金バンプを形成し、この金バンプを半田付けす
る場合には、以下に述べるような接合強度の劣化が生じ
やすい。すなわち、金バンプを半田付けすると半田中の
錫等の成分は金バンプ中に拡散する。そして時間の経過
とともにこれらの成分はアルミ電極と金バンプの界面ま
で到達し、そこで錫はアルミとの合金を形成する。とこ
ろがこの錫とアルミの合金は脆いため、アルミ電極と金
バンプの界面に沿ってこの合金層が形成されると、接合
強度を劣化させることになる。そして、チップが使用さ
れる環境によっては基板とチップとの熱膨張率の差に起
因する熱応力が繰り返し作用し、いわゆるヒートサイク
ルによってこの接合強度が劣化した部分が破断する場合
があるという問題点があった。However, when a gold bump is formed on an aluminum electrode and this gold bump is soldered, the bonding strength tends to deteriorate as described below. That is, when the gold bump is soldered, components such as tin in the solder diffuse into the gold bump. Over time, these components reach the interface between the aluminum electrode and the gold bumps, where tin forms an alloy with aluminum. However, since the alloy of tin and aluminum is brittle, if this alloy layer is formed along the interface between the aluminum electrode and the gold bump, the bonding strength will be degraded. Then, depending on the environment in which the chip is used, the thermal stress caused by the difference in the coefficient of thermal expansion between the substrate and the chip repeatedly acts, and a portion where the bonding strength is deteriorated by a so-called heat cycle may be broken. was there.

【０００４】そこで従来は、金バンプを形成する以前の
半導体ウェハ工程において、チップの表面に半田ぬれ性
がよい銅などの金属層をバリヤ層として形成し、この金
属層のうち、アルミ電極以外の部分をエッチングで取り
除いて電極を形成させることが行われていた。しかしな
がらこのような方法では、チップの表面に金属層を形成
したり、また金属層をエッチングにより除去して電極を
形成させる工程が新たに必要であるため、工程が面倒で
あって生産性が上がらず、またコストアップにもなると
いう問題点があった。Therefore, conventionally, in a semiconductor wafer process before forming a gold bump, a metal layer of copper or the like having good solder wettability is formed as a barrier layer on the surface of a chip. An electrode is formed by removing a portion by etching. However, such a method requires a new step of forming a metal layer on the surface of the chip or removing the metal layer by etching to form an electrode, which is cumbersome and increases productivity. In addition, there is a problem that the cost increases.

【０００５】ところで、フリップチップなどバンプ付き
のワークを基板に半田付けする場合、バンプの高さはよ
り高いことが望まれる。これは、高いバンプの方が半田
付け後に基板とチップの熱膨張の差によって生じる熱変
形をより吸収しやすいこと、また基板のうねりなどによ
る高低差をより吸収できることによる。[0005] When soldering a work having a bump such as a flip chip to a substrate, it is desired that the height of the bump be higher. This is because higher bumps can more easily absorb thermal deformation caused by the difference in thermal expansion between the substrate and the chip after soldering, and can more effectively absorb height differences due to undulation of the substrate.

【０００６】そこで本発明は、半田付け後に接合強度の
劣化を生じることがなく、しかも高さの高いバンプを形
成することができるバンプの形成方法を提供することを
目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a bump forming method capable of forming a tall bump without causing deterioration in bonding strength after soldering.

【０００７】[0007]

【課題を解決するための手段】本発明のバンプの形成方
法は、チップのアルミ電極上にワイヤボンディングによ
って銅バンプを形成し、次にこの銅バンプを上面から押
圧することにより銅バンプにフラット面を形成した後、
このフラット面上にワイヤボンディングにより金バンプ
を形成するようにした。According to the bump forming method of the present invention, a copper bump is formed on an aluminum electrode of a chip by wire bonding, and then the copper bump is pressed from the upper surface to form a flat surface on the copper bump. After forming
Gold bumps were formed on the flat surface by wire bonding.

【０００８】[0008]

【発明の実施の形態】上記構成の本発明によれば、チッ
プのアルミ電極上にワイヤボンディングによって銅バン
プを形成し、この銅バンプ上にワイヤボンディングによ
り金バンプを形成するようにしたので、半田中の錫は銅
バンプによって拡散が抑制されアルミ電極には到達せ
ず、したがって強度劣化の原因となる錫とアルミの合金
層が形成されることがない。また銅バンプと金バンプの
高さが加え合わされるため全体として高さの高いバンプ
が形成できる。According to the present invention having the above construction, a copper bump is formed on an aluminum electrode of a chip by wire bonding, and a gold bump is formed on the copper bump by wire bonding. The diffusion of tin inside is suppressed by the copper bumps and does not reach the aluminum electrode, so that an alloy layer of tin and aluminum, which causes deterioration in strength, is not formed. In addition, since the heights of the copper bump and the gold bump are added, a high bump can be formed as a whole.

【０００９】次に、本発明の実施の形態を図面を参照し
て説明する。図１（ａ）、（ｂ）、（ｃ）は本発明の一
実施の形態のチップの部分断面図、図２（ａ）、（ｂ）
は、同チップおよび基板の部分断面図である。まず、バ
ンプの形成方法について、図１を参照して説明する。図
１（ａ）〜（ｃ）は、バンプの形成工程を工程順に示し
たものである。図１（ａ）において、チップ１の上面に
はアルミ電極２が形成されており、電極２の周辺には絶
縁膜３が形成されている。まず電極２上にワイヤボンデ
ィングにより銅バンプ４が形成される。５は、ワイヤボ
ンディング時に生じるワイヤのテールである。Next, an embodiment of the present invention will be described with reference to the drawings. 1 (a), 1 (b) and 1 (c) are partial cross-sectional views of a chip according to an embodiment of the present invention, and FIGS. 2 (a) and 2 (b).
FIG. 2 is a partial sectional view of the chip and the substrate. First, a method for forming a bump will be described with reference to FIG. FIGS. 1A to 1C show the steps of forming a bump in the order of steps. In FIG. 1A, an aluminum electrode 2 is formed on an upper surface of a chip 1, and an insulating film 3 is formed around the electrode 2. First, a copper bump 4 is formed on the electrode 2 by wire bonding. Reference numeral 5 denotes a tail of the wire generated during wire bonding.

【００１０】次に、図１（ｂ）に示すように、フラット
ニングツールにより銅バンプ４を上面から押圧して銅バ
ンプ４の上面にフラット面ａを形成する。次いで、図１
（ｃ）に示すように、銅バンプ４のフラット面ａ上にワ
イヤボンディングにより金バンプ７を形成する。このよ
うにして形成されたバンプ９の高さＨは、銅バンプ４の
高さに金バンプ７の高さを加え合わせたものとなるた
め、かなり高いものとなる。Next, as shown in FIG. 1B, the flat surface a is formed on the upper surface of the copper bump 4 by pressing the copper bump 4 from the upper surface with a flattening tool. Then, FIG.
As shown in (c), the gold bump 7 is formed on the flat surface a of the copper bump 4 by wire bonding. The height H of the bumps 9 formed in this manner is considerably higher because the height of the copper bumps 4 is added to the height of the gold bumps 7.

【００１１】なお、銅バンプ４の表面にフラット面ａを
形成せずに金バンプ７を直接形成しても問題ないが、フ
ラット面ａを形成して金バンプ７を形成した方が高さの
ばらつきを小さくすることができる。Although there is no problem if the gold bump 7 is directly formed without forming the flat surface a on the surface of the copper bump 4, the formation of the flat surface a and the formation of the gold bump 7 results in a higher height. Variation can be reduced.

【００１２】次に、上記方法により形成されたバンプ９
を有するチップ１の基板への実装について図２を参照し
て説明する。図２（ａ）において、基板１１の電極１２
上には半田１３がプリコートされている。この半田１３
はメッキ法やレベラ法などにより形成されている。この
半田１３上にチップ１のバンプ９が搭載されるが、半田
１３は金より柔らかいため、金バンプ７のテール８が半
田１３にめり込んだ形となる。この後、チップ１を搭載
した基板１１はリフロー炉に送られて加熱され、半田１
３が溶融する。金バンプ７は半田ぬれ性が良好なため、
図２（ｂ）に示すように、溶融状態の半田１３は表面張
力により金バンプ７の表面に沿ってはい上がり、溶融状
態の半田１３の上端部は銅バンプ４まで到達する。Next, the bump 9 formed by the above method is
The mounting of the chip 1 having the above on a substrate will be described with reference to FIG. In FIG. 2A, the electrode 12 on the substrate 11
The solder 13 is pre-coated thereon. This solder 13
Are formed by a plating method or a leveler method. The bumps 9 of the chip 1 are mounted on the solder 13. Since the solder 13 is softer than gold, the tail 8 of the gold bump 7 has a shape in which the solder 8 is embedded. Thereafter, the substrate 11 on which the chip 1 is mounted is sent to a reflow furnace where it is heated, and the solder 1
3 melts. Since the gold bump 7 has good solder wettability,
As shown in FIG. 2B, the molten solder 13 rises along the surface of the gold bump 7 due to surface tension, and the upper end of the molten solder 13 reaches the copper bump 4.

【００１３】しかし銅バンプ４はワイヤボンディングに
より形成された後に大気中にさらされているため、銅バ
ンプ４の表面には酸化膜４ａが生じており、半田ぬれ性
は悪い。このため溶融状態の半田１３は銅バンプ４の表
面に沿って更にはい上がることはなく、冷却固化した後
の半田１３はアルミの電極２には接触しない。したがっ
て、チップ１のアルミニウムの電極２が半田によって腐
食されることがない。However, since the copper bump 4 is exposed to the air after being formed by wire bonding, an oxide film 4a is formed on the surface of the copper bump 4, and the solder wettability is poor. Therefore, the solder 13 in the molten state does not further rise along the surface of the copper bump 4, and the solder 13 after cooling and solidification does not contact the aluminum electrode 2. Therefore, the aluminum electrode 2 of the chip 1 is not corroded by the solder.

【００１４】また、半田付け後に金バンプ７中に拡散す
る錫等の半田１３中の成分は、銅バンプ４によって拡散
が抑制されるため、チップ１のアルミ電極２までは到達
しない。したがって、接合強度の劣化の原因となる錫と
アルミの合金が形成されることがない。The components of the solder 13 such as tin diffused into the gold bumps 7 after the soldering do not reach the aluminum electrodes 2 of the chip 1 because the diffusion of the solder 13 is suppressed by the copper bumps 4. Therefore, there is no formation of an alloy of tin and aluminum which causes deterioration of the bonding strength.

【００１５】また、上記方法で形成されたバンプを有す
るチップをプリコート半田が形成された電極に半田付け
する場合には、半田付けされる部分は金バンプであるた
め表面に酸化膜を生じることがなく、したがってフラッ
クスを必要とせずに電極に半田付けを行うことができ
る。このため、フラックスによる基板の回路電極の腐食
が発生しない。When a chip having a bump formed by the above method is soldered to an electrode on which pre-coated solder is formed, an oxide film may be formed on the surface because the soldered portion is a gold bump. And thus soldering to the electrodes can be performed without the need for flux. For this reason, the circuit electrodes of the substrate are not corroded by the flux.

【００１６】[0016]

【発明の効果】本発明は、チップのアルミ電極上にワイ
ヤボンディングによって銅バンプを形成し、この銅バン
プ上にワイヤボンディングにより金バンプを形成するよ
うにしたので、このバンプを基板に半田付けした場合に
金バンプ中に拡散する半田中の錫は銅バンプによって拡
散が抑制されてアルミの電極まで到達せず、したがって
強度劣化の原因となる錫とアルミとの合金層が形成され
ることがなく、半田付け後の接合強度の劣化が発生しな
い。また銅バンプの表面は酸化膜により半田ぬれ性が悪
いため、半田はチップのアルミ電極まで到達せず、アル
ミが半田により腐食されることがない。さらにワイヤボ
ンディングにより銅バンプ上に金バンプを形成するよう
にしているので、銅バンプと金バンプの高さが加え合わ
されることとなり、エッチング設備などの複雑高価な設
備を必要とせずに高さの高いバンプを形成することがで
きる。このようにして形成されたバンプを基板に半田付
けするに際してフラックスを使用する必要がないので、
フラックスによる基板の回路電極の腐食を防止すること
ができる。According to the present invention, a copper bump is formed on an aluminum electrode of a chip by wire bonding, and a gold bump is formed on the copper bump by wire bonding. Therefore, the bump is soldered to a substrate. In the case, the tin in the solder that diffuses into the gold bumps is suppressed by the copper bumps from diffusing and does not reach the aluminum electrode, so that an alloy layer of tin and aluminum that causes strength deterioration is not formed. Also, there is no deterioration in bonding strength after soldering. Further, since the surface of the copper bump has poor solder wettability due to the oxide film, the solder does not reach the aluminum electrode of the chip, and the aluminum is not corroded by the solder. Furthermore, since the gold bumps are formed on the copper bumps by wire bonding, the heights of the copper bumps and the gold bumps are added together, so that the height of the height can be reduced without requiring complicated and expensive equipment such as etching equipment. High bumps can be formed. Since there is no need to use flux when soldering the bumps formed in this way to the board,
Corrosion of the circuit electrode of the substrate by the flux can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）本発明の一実施の形態のチップの部分断
面図 （ｂ）本発明の一実施の形態のチップの部分断面図 （ｃ）本発明の一実施の形態のチップの部分断面図FIG. 1A is a partial cross-sectional view of a chip according to an embodiment of the present invention. FIG. 1B is a partial cross-sectional view of a chip according to an embodiment of the present invention. Sectional view

【図２】（ａ）本発明の一実施の形態のチップおよび基
板の部分断面図 （ｂ）本発明の一実施の形態のチップおよび基板の部分
断面図2A is a partial cross-sectional view of a chip and a substrate according to an embodiment of the present invention; FIG. 2B is a partial cross-sectional view of a chip and a substrate according to an embodiment of the present invention;

【符号の説明】[Explanation of symbols]

１ チップ ２ 電極 ３ 絶縁膜 ４ 銅バンプ ５ テール ６ フラットニングツール ７ 金バンプ ８ テール １１ 基板 １２ 電極 １３ 半田 Reference Signs List 1 chip 2 electrode 3 insulating film 4 copper bump 5 tail 6 flattening tool 7 gold bump 8 tail 11 substrate 12 electrode 13 solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】チップのアルミ電極上にワイヤボンディン
グによって銅バンプを形成し、次にこの銅バンプ上にワ
イヤボンディングにより金バンプを形成することを特徴
とするバンプの形成方法。1. A method of forming a bump, comprising: forming a copper bump on an aluminum electrode of a chip by wire bonding; and then forming a gold bump on the copper bump by wire bonding.
JP13207997A 1997-05-22 1997-05-22 Chip mounting method Expired - Lifetime JP3564944B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13207997A JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13207997A JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method

Publications (2)

Publication Number Publication Date
JPH10321633A true JPH10321633A (en) 1998-12-04
JP3564944B2 JP3564944B2 (en) 2004-09-15

Family

ID=15073026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13207997A Expired - Lifetime JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method

Country Status (1)

Country Link
JP (1) JP3564944B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026147A1 (en) * 1999-10-04 2001-04-12 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
WO2002080271A3 (en) * 2001-03-28 2003-11-27 Intel Corp Fluxless flip chip interconnection
US7407877B2 (en) 2001-02-27 2008-08-05 Chippac, Inc. Self-coplanarity bumping shape for flip-chip
JP2017204586A (en) * 2016-05-12 2017-11-16 パナソニックＩｐマネジメント株式会社 Connecting method of circuit member

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026147A1 (en) * 1999-10-04 2001-04-12 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6744122B1 (en) 1999-10-04 2004-06-01 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
US7407877B2 (en) 2001-02-27 2008-08-05 Chippac, Inc. Self-coplanarity bumping shape for flip-chip
WO2002080271A3 (en) * 2001-03-28 2003-11-27 Intel Corp Fluxless flip chip interconnection
JP2017204586A (en) * 2016-05-12 2017-11-16 パナソニックＩｐマネジメント株式会社 Connecting method of circuit member
US10464153B2 (en) 2016-05-12 2019-11-05 Panasonic Intellectual Property Management Co., Ltd. Connecting method of circuit member

Also Published As

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