JP3564944B2 - Chip mounting method of - Google Patents

Chip mounting method of

Info

Publication number
JP3564944B2
JP3564944B2 JP13207997A JP13207997A JP3564944B2 JP 3564944 B2 JP3564944 B2 JP 3564944B2 JP 13207997 A JP13207997 A JP 13207997A JP 13207997 A JP13207997 A JP 13207997A JP 3564944 B2 JP3564944 B2 JP 3564944B2
Authority
JP
Grant status
Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13207997A
Other languages
Japanese (ja)
Other versions
JPH10321633A (en )
Inventor
忠彦 境
秀喜 永福
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

【0001】 [0001]
【発明の属する技術分野】 BACKGROUND OF THE INVENTION
本発明は、チップのアルミ電極上にバンプを形成するチップの実装方法に関する。 The present invention relates to a chip mounting method for forming a bump on an aluminum electrode of the chip.
【0002】 [0002]
【従来の技術】 BACKGROUND OF THE INVENTION
フリップチップなどのチップを基板に接合するために、チップの電極上にバンプを形成する方法が知られている。 Chips such as flip-chip for bonding to the substrate, a method for forming bumps is known on the chip electrodes. そしてチップを基板に実装する際には、このバンプは基板の電極に半田付けされる。 And when mounting the chip on the substrate, the bumps are soldered to the electrode of the substrate. 従来、チップの電極としてはアルミ電極が多用されており、またバンプとしては金バンプが多用されている。 Conventionally, as a chip electrode has been widely used an aluminum electrode, also gold bumps is frequently used as a bump.
【0003】 [0003]
【発明が解決しようとする課題】 [Problems that the Invention is to Solve
しかしながら、アルミ電極上に金バンプを形成し、この金バンプを半田付けする場合には、以下に述べるような接合強度の劣化が生じやすい。 However, the gold bumps were formed on an aluminum electrode, when the gold bumps to solder tends to occur degradation of the bonding strength as described below. すなわち、金バンプを半田付けすると半田中の錫等の成分は金バンプ中に拡散する。 That is, components such as tin in the solder when soldering the gold bump diffuses into the gold bumps. そして時間の経過とともにこれらの成分はアルミ電極と金バンプの界面まで到達し、そこで錫はアルミとの合金を形成する。 And these components over time reaches the interface between the aluminum electrode and a gold bump, where tin form an alloy of aluminum. ところがこの錫とアルミの合金は脆いため、アルミ電極と金バンプの界面に沿ってこの合金層が形成されると、接合強度を劣化させることになる。 However brittle alloy of tin and aluminum, when this alloy layer is formed along the interface of the aluminum electrode and the gold bumps, would degrade the bonding strength. そして、チップが使用される環境によっては基板とチップとの熱膨張率の差に起因する熱応力が繰り返し作用し、いわゆるヒートサイクルによってこの接合強度が劣化した部分が破断する場合があるという問題点があった。 The chip is the environment used by thermal stress is repeatedly effects due to the difference in thermal expansion coefficient between the substrate and the chip, a problem that this part of the bonding strength is deteriorated by the so-called heat cycle is sometimes broken was there.
【0004】 [0004]
そこで従来は、金バンプを形成する以前の半導体ウェハ工程において、チップの表面に半田ぬれ性がよい銅などの金属層をバリヤ層として形成し、この金属層のうち、アルミ電極以外の部分をエッチングで取り除いて電極を形成させることが行われていた。 Therefore conventionally, in the previous semiconductor wafer to form a gold bump, a metal layer such as solder wettability good copper surface of the chip is formed as a barrier layer, of the metal layer, etching portions other than the aluminum electrode thereby forming the electrodes removed in has been performed. しかしながらこのような方法では、チップの表面に金属層を形成したり、また金属層をエッチングにより除去して電極を形成させる工程が新たに必要であるため、工程が面倒であって生産性が上がらず、またコストアップにもなるという問題点があった。 However, in this method, or forming a metal layer on the surface of the chip, and because the step of forming the electrode is removed by etching the metal layer are newly required, step productivity rise a troublesome not, also there is a problem that also increase in cost.
【0005】 [0005]
ところで、フリップチップなどバンプ付きのワークを基板に半田付けする場合、バンプの高さはより高いことが望まれる。 Incidentally, when soldering the workpiece with bumps such as a flip chip to a substrate, the height of the bump is desired higher. これは、高いバンプの方が半田付け後に基板とチップの熱膨張の差によって生じる熱変形をより吸収しやすいこと、また基板のうねりなどによる高低差をより吸収できることによる。 This is due to thermal deformation caused by the difference in the direction of higher bump soldering thermal expansion of the substrate and the chip after more easily absorb it, also to be more absorbing height difference due to undulation of the substrate.
【0006】 [0006]
そこで本発明は、半田付け後に接合強度の劣化を生じることがなく、しかも高さの高いバンプを形成することができるチップの実装方法を提供することを目的とする。 Accordingly, the present invention aims to provide a chip mounting method capable of forming a high bump of it without, moreover height resulting in deterioration of the bonding strength after soldering.
【0007】 [0007]
【課題を解決するための手段】 In order to solve the problems]
本発明のチップの実装方法は、チップのアルミ電極上にワイヤボンディングによって銅バンプを形成し、次にこの銅バンプを上面から押圧することにより銅バンプにフラット面を形成した後、このフラット面上にワイヤボンディングにより金バンプを形成し、この金バンプを基板に半田付けするチップの実装方法であって、溶融した半田のはい上がりを前記銅バンプの表面の酸化膜によって防止することにより前記アルミ電極に溶融した半田を接触させないようにした。 Chip mounting method of the present invention, the copper bumps formed by wire bonding on the aluminum electrodes of the chip, then after forming the flat surface of the copper bump by pressing the copper bumps from the top surface, on the flat surface the gold bumps formed by wire bonding, a chip mounting method for soldering the gold bumps on the substrate, the aluminum electrode by preventing wicking of molten solder with the oxide film on the surface of the copper bump and so as not to contact with the molten solder to.
【0008】 [0008]
【発明の実施の形態】 DETAILED DESCRIPTION OF THE INVENTION
上記構成の本発明によれば、チップのアルミ電極上にワイヤボンディングによって銅バンプを形成し、この銅バンプ上にワイヤボンディングにより金バンプを形成し、この金バンプを基板に半田付けするチップの実装方法であって、溶融した半田のはい上がりを前記銅バンプの表面の酸化膜によって防止することにより前記アルミ電極に溶融した半田を接触させないようにしたので、半田中の錫は銅バンプによって拡散が抑制されアルミ電極には到達せず、したがって強度劣化の原因となる錫とアルミの合金層が形成されることがない。 According to the present invention having the above structure, the copper bumps formed by wire bonding on the aluminum electrodes of the chip, a gold bump formed by wire bonding on the copper bump, mounting of the chip soldering the gold bumps on the substrate a method, since so as not to contact the molten solder to the aluminum electrode by preventing wicking of molten solder with the oxide film on the surface of the copper bumps, tin in the solder is diffused by the copper bumps It does not reach the aluminum electrode is suppressed, thus never tin and aluminum alloy layer which causes deterioration of strength is formed. また銅バンプと金バンプの高さが加え合わされるため全体として高さの高いバンプが形成できる。 The high bump heights can be formed as a whole since the height of the copper bumps and gold bumps are summed.
【0009】 [0009]
次に、本発明の実施の形態を図面を参照して説明する。 Next, an embodiment of the present invention with reference to the drawings. 図1(a)、(b)、(c)は本発明の一実施の形態のチップの部分断面図、図2(a)、(b)は、同チップおよび基板の部分断面図である。 Figure 1 (a), (b), (c) is a partial sectional view of a chip of an embodiment of the present invention, FIG. 2 (a), (b) is a partial sectional view of the chip and the substrate. まず、バンプの形成方法について、図1を参照して説明する。 First, a method of forming the bump, will be described with reference to FIG. 図1(a)〜(c)は、バンプの形成工程を工程順に示したものである。 Figure 1 (a) ~ (c) is a diagram showing the bump forming process in the order of steps. 図1(a)において、チップ1の上面にはアルミ電極2が形成されており、電極2の周辺には絶縁膜3が形成されている。 In FIG. 1 (a), the upper surface of the chip 1 are formed an aluminum electrode 2, the periphery of the electrode 2 are formed an insulating film 3. まず電極2上にワイヤボンディングにより銅バンプ4が形成される。 Copper bumps 4 are formed by first wire bonding on the electrode 2. 5は、ワイヤボンディング時に生じるワイヤのテールである。 5 is a wire tail that occurs during wire bonding.
【0010】 [0010]
次に、図1(b)に示すように、フラットニングツールにより銅バンプ4を上面から押圧して銅バンプ4の上面にフラット面aを形成する。 Next, as shown in FIG. 1 (b), to form a flat surface a presses the copper bumps 4 from the upper surface by flattening tool on the upper surface of the copper bump 4. 次いで、図1(c)に示すように、銅バンプ4のフラット面a上にワイヤボンディングにより金バンプ7を形成する。 Then, as shown in FIG. 1 (c), to form the gold bump 7 by wire bonding on the flat surface a copper bumps 4. このようにして形成されたバンプ9の高さHは、銅バンプ4の高さに金バンプ7の高さを加え合わせたものとなるため、かなり高いものとなる。 The height H of the bumps 9 formed in this way, since the to the combined height of the gold bumps 7 in addition to the height of the copper bumps 4, becomes quite high.
【0011】 [0011]
なお、銅バンプ4の表面にフラット面aを形成せずに金バンプ7を直接形成しても問題ないが、フラット面aを形成して金バンプ7を形成した方が高さのばらつきを小さくすることができる。 Incidentally, without forming the flat surface a on the surface of the copper bump 4 is no problem be formed gold bumps 7 directly, reduce the variation of it is the height of forming the gold bumps 7 to form a flat surface a can do.
【0012】 [0012]
次に、上記方法により形成されたバンプ9を有するチップ1の基板への実装について図2を参照して説明する。 Will now be described with reference to FIG. 2 mounted to the substrate of the chip 1 with bumps 9 formed by the above method. 図2(a)において、基板11の電極12上には半田13がプリコートされている。 In FIG. 2 (a), on the electrode 12 of the substrate 11 the solder 13 is precoated. この半田13はメッキ法やレベラ法などにより形成されている。 The solder 13 is formed by plating method or leveler method. この半田13上にチップ1のバンプ9が搭載されるが、半田13は金より柔らかいため、金バンプ7のテール8が半田13にめり込んだ形となる。 Although the bumps 9 of the chip 1 on the solder 13 is mounted, the solder 13 is softer than gold, the tail 8 of the gold bumps 7 is a form that sinks to the solder 13. この後、チップ1を搭載した基板11はリフロー炉に送られて加熱され、半田13が溶融する。 Thereafter, the substrate 11 mounted with the chip 1 is heated is sent to a reflow furnace, the solder 13 is melted. 金バンプ7は半田ぬれ性が良好なため、図2(b)に示すように、溶融状態の半田13は表面張力により金バンプ7の表面に沿ってはい上がり、溶融状態の半田13の上端部は銅バンプ4まで到達する。 Since the gold bumps 7 have good solderability, as shown in FIG. 2 (b), the solder 13 is creeping along the surface of the gold bumps 7 by the surface tension of the molten solder 13 upper portion of the molten It is to reach the copper bump 4.
【0013】 [0013]
しかし銅バンプ4はワイヤボンディングにより形成された後に大気中にさらされているため、銅バンプ4の表面には酸化膜4aが生じており、半田ぬれ性は悪い。 However, since the copper bumps 4 are exposed to the atmosphere after being formed by wire bonding, the surface of the copper bump 4 has occurred oxide film 4a, the solder wettability is poor. このため溶融状態の半田13は銅バンプ4の表面に沿って更にはい上がることはなく、冷却固化した後の半田13はアルミの電極2には接触しない。 Thus solder 13 in a molten state is not further Yes up along the surface of the copper bump 4, the solder 13 after cooled and solidified is not in contact with the electrodes 2 of the aluminum. したがって、チップ1のアルミニウムの電極2が半田によって腐食されることがない。 Therefore, it never electrodes 2 of the aluminum of the chip 1 is corroded by solder.
【0014】 [0014]
また、半田付け後に金バンプ7中に拡散する錫等の半田13中の成分は、銅バンプ4によって拡散が抑制されるため、チップ1のアルミ電極2までは到達しない。 Further, components of the solder 13 in tin to diffuse into the gold bumps 7 after soldering, the diffusion of copper bumps 4 is suppressed, until the aluminum electrode 2 of the chip 1 does not reach. したがって、接合強度の劣化の原因となる錫とアルミの合金が形成されることがない。 Therefore, never tin and aluminum alloy causes deterioration of the bonding strength is formed.
【0015】 [0015]
また、上記方法で形成されたバンプを有するチップをプリコート半田が形成された電極に半田付けする場合には、半田付けされる部分は金バンプであるため表面に酸化膜を生じることがなく、したがってフラックスを必要とせずに電極に半田付けを行うことができる。 Further, in the case of soldering to electrodes precoated solder is formed a chip with bumps formed by the above method, without causing an oxide film on the surface for the portion to be soldered is gold bumps, thus flux can be performed soldering to the electrodes without the need for. このため、フラックスによる基板の回路電極の腐食が発生しない。 Therefore, corrosion of the circuit electrodes of the substrate by the flux does not occur.
【0016】 [0016]
【発明の効果】 【Effect of the invention】
本発明は、チップのアルミ電極上にワイヤボンディングによって銅バンプを形成し、この銅バンプ上にワイヤボンディングにより金バンプを形成し、この金バンプを基板に半田付けするチップの実装方法であって、溶融した半田のはい上がりを前記銅バンプの表面の酸化膜によって防止することにより前記アルミ電極に溶融した半田を接触させないようにしたので、このバンプを基板に半田付けした場合に金バンプ中に拡散する半田中の錫は銅バンプによって拡散が抑制されてアルミの電極まで到達せず、したがって強度劣化の原因となる錫とアルミとの合金層が形成されることがなく、半田付け後の接合強度の劣化が発生しない。 The present invention is a copper bump formed by wire bonding on the aluminum electrodes of the chip, and this on a copper bump gold bump formed by wire bonding, a chip mounting method for soldering the gold bumps on the substrate, since molten solder wicking was prevented by contacting the molten solder to the aluminum electrode by preventing the oxide film on the surface of the copper bumps, spreading the bumps to the gold in bumps when soldered to the substrate tin is suppressed diffusion of copper bumps do not reach the electrodes of aluminum, thus without alloy layer is formed of tin and aluminum which causes strength degradation, the bonding strength after soldering in solder deterioration of does not occur. また銅バンプの表面は酸化膜により半田ぬれ性が悪いため、半田はチップのアルミ電極まで到達せず、アルミが半田により腐食されることがない。 Since the surface of the copper bumps poor solder wettability by oxide films, solder does not reach the aluminum electrode of the chip, it is not to be corroded by soldering aluminum. さらにワイヤボンディングにより銅バンプ上に金バンプを形成するようにしているので、銅バンプと金バンプの高さが加え合わされることとなり、エッチング設備などの複雑高価な設備を必要とせずに高さの高いバンプを形成することができる。 Since so as further to form a gold bump on the copper bump by wire bonding, it is the height of the copper bumps and gold bumps are summed, the height of without the need for complicated expensive equipment, such as etching equipment it is possible to form a high bump. このようにして形成されたバンプを基板に半田付けするに際してフラックスを使用する必要がないので、フラックスによる基板の回路電極の腐食を防止することができる。 It is not necessary to use a flux during soldering Thus the bumps formed in the substrate, it is possible to prevent corrosion of the circuit electrodes of the substrate by the flux.
【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS
【図1】(a)本発明の一実施の形態のチップの部分断面図(b)本発明の一実施の形態のチップの部分断面図(c)本発明の一実施の形態のチップの部分断面図【図2】(a)本発明の一実施の形態のチップおよび基板の部分断面図(b)本発明の一実施の形態のチップおよび基板の部分断面図【符号の説明】 Portion of the chip of an embodiment of a partial cross-sectional view of a chip of an embodiment (c) the invention of partial cross-sectional view of a chip of an embodiment (b) The present invention of FIG. 1 (a) the invention sectional view 2 (a) partial sectional view of the chip and the substrate of an embodiment of a partial cross-sectional view of the chip and the substrate of the embodiment (b) the invention of the present invention description of Reference numerals]
1 チップ2 電極3 絶縁膜4 銅バンプ5 テール6 フラットニングツール7 金バンプ8 テール11 基板12 電極13 半田 1 chip 2 electrode 3 insulating film 4 copper bumps 5 tail 6 flattening tool 7 gold bumps 8 tail 11 substrate 12 electrode 13 solder

Claims (1)

  1. チップのアルミ電極上にワイヤボンディングによって銅バンプを形成し、次にこの銅バンプ上にワイヤボンディングにより金バンプを形成し、この金バンプを基板に半田付けするチップの実装方法であって、溶融した半田のはい上がりを前記銅バンプの表面の酸化膜によって防止することにより前記アルミ電極に溶融した半田を接触させないようにしたことを特徴とするチップの実装方法。 Copper bumps formed by wire bonding on the aluminum electrode of a chip, then the gold bump formed by wire bonding on the copper bump, a mounting method of the chip soldering the gold bumps on the substrate, and molten chip mounting method which is characterized in that so as not to contact the molten solder to the aluminum electrode by preventing solder wicking by oxidation film on the surface of the copper bumps.
JP13207997A 1997-05-22 1997-05-22 Chip mounting method of Expired - Lifetime JP3564944B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13207997A JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method of

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13207997A JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method of

Publications (2)

Publication Number Publication Date
JPH10321633A true JPH10321633A (en) 1998-12-04
JP3564944B2 true JP3564944B2 (en) 2004-09-15

Family

ID=15073026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13207997A Expired - Lifetime JP3564944B2 (en) 1997-05-22 1997-05-22 Chip mounting method of

Country Status (1)

Country Link
JP (1) JP3564944B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026147A1 (en) * 1999-10-04 2001-04-12 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6940178B2 (en) 2001-02-27 2005-09-06 Chippac, Inc. Self-coplanarity bumping shape for flip chip
US6495397B2 (en) * 2001-03-28 2002-12-17 Intel Corporation Fluxless flip chip interconnection

Also Published As

Publication number Publication date Type
JPH10321633A (en) 1998-12-04 application

Similar Documents

Publication Publication Date Title
US5219794A (en) Semiconductor integrated circuit device and method of fabricating same
US7274088B2 (en) Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof
US5990564A (en) Flip chip packaging of memory chips
US5466635A (en) Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
US5235212A (en) Semiconductor device having a mechanical buffer
US6229220B1 (en) Bump structure, bump forming method and package connecting body
US4518112A (en) Process for controlled braze joining of electronic packaging elements
US5081067A (en) Ceramic package type semiconductor device and method of assembling the same
US20040177997A1 (en) Electronic apparatus
US5985692A (en) Process for flip-chip bonding a semiconductor die having gold bump electrodes
US6396155B1 (en) Semiconductor device and method of producing the same
US6164523A (en) Electronic component and method of manufacture
US5349495A (en) System for securing and electrically connecting a semiconductor chip to a substrate
US4661375A (en) Method for increasing the height of solder bumps
US4942452A (en) Lead frame and semiconductor device
US20050151268A1 (en) Wafer-level assembly method for chip-size devices having flipped chips
US20070205253A1 (en) Method for diffusion soldering
US5249732A (en) Method of bonding semiconductor chips to a substrate
US7902678B2 (en) Semiconductor device and manufacturing method thereof
US6162664A (en) Method for fabricating a surface mounting type semiconductor chip package
US6214156B1 (en) Semiconductor device mounted on board by flip-chip and method for mounting the same
US20020079577A1 (en) Advanced electronic package
US4920074A (en) Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US7145236B2 (en) Semiconductor device having solder bumps reliably reflow solderable
US5908317A (en) Method of forming chip bumps of bump chip scale semiconductor package

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040302

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040416

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040518

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040531

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080618

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090618

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100618

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100618

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110618

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120618

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120618

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130618

Year of fee payment: 9

EXPY Cancellation because of completion of term