TW200421501A - Localized reflow for wire bonding and flip chip connections - Google Patents
Localized reflow for wire bonding and flip chip connections Download PDFInfo
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- TW200421501A TW200421501A TW092135994A TW92135994A TW200421501A TW 200421501 A TW200421501 A TW 200421501A TW 092135994 A TW092135994 A TW 092135994A TW 92135994 A TW92135994 A TW 92135994A TW 200421501 A TW200421501 A TW 200421501A
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Abstract
Description
200421501 ⑴ 玖、發明說明 相關發明之交叉參考 本發明主張於2002年12月18日申請之美國暫時申 請案第60/43 4,474號之「佈線接合及倒裝晶片連接之局 部回焊」的好處,在此參照包含其完整之內容。 【發明所屬之技術領域】 本發明大致上有關於電子連結至晶片之焊接,詳言之 係有關於佈線接合與倒裝晶片連接。 【先前技術】 自從低電介質(低k )材料之引入,許多人已投入很 大的努力發展新的技術以及整合舊有習知的方法,以解決 由低k材料形成之電介質材料所產生之問題。低k材料比 習知的絕緣體,如Si02,結構上與機械上更弱。因此由 於在製造過程中低k層之脫層以及互連線之破裂與裂洞, 更易導致裝置失敗。 例如’習知佈線接合至接合墊或連接倒裝晶片至基體 的技術’於接合過程中需要施予頗大壓力至下層金屬結構 。另外’製造倒裝晶片連接通常需要於熔爐內將倒裝晶片 及基體加熱至不低於形成連接接合於倒裝晶片與基體之焊 接材料的熔點溫度。尤甚者,若焊接凸塊,需要更高的溫 度以助於回焊與連接,例如攝氏2 0至3 0度高於焊接凸塊 之熔點溫度(Pb-Sn共熔合金爲攝氏205 -22 0度)。又, (2) (2)200421501 右焊接倒裝晶片連接,除了高溫外,因爲倒裝晶片與基體 之不同的熱膨脹係數,當晶片冷卻時會產生熱應力。如第 1 2 A、與2 B圖所示,當使用低k材料時,與習知技術 有關之應力與熱膨脹可能造成缺陷形成於低k材料中。 再者’亞洲與歐洲的國家最早將從2〇〇4年開始禁止 使用纟α作爲電子兀件焊接材料。p b或s η P b共熔合金比譬 如S η或A g C11之具有較高熔點溫度特性之不具鉛的焊接 代替材料需要較低的焊接溫度。因此,低k材料之推動與 電子封裝中鉛的禁止,熱計畫控制將成爲於佈線接合與倒 裝晶片製程時減小或移除互連線破壞金屬層之關鍵。 於某些習知技術中,減低接合墊之大小或將之強化以 減少施於金屬層上的力量。雖然此能減輕些許接觸壓力, 但仍有熱應力以及於下層金屬層之重複接觸壓力累增效應 【發明內容】 於一範例實施例中,晶片電子連接之焊接系統包括接 合墊、焊接凸塊、以及能量源。在此範例實施例中,將能 量源局部化於焊接凸塊,但不實際接觸焊接凸塊。局部能 量源將焊接凸塊加熱以回焊焊接凸塊於接合墊上而不至於 將整個晶片加熱。 【實施方式】 下列說明揭示多種特定配置以及參數等。惟應了解此 -5- (3) (3)200421501 說明並非用於限制本發明之範圍,而應視爲提供範例實施 例之說明。 佈線接合 參考第3A圖,在一範例實施例中,晶片3 00之電子 連接焊接系統包括接合墊3 02、焊接凸塊3 04、以及能量 源3 0 6。在此範例實施例中,將能量源3 〇 6局部化至焊接 凸塊3〇4而不實際接觸焊接凸塊3〇4。局部能量源3〇6加 熱焊接凸塊3 04以回焊焊節凸塊3 04於接合墊3 02上,而 不至於加熱整個晶片3 0 0。 於第3 A圖所示之實施例中,焊接凸塊3 〇 4連接佈線 3 08。焊接凸塊3 04與佈線3 0 8係位於接合墊3 02上,接 者局部能量源3 0 6將位於接合墊3 0 2上之焊接凸塊3 0 4加 熱。如第3 B圖所示,焊接凸塊3 0 4與佈線3 0 8於接合墊 3 02上形成佈線接合。 於此範例實施例中’焊接凸塊3 04最好爲96.5 %的錫 與3.5%的銀錫。焊接凸塊304最好具有高於攝氏221度 之熔點。但應了解到可用具有其他熔點之其他材料形成焊 接凸塊3 0 4。 於本範例實施例中,局部能量源3〇6可包括雷射、χ 光射、電子安迪(Andy )電流式加熱器、紅外線加熱器 、以及電子光束之類的。當局部能量源3 〇 6雷射時,雷射 可爲固態雷射(例如紅寶石、N cU玻璃、N D : Y A G (釔鋁 石榴石,YMhO】2 )、以及之類的),或氣體雷射(例如 (4) (4)200421501 HE-NE、C02、HF、以及之類的)。 參考第4A圖,於另一範例實施例中,將焊接凸塊 3 0 4定位於接合墊3 0 2上之前,局部能量源3 0 6加熱焊接 凸塊3 0 4。當焊接凸塊3 0 4已經被加熱溶化時,將焊接凸 塊3 0 4與佈線3 0 8定位於接合墊3 0 2上。如第4 B圖所示 ,焊接凸塊3 0 4與佈線3 0 8形成佈線接合於接合墊上。 參考第5 A圖,於又一範例實施例中,將焊接凸塊 3 0 4定位於接合墊3 0 2上之前’局部能量源3 0 6加熱焊接 凸塊3 0 4與接合墊3 0 2。當焊接凸塊3 0 4已經被加熱溶化 時,將加熱焊接凸塊3 04定位於加熱接合墊3 〇2上。如第 5 B圖所示’焊接凸塊3 0 4與佈線3 0 8形成佈線接合於接 合墊上。 於此範例實施中,於接合墊3 02上形成潤濕層5 02。 局部能量源3 02溶化覆蓋接合墊3 02之潤濕層5 02。潤濕 層 502 可包括 Au、CuTi、TiN、Tin、SbPb、SnAg 合金、 以及之類的。 於此範例實施中,局部能量源3 0 6可包括第一能量源 3 06局部化至焊接凸塊3 04以及第二能量源3 06局部化至 接合墊302。第一能量源3 06加熱焊接凸塊3 04,以及第 二能量源3 06加熱接合墊3 02。 代替性地,局部能量源3 06係可移動。可移動能量源 3 06先加熱焊接凸塊3 04,接著移動以加熱接合墊3 02。 參考第6A圖,於另一範例實施例,藉由局部能量源 3 06加熱焊接凸塊3 04之前,將焊接凸塊3 04定位於接合 -7- (5) (5)200421501 墊3 02上。於第6B圖所示,加熱焊接凸塊3 04之後,將 佈線3 0 8連接於焊接凸塊3 04。於此範例實施例中,局部 能量源3 06加熱佈線3 0 8與焊接凸塊3 04,接著將加熱的 佈線3 0 8連接於加熱的焊接凸塊3 04以形成佈線接合於接 合墊3 02上。 於此範例實施中,於接合墊3 02上形成潤濕層5 02。 局部能量源3 0 2溶化覆蓋接合墊3 0 2之潤濕層5 0 2。潤濕 層 502 可包括 Au、CuTi、TiN、Tin、SbPb、SnAg 合金、 以及之類的。 於此範例實施中,局部能量源3 0 6可包括第一能量源 3 〇 6局部化至佈線3 0 8以及第二能量源3 0 6局部化至焊接 凸塊3 04。第一能量源3 06加熱佈線3 0 8,以及第二能量 源3 06加熱焊接凸塊3 04。 代替性地,局部能量源3 06係可移動。可移動能量源 3 〇 6先加熱佈線3 0 8,接著移動以加熱焊接凸塊3 〇 4。 參考第7圖,於一範例實施例,晶片3 00可包括多個 接合墊3 02、多個焊接凸塊3 04、以及佈線3 0 8。如第7 圖所示,可使用多個能量源306來加熱多個焊接凸塊304 。尤甚者’各能量源3 0 6係局部化至各焊接凸塊3 0 4以加 熱各焊接凸塊304以回焊各焊接凸塊304於各接合墊302 ’而不至於加熱整個晶片3 00。使用多個能量源3 06加熱 多個焊接凸塊3 0 4可增加回焊過程的效率。 參考第8圖,於另一範例實施例中,鑲嵌遮罩802係 置於能量源3 06與多個焊接凸塊3 〇4之間。如第8圖所示 (6) (6)200421501 ,鑲嵌遮罩8 0 2包括對應焊接凸塊3 0 4之剪下區域8 0 4。 因此,能量源3 0 6係藉由各剪下區域8 0 4局部化至各焊接 凸塊3 04以加熱各焊接凸塊3 04以回焊各焊接凸塊3 04於 各接合墊3 02上,而不加熱整個晶片3 00。 於此範例實施例中,鑲嵌遮罩8 02可爲不透光材料, 最好爲具有高導電性以及高熔點之金屬或合金,如T i、W 、Cu、Ta、Au、A1、以及之類的。鑲嵌遮罩802可連接 至熱交換元件8 06以保持鑲嵌遮罩8 02之溫度。能量源 3 06可爲寬光束雷射、紅外線加熱燈、電子光束、以及之 類的。當能量源3 0 6爲電子光束時,回焊過程最好於真空 環境中執行。 參考第9圖,於另一範例實施例中,能量源3 06可移 動。如第9圖所示,可移動能量源3 06可移動至焊接凸塊 3 04之間以加熱各焊接凸塊3 04以回焊各焊接凸塊於接合 墊302上,而不加熱整個晶片300。亦如第9圖所示,可 移動能量源3 0 6可往X、y、以及y方向移動。應注意到 晶片3 0 0可保持靜止或與移動之能量源3 0 6相對移動。 參考第10圖,於再一範例實施例中,移動晶片300 使各焊接凸塊3 04定位相鄰能量源3 06,以加熱焊接凸塊 3 04以回焊個焊接凸塊304於各接合墊3 02上,而不加熱 整個晶片3 00。於此範例實施例中,晶片3 00可置於可移 動桌1 002或任何適合的移動裝置上。應注意到晶片300 可保持靜止或與移動之能量源3 06相對移動。 參考第1 ]圖,於又一範例實施例中,定位系統1 1 0 2 -9 - (7) (7)200421501 可用於調查並定位晶片3 0 0上個接合墊3 02之位置。於此 範例實施例中,定位系統1 1 〇2可爲光學影像系統,如電 荷耦合器件(CCD )攝影機。如第1 1圖所示,可將定位 系統1 1 02與能量源3 06連接。定位系統1 1 02以及能量源 3 06可設於並沿著X軸條1 104移動,該X軸條1 104可沿 著y軸條1 1 06移動。因此,於本範例實施例中,可移動 定位系統1 1 02與能量源至晶片上任何位置。 倒裝晶片連接 參考第12A圖,晶片300係接合於基體1200上,且 通常稱爲倒裝晶片。如第12A圖所示,焊接凸塊3 04係 置於倒裝晶片3 00與基體1 200之間,以連接接合倒裝晶 片3 00與基體1 200。 通常,對於典型63 %的Sn與37%的Pb之共熔合金, 倒裝晶片連接需要攝氏1 8 3度之高熔點,以及焊料沉積時 間約1 〇秒。較長的焊料沉積時間會於晶片3 0 0之電介質 層上導致較長的接觸壓力,其可能早成電介質層中的缺陷 ,特別係當電介質層包括有低k材料時。 因此,於本範例實施例中,能量源3 0 6係局部化至位 於倒裝晶片3 00與基體1 200之間的焊接凸塊3 04。如第 1 2 B圖所示,局部能量源3 0 6加熱焊接凸塊3 〇 4直到焊接 凸塊3 0 4回焊至沙漏形狀連接於倒裝晶片3 〇 〇與基體 1 2 0 0之間。 參考第1 3圖,於一範例實施例中,倒裝晶片3 〇 〇可 (8) (8)200421501 包括多個焊接凸塊3 (Μ。於本範例實施例中,鑲嵌遮罩 802可置於能量源3 06與多個焊接凸塊3〇4之間。如第13 圖所示,鑲嵌遮罩8 02包括對應焊接凸塊3 04之剪下區域 8 0 4。因此’能量源3 0 6係藉由各剪下區域8 〇 4局部化至 各焊接凸塊3 0 4以加熱各焊接凸塊3 0 4以回焊各焊接凸塊 3 〇 4於各接合墊3 0 2上,而不加熱整個倒裝晶片3 0 0。 詳言之,於本範例實施例中,能量源3 06藉由加熱基 體1200上的焊接凸塊304加熱倒裝晶片300上之焊接凸 塊3〇4。因此,於本範例實施例中,可裝配感測器1302 掃描基體1 200後面之定位標記13〇4,以定位鑲嵌遮罩 8 04於基體1 200之上。亦可裝配感測器13〇6來調整相對 於倒裝晶片3 0 0基體1 2 0 0之位置。於本範例實施例中, 感測器1 3 02與1 3 06爲光學感測器。但應注意到可使用其 他種類的感測器。 於本範例實施例中,倒裝晶片係位於可移動桌1 002 上,可移動桌1 002移動倒裝晶片3 00相對於鑲嵌遮罩 802。如第13圖所示,可移動桌1002可往x、y、z、與 theta方向移動。 參考第14圖,於另一範例實施例中,可使用加熱器 14 02來加熱倒裝晶片300。加熱器1 402加熱倒裝晶片 3 00以減少從能量源3 06所需之功率量。惟加熱器1402 加熱倒裝晶片3 00至低於倒裝晶片3 00中焊接凸塊3 04之 熔點的溫度。 參考第1 5圖,於再一範例實施例中,倒裝晶片3 0 0 (9) (9)200421501 以及基體1 2 0 0係置於密封室} 5 〇 2之中。如第i 5圖所示 ’鑲嵌遮罩8 02係置於密封式15〇2外。於本範例實施例 中,密封室1 5 02包括玻璃上部件1 5 04。因此,能量源 306係藉由鑲嵌遮罩802之各剪下區域804以及玻璃上部 件1 5 04局部化至倒裝晶片3〇〇上之各焊接凸塊3〇4,以 回焊各焊接凸塊3 04,而不加熱整個倒裝晶片3 00。 於本範例實施例中,密封室1 5 0 2具有控制的溫度。 如第15圖所示,密封室1502具有氣體入口 1506。於回 焊過程當焊接凸塊304回焊時,譬如氮之鈍氣由氣體入口 1 5 06引入,以減少或防止焊接凸塊3〇4之氧化。於回焊 後,如氮之冷卻氣體藉由氣體入口 1506引入,以冷卻倒 裝晶片300以及基體1200以將回焊過程中產生的熱作用 減少或減至最小。 參考第16A、16B、與16C圖,說明回焊倒裝晶片 300上之焊接凸塊3〇4的一範例過程。尤甚者,於第16A 圖中,使用鑲嵌遮罩802將能量源3 06局部化至倒裝晶片 300上之焊接凸塊304,以高於焊接凸塊304之熔點的溫 度加熱焊接凸塊304,以回焊焊接凸塊304,而不加熱整 個倒裝晶片300。詳言之,將焊接凸塊3 04加熱至高於焊 接凸塊3 04之熔點攝氏10至100度,最好係50度之溫度 。於第16圖,當倒裝晶片3 00上之焊接凸塊3 04的溫度 係高於焊接凸塊3 04之熔點時,接合墊或基體1 200上之 焊接凸塊與倒裝晶片3 00上之焊接凸塊3 04相接觸。於第 16C圖中,倒裝晶片3 00之焊接凸塊3 04以及接合墊或基 (10) (10)200421501 體1 200上之焊接凸塊係保持接觸直到倒裝晶片3 00上之 焊接凸塊3 04冷卻至低於倒裝晶片3 00上之焊接凸塊304 之熔點。 參考第I7A、17B、與17C圖,於一範例實施例中, 基體1 200爲印刷電路板/卡。因此,倒裝晶片係接合於印 刷電路板/卡1 200上。 參考第18A圖,於一範例實施例中,倒裝晶片300 係置於可移動桌1 002上。可移動桌1 002移動倒裝晶片 3 00至低於鑲嵌遮罩8 08之第一位置以及低於基體1200 之第二位置之間。當倒裝晶片3 00係於第一位置時,倒裝 晶片3 00之焊接凸塊3 04藉由加熱源3 06經過鑲嵌裝置 8 0 8加熱。如第18B圖所示,當倒裝晶片3 00係於第二位 置時,接合墊或基體1200上之焊接凸塊與倒裝晶片300 上之焊接凸塊3 04接觸。 參考第19A圖,於又一範例實施例中,倒裝晶片300 係保持靜止。鑲嵌遮罩8 0 8以及能量源3 0 6係移動至倒裝 晶片3 00相鄰處,以加熱倒裝晶片3 00之焊接凸塊3 04。 如第19B圖所示,當倒裝晶片3 00之焊接凸塊3 04已經加 熱時,將基體1200移至倒裝晶片300之相鄰處,使基體 1 2 00之焊接凸塊或接合墊與倒裝晶片3 00之焊接凸塊304 接觸。於本範例實施例中,裝載自動控制裝置1902移動 基體1200,以將基體1200之焊接凸塊或接合墊與倒裝晶 片300之焊接凸塊304接觸。 雖已描述範例實施例,仍可進行多種更改而不違背本 -13- (11) (11)200421501 發明之精神與範疇。因此,本發明不應限制於如上所述與 圖式所示之特定型態。 【圖式簡單說明】 可參考上述說明與所附圖式使本發明易於了解,其中 類似元件將以類似符號代表。 第1圖爲顯示使用接觸壓力以握持並焊接佈線於接合 墊上之先前技術; 第2A與2B圖顯示使用熔爐回焊焊接材料於倒裝晶 片與基體之間的先前技術; 第3厶、38、4八、48、5八、56、6八、以及66圖顯示 使用局部能量源加熱焊接凸塊之範例實施例·, 第7圖顯示使用多個局部能量源以加熱多個焊接焊接 凸塊之範例實施例; 第8圖顯示使用藉由鑲嵌遮罩局部化之能量源以加熱 多個焊接凸塊之範例實施例; 第9圖顯示使用可移動局部能量源以加熱多個焊接焊 接凸塊之範例實施例; 第1〇圖顯示使用具有固定能量源與移動桌以加熱多 個焊接焊接凸塊之範例實施例; 第】1圖顯示使用定位系統以及能量源之範例實施例 第12A與12B圖顯示使用局部能量源以加熱接合倒 S晶片於基體上之範例實施例; •14- (12) (12)200421501 第1 3 -1 5圖顯示使用藉由鑲嵌遮罩局部化之能量源以 加熱多個焊接凸塊以接合倒裝晶片於基體上之範例實施例 第16A、16B、與16C圖顯示接合倒裝晶片於基體上 之範例實施例; 第17A、17B、與17C圖顯示接合倒裝晶片於印刷積 體電路版/卡上之範例實施例; 第18A與18B圖顯示使用可移動桌接合倒裝晶片於 基體上之範例實施例; 第19A與19B圖顯示使用裝載自動控制裝置接合倒 裝晶片於基體上之範例實施例; 【主要元件對照表】 300 晶 片 302 接 合 墊 304 焊 接 凸 塊 306 能 量 源 308 佈 線 502 潤 濕 層 802 鑲 嵌 遮 罩 804 剪 下 區 域 806 熱 交 換 元件 808 鑲 嵌 遮 罩 1002 可 移 動 桌 -15- (13) 定位系統 X軸條 y軸條 基體 感測器 定位標記 感測器 加熱器 · 密封室 玻璃上部件 氣體入口 裝載自動控制裝置200421501 玖 玖, cross-reference to related invention descriptions The present invention claims the benefits of "Partial Reflow of Wiring Bonding and Flip Chip Connection" in US Provisional Application No. 60/43 4,474, filed on December 18, 2002, This reference contains its entirety. [Technical Field to which the Invention belongs] The present invention relates generally to soldering for electronic connection to a wafer, and more specifically to wiring bonding and flip-chip bonding. [Previous technology] Since the introduction of low dielectric (low-k) materials, many people have invested a lot of effort to develop new technologies and integrate old and known methods to solve the problems caused by dielectric materials formed of low-k materials. . Low-k materials are structurally and mechanically weaker than conventional insulators such as SiO2. Therefore, due to the delamination of the low-k layer and the cracking and cracking of the interconnect lines during the manufacturing process, the device is more likely to fail. For example, "the conventional technique of wiring bonding to a bonding pad or connecting a flip chip to a substrate" requires considerable pressure to be applied to the underlying metal structure during the bonding process. In addition, the fabrication of a flip chip connection usually requires heating the flip chip and the substrate in a furnace to a temperature not lower than the melting point of the soldering material that forms the joint between the flip chip and the substrate. In particular, if soldering the bumps, higher temperatures are needed to facilitate reflow and connection. For example, 20 to 30 degrees Celsius is higher than the melting point of the solder bumps (Pb-Sn eutectic alloy is 205 -22 Celsius). 0 degree). In addition, (2) (2) 200421501 right-side flip-chip connection, in addition to high temperature, due to the different thermal expansion coefficient of the flip-chip and the substrate, thermal stress will be generated when the wafer is cooled. As shown in Figures 1 A and 2B, when low-k materials are used, stress and thermal expansion associated with conventional techniques may cause defects to form in the low-k materials. Furthermore, countries in Asia and Europe will ban the use of 纟 α as a soldering material for electronic components as early as 2004. p b or s η P b eutectic alloys require lower soldering temperatures than lead-free solders with higher melting temperature characteristics such as S η or Ag C11. Therefore, the promotion of low-k materials and the prohibition of lead in electronic packaging, and thermal planning control will become the key to reduce or remove the damage to the metal layer during interconnection and flip-chip manufacturing. In some conventional techniques, the size of the bonding pad is reduced or strengthened to reduce the force applied to the metal layer. Although this can reduce some contact pressure, there are still thermal stresses and the effect of repeated contact pressure accumulation on the underlying metal layer. [Summary of the Invention] In an exemplary embodiment, a soldering system for chip electronic connection includes bonding pads, solder bumps, As well as energy sources. In this exemplary embodiment, the energy source is localized to the welding bump, but does not actually contact the welding bump. The local energy source heats the solder bumps to re-solder the solder bumps onto the bond pads without heating the entire wafer. [Embodiment] The following description discloses various specific configurations and parameters. It should be understood, however, that this description is not intended to limit the scope of the present invention, but should be considered as providing a description of example embodiments. Wiring Bonding Referring to FIG. 3A, in an exemplary embodiment, an electronic connection soldering system for a wafer 300 includes a bonding pad 302, a solder bump 304, and an energy source 306. In this exemplary embodiment, the energy source 306 is localized to the solder bumps 304 without actually touching the solder bumps 304. The local energy source 3 06 heats the solder bumps 3 04 to re-solder the solder bumps 3 04 on the bonding pads 3 02 without heating the entire wafer 300. In the embodiment shown in FIG. 3A, the solder bumps 304 are connected to the wiring 308. The solder bump 3 04 and the wiring 3 0 8 are located on the bonding pad 3 02, and the local energy source 3 0 6 heats the solder bump 3 0 4 located on the bonding pad 3 0 2. As shown in FIG. 3B, the solder bumps 3 0 4 and the wirings 3 0 8 form wiring bonds on the bonding pads 3 02. In this exemplary embodiment, the 'soldering bump 304 is preferably 96.5% tin and 3.5% silver tin. The solder bump 304 preferably has a melting point higher than 221 ° C. It should be understood, however, that other materials having other melting points may be used to form the solder bumps 304. In this exemplary embodiment, the local energy source 306 may include laser, x-ray, electronic Andy electric heater, infrared heater, and electron beam. When the local energy source 3 0 6 laser, the laser can be a solid-state laser (such as ruby, N cU glass, ND: YAG (Yttrium Aluminum Garnet, YMhO] 2), and the like, or a gas laser (Such as (4) (4) 200421501 HE-NE, CO2, HF, and the like). Referring to FIG. 4A, in another exemplary embodiment, before the welding bump 3 0 4 is positioned on the bonding pad 3 0 2, the local energy source 3 0 6 heats the welding bump 3 0 4. When the solder bump 3 04 has been melted by heating, the solder bump 3 04 and the wiring 3 08 are positioned on the bonding pad 3 02. As shown in FIG. 4B, the solder bumps 304 and the wirings 308 form wirings bonded to the bonding pads. Referring to FIG. 5A, in another exemplary embodiment, the welding bump 3 0 4 is positioned on the bonding pad 3 0 2 before the local energy source 3 0 6 heats the welding bump 3 0 4 and the bonding pad 3 0 2 . When the solder bump 3 04 has been melted by heating, the thermal solder bump 3 04 is positioned on the heating bonding pad 3 02. As shown in FIG. 5B, the 'soldering bumps 3 0 4 and the wirings 3 0 8 form wirings and are bonded to the bonding pads. In this exemplary implementation, a wetting layer 502 is formed on the bonding pad 302. The local energy source 3 02 melts the wetting layer 5 02 covering the bonding pad 3 02. The wetting layer 502 may include Au, CuTi, TiN, Tin, SbPb, SnAg alloy, and the like. In this example implementation, the local energy source 3 06 may include a first energy source 3 06 localized to the welding bump 3004 and a second energy source 3 06 localized to the bonding pad 302. The first energy source 3 06 heats the solder bump 30 04 and the second energy source 3 06 heats the bonding pad 30 02. Instead, the local energy source 3 06 series can be moved. The movable energy source 3 06 first heats the solder bump 3 04 and then moves to heat the bonding pad 3 02. Referring to FIG. 6A, in another exemplary embodiment, before the welding bump 3 04 is heated by the local energy source 3 06, the welding bump 3 04 is positioned on the joint -7- (5) (5) 200421501 pad 3 02 . As shown in FIG. 6B, after the solder bump 304 is heated, the wiring 308 is connected to the solder bump 304. In this exemplary embodiment, the local energy source 3 06 heats the wiring 3 0 8 and the solder bump 3 04, and then connects the heated wiring 3 0 8 to the heated solder bump 3 04 to form a wire bonded to the bonding pad 3 02 on. In this exemplary implementation, a wetting layer 502 is formed on the bonding pad 302. The local energy source 3 0 2 melts the wetting layer 5 2 covering the bonding pad 3 0 2. The wetting layer 502 may include Au, CuTi, TiN, Tin, SbPb, SnAg alloy, and the like. In this example implementation, the local energy source 306 may include a first energy source 306 localized to the wiring 308 and a second energy source 306 localized to the solder bump 304. The first energy source 306 heats the wiring 308, and the second energy source 306 heats the solder bump 304. Instead, the local energy source 3 06 series can be moved. The movable energy source 306 first heats the wiring 308, and then moves to heat the solder bump 304. Referring to FIG. 7, in an exemplary embodiment, the wafer 300 may include a plurality of bonding pads 302, a plurality of solder bumps 304, and wirings 308. As shown in Figure 7, multiple energy sources 306 can be used to heat multiple solder bumps 304. In particular, 'each energy source 3 0 6 is localized to each solder bump 3 0 4 to heat each solder bump 304 to resolder each solder bump 304 to each bonding pad 302' without heating the entire wafer 300 . Using multiple energy sources 3 06 to heat multiple solder bumps 3 0 4 can increase the efficiency of the reflow process. Referring to FIG. 8, in another exemplary embodiment, the mosaic mask 802 is disposed between the energy source 306 and the plurality of solder bumps 304. As shown in Fig. 8 (6) (6) 200421501, the mosaic mask 80 2 includes a cutout region 8 0 4 corresponding to the solder bump 3 0 4. Therefore, the energy source 3 0 6 is localized to each welding bump 3 04 through each cut-out region 8 0 4 to heat each welding bump 3 04 to re-solder each welding bump 3 04 on each bonding pad 3 02 Without heating the entire wafer 3,000. In this exemplary embodiment, the mosaic mask 802 may be an opaque material, preferably a metal or alloy with high conductivity and high melting point, such as Ti, W, Cu, Ta, Au, A1, and the like. Category. The mosaic mask 802 may be connected to the heat exchanging element 806 to maintain the temperature of the mosaic mask 802. The energy source 3 06 may be a wide beam laser, an infrared heating lamp, an electron beam, and the like. When the energy source 306 is an electron beam, the reflow process is best performed in a vacuum environment. Referring to FIG. 9, in another exemplary embodiment, the energy source 306 is movable. As shown in FIG. 9, the movable energy source 3 06 can be moved to between the solder bumps 3 04 to heat each solder bump 3 04 to resolder the solder bumps on the bonding pad 302 without heating the entire wafer 300. . As also shown in Fig. 9, the movable energy source 3 0 6 can move in the X, y, and y directions. It should be noted that the wafer 300 can remain stationary or move relative to the moving energy source 300. Referring to FIG. 10, in yet another exemplary embodiment, the wafer 300 is moved to position each welding bump 3 04 to adjacent energy source 3 06 to heat the welding bump 3 04 to re-solder a welding bump 304 to each bonding pad. 3 02 without heating the entire wafer 3 00. In this exemplary embodiment, the chip 300 can be placed on the movable table 1002 or any suitable mobile device. It should be noted that the wafer 300 may remain stationary or move relative to the moving energy source 306. Referring to FIG. 1, in another exemplary embodiment, the positioning system 1 102-9-(7) (7) 200421501 can be used to investigate and locate the position of the bonding pad 300 on the wafer 300. In this exemplary embodiment, the positioning system 1 102 may be an optical imaging system, such as a charge coupled device (CCD) camera. As shown in Fig. 11, the positioning system 1 102 can be connected to the energy source 3 06. The positioning system 1 102 and the energy source 3 06 may be disposed on and move along the X-axis bar 1 104, and the X-axis bar 1 104 may be moved along the y-axis bar 1 1 06. Therefore, in this exemplary embodiment, the positioning system 110 and the energy source can be moved to any position on the wafer. Flip-Chip Connection Referring to Figure 12A, the wafer 300 is bonded to the base 1200 and is commonly referred to as a flip-chip. As shown in FIG. 12A, the solder bump 3 04 is interposed between the flip chip 300 and the base body 1 200 to connect and bond the flip chip 300 and the base body 1 200. Generally, for a typical eutectic alloy of 63% Sn and 37% Pb, a flip chip connection requires a high melting point of 183 ° C and a solder deposition time of about 10 seconds. A longer solder deposition time will cause longer contact pressure on the dielectric layer of the wafer 300, which may be a defect in the dielectric layer early, especially when the dielectric layer includes a low-k material. Therefore, in this exemplary embodiment, the energy source 306 is localized to the solder bump 304 located between the flip chip 300 and the substrate 1 200. As shown in FIG. 12B, the local energy source 3 06 heats the solder bump 3 04 until the solder bump 3 04 is re-soldered to an hourglass shape connected between the flip chip 3 00 and the substrate 1 2 0 0 . Referring to FIG. 13, in an exemplary embodiment, the flip chip 300 may (8) (8) 200421501 include a plurality of solder bumps 3 (M. In this exemplary embodiment, the mosaic mask 802 may be placed Between the energy source 306 and the plurality of welding bumps 304. As shown in FIG. 13, the mosaic mask 802 includes a cut-out area 804 corresponding to the welding bump 304. Therefore, the 'energy source 3 0 The 6 series is localized to each solder bump 3 0 4 by each cut-out area 8 0 4 to heat each solder bump 3 0 4 to resolder each solder bump 3 0 4 on each bonding pad 3 02, and The entire flip chip 300 is not heated. Specifically, in this exemplary embodiment, the energy source 306 heats the solder bumps 304 on the flip chip 300 by heating the solder bumps 304 on the substrate 1200. Therefore, in this exemplary embodiment, a sensor 1302 can be equipped to scan the positioning mark 1304 behind the base body 1 200 to position the mosaic mask 8 04 on the base body 1 200. The sensor 1306 can also be equipped. To adjust the position relative to the flip chip 3 0 0 base 1 2 0 0. In this exemplary embodiment, the sensors 1 3 02 and 1 3 06 are optical sensors. However, it should be noted that Other types of sensors are used. In this exemplary embodiment, the flip chip is located on the movable table 1 002, and the movable table 1 002 moves the flip chip 3 00 relative to the inlay mask 802. As shown in FIG. 13 As shown, the movable table 1002 can be moved in the directions of x, y, z, and theta. Referring to FIG. 14, in another exemplary embodiment, a heater 140 can be used to heat the flip chip 300. The heater 1 402 heats Flip chip 300 to reduce the amount of power required from energy source 3 06. However, heater 1402 heats flip chip 300 to a temperature lower than the melting point of solder bump 3004 in flip chip 300. Refer to Section 1 Figure 5, in yet another exemplary embodiment, the flip chip 3 0 0 (9) (9) 200421501 and the substrate 1 2 0 0 are placed in a sealed chamber} 5 〇2. As shown in Figure i 5 ' The mosaic mask 8 02 is placed outside the sealed 1502. In this exemplary embodiment, the sealed chamber 1 50 02 includes a glass upper part 1 5 04. Therefore, the energy source 306 is cut by the mosaic mask 802 The lower area 804 and the upper glass part 1 5 04 are localized to the solder bumps 304 on the flip chip 300 to re-solder the solder bumps 3 04, without heating the entire flip chip 3 00. In this exemplary embodiment, the sealed chamber 1502 has a controlled temperature. As shown in FIG. 15, the sealed chamber 1502 has a gas inlet 1506. During the reflow process, When the solder bump 304 is re-soldered, for example, a blunt gas of nitrogen is introduced from the gas inlet 1506 to reduce or prevent oxidation of the solder bump 304. After reflow, a cooling gas such as nitrogen is introduced through the gas inlet 1506 to cool the flip chip 300 and the substrate 1200 to reduce or minimize the thermal effect generated during the reflow process. Referring to FIGS. 16A, 16B, and 16C, an example process of re-soldering the solder bumps 304 on the flip chip 300 will be described. In particular, in FIG. 16A, a mosaic mask 802 is used to localize the energy source 3 06 to the solder bump 304 on the flip chip 300, and the solder bump 304 is heated at a temperature higher than the melting point of the solder bump 304. The solder bumps 304 are re-soldered without heating the entire flip chip 300. In detail, the solder bump 3 04 is heated to a temperature of 10 to 100 degrees Celsius higher than the melting point of the solder bump 3 04, preferably 50 degrees Celsius. In FIG. 16, when the temperature of the solder bump 3 04 on the flip chip 300 is higher than the melting point of the solder bump 300, the solder bump on the bonding pad or the substrate 1 200 and the flip chip 300 The solder bumps 3 04 are in contact. In FIG. 16C, the solder bump 3 04 of the flip chip 300 and the bonding pad or base (10) (10) 200421501 body 1 200 are kept in contact until the solder bump on the flip chip 300. Block 3 04 is cooled below the melting point of solder bump 304 on flip chip 300. Referring to FIGS. I7A, 17B, and 17C, in an exemplary embodiment, the substrate 1 200 is a printed circuit board / card. Therefore, the flip chip is bonded to the printed circuit board / card 1200. Referring to FIG. 18A, in an exemplary embodiment, the flip chip 300 is placed on the movable table 1002. The movable table 1 002 moves the flip chip 300 to a first position lower than the mosaic mask 8 08 and a second position lower than the base 1200. When the flip chip 300 is in the first position, the solder bump 3 04 of the flip chip 300 is heated by the heating source 3 06 through the mounting device 8 0 8. As shown in FIG. 18B, when the flip chip 300 is in the second position, the solder bump on the bonding pad or the substrate 1200 is in contact with the solder bump 300 on the flip chip 300. Referring to FIG. 19A, in yet another exemplary embodiment, the flip chip 300 is kept stationary. The inlaid mask 8 0 8 and the energy source 3 0 6 are moved to the vicinity of the flip chip 300 to heat the solder bump 3 04 of the flip chip 300. As shown in FIG. 19B, when the solder bump 3 04 of the flip chip 300 has been heated, the substrate 1200 is moved to the adjacent position of the flip chip 300, so that the solder bump or the bonding pad of the base 1 2 00 and The solder bumps 304 of the flip chip 300 are in contact. In this exemplary embodiment, the loading automatic control device 1902 moves the substrate 1200 to contact the solder bumps or bonding pads of the substrate 1200 with the solder bumps 304 of the flip chip 300. Although the exemplary embodiment has been described, a variety of changes can be made without departing from the spirit and scope of the invention -13- (11) (11) 200421501. Therefore, the present invention should not be limited to the specific forms described above and shown in the drawings. [Brief description of the drawings] The present invention can be easily understood by referring to the above description and the accompanying drawings, wherein similar elements will be represented by similar symbols. Figure 1 shows the prior art of using contact pressure to hold and solder the wiring on the bonding pads; Figures 2A and 2B show the prior art of reflow soldering materials between the flip chip and the substrate using a furnace; Figures 3, 38 Figure 4, Figure 48, Figure 48, Figure 5, Figure 8, Figure 6, and Figure 66 show example embodiments of heating welding bumps using local energy sources. Figure 7 shows the use of multiple local energy sources to heat multiple welding solder bumps. Example embodiment; Figure 8 shows an example embodiment of heating multiple welding bumps using an energy source localized by a mosaic mask; Figure 9 shows using a movable local energy source to heating multiple welding solder bumps Example embodiment; FIG. 10 shows an example embodiment using a fixed energy source and a mobile table to heat a plurality of welding welding bumps; FIG. 1 shows an example embodiment using a positioning system and an energy source 12A and 12B The figure shows an example embodiment using a local energy source to heat bond the inverted S-wafer to the substrate; • 14- (12) (12) 200421501 Figures 1 3 -1 5 shows the use of an energy source localized by a mosaic mask to Example embodiments of heating multiple solder bumps to bond flip-chips to a substrate Figures 16A, 16B, and 16C show example embodiments of bonding flip-chips to a substrate; Figures 17A, 17B, and 17C show bonding Example embodiment of mounting a wafer on a printed circuit board / card. Figures 18A and 18B show an example of bonding a flip chip to a substrate using a movable table. Figures 19A and 19B show bonding using a loading automatic control device. Example embodiment of flip chip on the substrate; [Comparison table of main components] 300 wafers 302 bonding pads 304 solder bumps 306 energy source 308 wiring 502 wetting layer 802 mosaic mask 804 cut-out area 806 heat exchange element 808 mosaic mask Cover 1002 Movable table -15- (13) Positioning system X-axis bar y-axis bar Base sensor Positioning mark sensor Heater · Sealed chamber glass upper part Gas inlet automatic control device
-16--16-
Claims (1)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US43447402P | 2002-12-18 | 2002-12-18 |
Publications (1)
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TW200421501A true TW200421501A (en) | 2004-10-16 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092135994A TW200421501A (en) | 2002-12-18 | 2003-12-18 | Localized reflow for wire bonding and flip chip connections |
Country Status (3)
Country | Link |
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AU (1) | AU2003303155A1 (en) |
TW (1) | TW200421501A (en) |
WO (1) | WO2004057648A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105518888A (en) * | 2015-09-09 | 2016-04-20 | 歌尔声学股份有限公司 | Method for repairing micro-LED, manufacture method, device and electronic device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI698964B (en) * | 2019-03-15 | 2020-07-11 | 台灣愛司帝科技股份有限公司 | Chip fastening structure and chip fastening apparatus |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4955523A (en) * | 1986-12-17 | 1990-09-11 | Raychem Corporation | Interconnection of electronic components |
US4926022A (en) * | 1989-06-20 | 1990-05-15 | Digital Equipment Corporation | Laser reflow soldering process and bonded assembly formed thereby |
US5946553A (en) * | 1991-06-04 | 1999-08-31 | Micron Technology, Inc. | Process for manufacturing a semiconductor package with bi-substrate die |
US5985693A (en) * | 1994-09-30 | 1999-11-16 | Elm Technology Corporation | High density three-dimensional IC interconnection |
US5731244A (en) * | 1996-05-28 | 1998-03-24 | Micron Technology, Inc. | Laser wire bonding for wire embedded dielectrics to integrated circuits |
US6082610A (en) * | 1997-06-23 | 2000-07-04 | Ford Motor Company | Method of forming interconnections on electronic modules |
US6258627B1 (en) * | 1999-01-19 | 2001-07-10 | International Business Machines Corporation | Underfill preform interposer for joining chip to substrate |
JP2001077524A (en) * | 1999-09-03 | 2001-03-23 | Fujitsu Ltd | Method and device for reflow soldering |
US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
JP2002151534A (en) * | 2000-11-08 | 2002-05-24 | Mitsubishi Electric Corp | Method for forming electrode and semiconductor device and substrate for use therein |
US6458623B1 (en) * | 2001-01-17 | 2002-10-01 | International Business Machines Corporation | Conductive adhesive interconnection with insulating polymer carrier |
-
2003
- 2003-12-18 TW TW092135994A patent/TW200421501A/en unknown
- 2003-12-18 WO PCT/US2003/040638 patent/WO2004057648A2/en not_active Application Discontinuation
- 2003-12-18 AU AU2003303155A patent/AU2003303155A1/en not_active Abandoned
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105518888A (en) * | 2015-09-09 | 2016-04-20 | 歌尔声学股份有限公司 | Method for repairing micro-LED, manufacture method, device and electronic device |
WO2017041253A1 (en) * | 2015-09-09 | 2017-03-16 | Goertek. Inc | Repairing method, manufacturing method, device and electronics apparatus of micro-led |
CN105518888B (en) * | 2015-09-09 | 2018-06-12 | 歌尔股份有限公司 | Restorative procedure, manufacturing method, device and the electronic equipment of micro- light emitting diode |
US10170665B2 (en) | 2015-09-09 | 2019-01-01 | Goertek.Inc | Repairing method, manufacturing method, device and electronics apparatus of micro-LED |
Also Published As
Publication number | Publication date |
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AU2003303155A8 (en) | 2004-07-14 |
WO2004057648A3 (en) | 2005-02-17 |
AU2003303155A1 (en) | 2004-07-14 |
WO2004057648A2 (en) | 2004-07-08 |
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