JP2005259925A - Mounting method - Google Patents

Mounting method Download PDF

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JP2005259925A
JP2005259925A JP2004068483A JP2004068483A JP2005259925A JP 2005259925 A JP2005259925 A JP 2005259925A JP 2004068483 A JP2004068483 A JP 2004068483A JP 2004068483 A JP2004068483 A JP 2004068483A JP 2005259925 A JP2005259925 A JP 2005259925A
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contact
electronic component
chip
substrate
mounting
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Hisashi Hayakawa
寿 早川
Yuji Nishitani
祐司 西谷
Hiroshi Asami
浅見  博
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Sony Corp
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Sony Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the mounting method of a chip-shaped electronic component, capable of high reliability junction by restraining the production of an alloy due to intermetallic diffusion. <P>SOLUTION: Before a solder ball 14, formed on the side of an IC chip 10, makes contact with the wiring land 2 of a substrate 1, the solder ball 14 is heated beyond a melting point and melted, and is brought into contact with the wiring land 2 in the molten state. The molten state is kept after the contacting, and then heating is stopped and cooling is applied. Consequently, since jointing time is shortened to restrain alloy formation and proper jointing is made. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、例えばフェイスダウンでの電子部品の実装に好適な実装方法に関するものである。   The present invention relates to a mounting method suitable for mounting electronic components, for example, face down.

従来、半導体チップ等のチップ部品の端子接続法としては、例えば電子機器の製造に広く用いられているように、Sn−Pb系の共晶はんだ等を用いてチップ部品をダイボンドするタイプの半導体装置や、チップ部品をフリップチップ接続するBGA(Ball Grid Array)又はCSP(Chip Scale Package)により接続される半導体装置等で適用されている。   Conventionally, as a terminal connection method of a chip component such as a semiconductor chip, a semiconductor device of a type in which a chip component is die-bonded using Sn—Pb-based eutectic solder or the like as widely used in the manufacture of electronic equipment, for example. In addition, it is applied to a semiconductor device connected by BGA (Ball Grid Array) or CSP (Chip Scale Package) for flip-chip connection of chip components.

特に、チップ部品をフリップチップ接続する場合には、一般にC4(Controlled Collapse Chip Connection)接続と称される、はんだバンプを電子部品の電極とプリント配線板の電極との間に用い、リフローにより接合する方法が知られている。   In particular, when flip-chip connection of chip parts is performed, solder bumps are used between the electrodes of the electronic parts and the electrodes of the printed wiring board, commonly referred to as C4 (Controlled Collapse Chip Connection) connection, and are joined by reflow. The method is known.

図17は、上記したC4と言われるSn−Pb共晶ボールを用い、ICチップ10側の電極11と基板1の配線ランド2とを接合するプロセスを示す概略図である。   FIG. 17 is a schematic diagram showing a process of bonding the electrode 11 on the IC chip 10 side and the wiring land 2 of the substrate 1 using the above-described Sn—Pb eutectic ball called C4.

即ち、図17(a)に示すように、実装されるICチップ10の電極11にはんだボール14を形成し、これを例えば不図示のヘッド等を用いてプリント配線板(以下、基板と称する。)1の配線ランド2上方に配置して位置合せを行った後、図17(b)に示すように、はんだボール14を配線ランド2に接触させる。なお、基板1には、はんだレジスト及びフラックス等が存在するが図示省略する。   That is, as shown in FIG. 17A, solder balls 14 are formed on the electrodes 11 of the IC chip 10 to be mounted, and this is referred to as a printed wiring board (hereinafter referred to as a substrate) using a head (not shown), for example. ) After being positioned above the wiring land 2 of 1, the solder balls 14 are brought into contact with the wiring land 2 as shown in FIG. In addition, although the solder resist and flux etc. exist in the board | substrate 1, illustration is abbreviate | omitted.

次に、はんだボール14が配線ランド2に接触した状態で、ICチップ10と基板1とを所定間隔に保持する治具を用いて、不図示のリフロー炉に搬入してリフローすることにより、図17(c)に示すように、はんだ14がフィレット形をなしてICチップ10と基板1との接合が行われ、ICチップ10及び基板1に荷重をかけずに実装することができる。   Next, with the solder balls 14 in contact with the wiring lands 2, using a jig for holding the IC chip 10 and the substrate 1 at a predetermined interval, they are carried into a reflow furnace (not shown) and reflowed. As shown in 17 (c), the solder 14 has a fillet shape, and the IC chip 10 and the substrate 1 are joined, so that the IC chip 10 and the substrate 1 can be mounted without applying a load.

この場合、電極11にCuスタッドバンプ(後述する図18参照)を突設し、この上にはんだボール14を配することもできる。   In this case, a Cu stud bump (see FIG. 18 to be described later) is projected from the electrode 11 and the solder ball 14 can be disposed thereon.

また、図18は、FC(Flip Chip)ボンダーを用いてICチップを基板へ実装するプロセスを示す概略図である。   FIG. 18 is a schematic view showing a process of mounting an IC chip on a substrate using an FC (Flip Chip) bonder.

まず、図18(a)に示すように、基板1表面の配線2A上にパターン印刷により絶縁膜3を部分的に配して被覆し、被覆されていないランド2を形成した後、図18(b)に示すように、ランド間及びランド2上にUF(アンダーフィル)樹脂4が滴下される。   First, as shown in FIG. 18 (a), the insulating film 3 is partially arranged and coated on the wiring 2A on the surface of the substrate 1 by pattern printing to form an uncoated land 2; As shown in b), UF (underfill) resin 4 is dropped between lands and on lands 2.

次に、図18(c)に示すように、実装されるICチップ10の電極11にCuスタッドバンプ12を設けてこの上にはんだボール14を形成し、このICチップ10をヒーター9によって加熱された吸着ヘッド8で把持してはんだボール14を80℃に加熱し、この状態で基板1上方に配し、位置合せしながら下降される。   Next, as shown in FIG. 18 (c), Cu stud bumps 12 are provided on the electrodes 11 of the IC chip 10 to be mounted, and solder balls 14 are formed thereon, and the IC chip 10 is heated by the heater 9. The solder ball 14 is heated to 80 ° C. by being held by the suction head 8, placed in this state above the substrate 1, and lowered while being aligned.

次に、図18(d)に示すように、吸着ヘッド8で加圧(数10g/1ピン当たり)しながらはんだボール14を流動性のUF樹脂4の中に押し込み、はんだボール14を配線ランド2に接触させた後に、吸着ヘッド8に内設のヒーター9によって吸着ヘッド8を220℃〜250℃に昇温し、この吸着ヘッド8に把持されたICチップ10の電極11上のはんだボール14を加熱溶融し、図19(e)に示すように、例えば2秒間はんだ14の溶融状態を保持する。また、この加熱によりUF樹脂4も硬化する。そして、このようなはんだボール14の接触の検知にはカメラ等が用いられる。   Next, as shown in FIG. 18 (d), the solder ball 14 is pushed into the fluid UF resin 4 while being pressurized (several tens of grams per pin) by the suction head 8, and the solder ball 14 is inserted into the wiring land. 2, the suction head 8 is heated to 220 ° C. to 250 ° C. by a heater 9 provided in the suction head 8, and the solder balls 14 on the electrodes 11 of the IC chip 10 held by the suction head 8. As shown in FIG. 19E, the molten state of the solder 14 is maintained for 2 seconds, for example. Further, the UF resin 4 is also cured by this heating. A camera or the like is used to detect such contact of the solder balls 14.

次に図19(f)に示すように、吸着ヘッド8によるはんだ14の加熱を止め、例えば冷風を吹き付けてはんだ14を冷却し、固化させることにより、ICチップ10の電極11が基板1の配線ランド2に結合される。そして約150℃に冷却後、図19(g)に示すように、ヘッドを離脱させて実装完了する。   Next, as shown in FIG. 19 (f), the heating of the solder 14 by the suction head 8 is stopped, and the solder 14 is cooled and solidified by blowing, for example, cold air, whereby the electrode 11 of the IC chip 10 is connected to the wiring of the substrate 1. Coupled to land 2. Then, after cooling to about 150 ° C., the head is detached as shown in FIG.

図20は、上記したプロセスにおける各工程の所要時間とはんだ温度の関係を示すグラフである。   FIG. 20 is a graph showing the relationship between the time required for each step and the solder temperature in the above-described process.

即ち、はんだ14は80℃に加熱された状態で基板1の配線ランド2に接触後に加熱され、8秒で220℃に昇温して溶融し、この溶融状態を2秒間保持され、その後に加熱を止めて2秒間冷却され、これによりICチップ10の電極11と基板1の配線ランド2とが結合する。そして、約150℃に降温したときにヘッド8が離脱される。従って、昇温〜溶融保持時間までの間(10秒間)に金属間の拡散現象が持続される。   That is, the solder 14 is heated after contacting the wiring land 2 of the substrate 1 while being heated to 80 ° C., heated to 220 ° C. in 8 seconds and melted, and this molten state is held for 2 seconds, and then heated. Then, the electrode 11 of the IC chip 10 and the wiring land 2 of the substrate 1 are combined. When the temperature is lowered to about 150 ° C., the head 8 is detached. Accordingly, the diffusion phenomenon between the metals is maintained during the period from the temperature rise to the melt holding time (10 seconds).

つまり、上記したように、この接合法は、はんだボール14と基板1の配線ランド2が接触後に、はんだ14を加熱溶融することに伴うCuバンプ12と配線ランド2との金属の拡散接合とUF樹脂4による固定力を用いている。   In other words, as described above, this bonding method is performed by the metal diffusion bonding and the UF between the Cu bump 12 and the wiring land 2 accompanying the heat melting of the solder 14 after the solder ball 14 and the wiring land 2 of the substrate 1 are in contact with each other. The fixing force by the resin 4 is used.

このようなICチップの実装技術については、チップ側に設けたはんだバンプをはんだの融点温度よりも低い温度に加熱し、チップと基板との間を加圧してはんだバンプを塑性変形させながら接触させた後に、はんだバンプを融点温度以上に加熱し、チップの自重のみの圧力で接続させることが開示されている(後述の特許文献参照)。   Regarding such IC chip mounting technology, the solder bumps provided on the chip side are heated to a temperature lower than the melting point temperature of the solder, and the solder bumps are contacted while being plastically deformed by pressing between the chip and the substrate. After that, it is disclosed that the solder bumps are heated to the melting point temperature or more and are connected by the pressure of only the weight of the chip (see the patent document described later).

特許法第3198555号(第1頁第1欄第6〜12行目、第2頁第4欄21〜26行目及び第3頁第5欄第12〜15行目)、図1)Japanese Patent No. 3198555 (page 1, column 1, lines 6-12, page 2, column 4, lines 21-26 and page 3, column 5, lines 12-15), FIG. 1)

しかしながら、図17に示した従来の実装方法では、ICチップ10側のはんだボール14や配線ランド2に高さのばらつきや反りがある場合には、はんだボール14と配線ランド2との間の距離が均一でないため、全ての接続部において接合をとることは困難であると共に、長い接合時間を要する。   However, in the conventional mounting method shown in FIG. 17, the distance between the solder ball 14 and the wiring land 2 when the solder ball 14 or the wiring land 2 on the IC chip 10 side has a height variation or warpage. Is not uniform, it is difficult to bond at all the connecting portions, and a long bonding time is required.

また、図18〜図19に示した従来の実装方法では、接合時にICチップ側の全てのはんだボール14と基板1の配線ランド2とを接触させ、金属間の拡散接合を促進させるために、接合時にはかなり大きな荷重が必要であり、この加圧によりICチップ10がダメージを受け易い。   Further, in the conventional mounting method shown in FIGS. 18 to 19, in order to bring all the solder balls 14 on the IC chip side into contact with the wiring lands 2 of the substrate 1 at the time of bonding, and to promote diffusion bonding between metals, A considerably large load is required at the time of bonding, and the IC chip 10 is easily damaged by this pressurization.

つまり、接触時に溶融前の固形の各はんだボール14に数10gの荷重がかけられて配線ランド2に当接するため、薄型のICチップ10がはんだボール14を介して下からの圧力を受け、この圧力によるストレスを生じるため、チップ表面のlow k膜がダメージを受け、界面でクラックが生じ易くなると共に、接合時間が長い。   In other words, since a load of several tens of grams is applied to each solid solder ball 14 before melting at the time of contact and comes into contact with the wiring land 2, the thin IC chip 10 receives pressure from below through the solder ball 14, and this Since stress due to pressure is generated, the low-k film on the chip surface is damaged, cracks are likely to occur at the interface, and the bonding time is long.

その結果、図21(上記したICチップ10の単一の電極11と基板1の単一の配線ランド2近傍の拡大図)に示すように、チップ電極11上のCuスタッドバンプ12と、基板の配線ランド2を構成しているCu層5及びNi(ニッケル)層6、Au(銀)層7との間において、矢印で示すように金属原子の拡散による合金層15が生成されることにより結合されるものであるが、接合時間が長いとこの生成合金層15が厚くなってしまい、結合部が脆くなる。   As a result, as shown in FIG. 21 (enlarged view of the vicinity of the single electrode 11 of the IC chip 10 and the single wiring land 2 of the substrate 1), the Cu stud bump 12 on the chip electrode 11 and the substrate Bonded by forming an alloy layer 15 by diffusion of metal atoms between the Cu layer 5, the Ni (nickel) layer 6, and the Au (silver) layer 7 constituting the wiring land 2, as indicated by arrows. However, if the joining time is long, the resulting alloy layer 15 becomes thick and the joint becomes brittle.

このような接合部は、−25℃と125℃との間での温度サイクル試験(加速テスト)を行うと、1000回でクラックを生じてしまう。   When such a joint is subjected to a temperature cycle test (acceleration test) between −25 ° C. and 125 ° C., cracks occur 1000 times.

このように、上記のいずれにおいても接合に要する時間が長いため、接合部に脆い金属間化合物ができる。従って、この金属間化合物が接合の信頼性を低減することが懸念される。しかし、上記した特許文献1は、はんだを融点温度で更に長時間(5〜30秒)加熱するので、更に金属間化合物が厚くなり、接合部の良好な接合を得ることはできない。   Thus, in any of the above, since the time required for bonding is long, a brittle intermetallic compound is formed at the bonded portion. Therefore, there is a concern that this intermetallic compound reduces the reliability of bonding. However, in Patent Document 1 described above, since the solder is heated at the melting point for a longer time (5 to 30 seconds), the intermetallic compound becomes thicker and a good joint cannot be obtained.

そこで本発明の目的は、金属間の拡散による合金生成を抑制して、信頼性の高い接合を短時間で形成可能な実装方法を提供することにある。   Therefore, an object of the present invention is to provide a mounting method capable of forming a highly reliable bond in a short time by suppressing alloy formation due to diffusion between metals.

即ち、本発明は、
電子部品と前記実装基板とを互いに接触させない非接触状態で、導電性の低融点接合 材を前記電子部品及び前記実装基板のいずれかに配して前記低融点接合材を軟化点以上 の温度に加熱する工程と、
前記加熱温度下で前記電子部品と前記実装基板とを互いに接触させる工程と、
この接触後に前記低融点接合材を溶融状態に保持する工程と、
前記溶融状態から降温して前記低融点接合材を固化させる工程と
を有する実装方法(以下、本発明の実装方法と称する。)に係るものである。
That is, the present invention
In a non-contact state where the electronic component and the mounting substrate are not in contact with each other, a conductive low melting point bonding material is disposed on either the electronic component or the mounting substrate, and the low melting point bonding material is brought to a temperature equal to or higher than the softening point. Heating, and
Bringing the electronic component and the mounting substrate into contact with each other under the heating temperature;
Holding the low melting point bonding material in a molten state after this contact;
And a step of solidifying the low melting point bonding material by lowering the temperature from the molten state (hereinafter referred to as a mounting method of the present invention).

本発明の実装方法によれば、電子部品と実装基板との接触前に低融点接合材を軟化点以上の温度に加熱し、この状態で電子部品と実装基板とを接触させるため、互いに圧力をかけないで接触させて低融点接合材を溶融状態に保持し、更にこれを降温して固化することができる。   According to the mounting method of the present invention, the low melting point bonding material is heated to a temperature equal to or higher than the softening point before contact between the electronic component and the mounting substrate, and in this state, the electronic component and the mounting substrate are brought into contact with each other. The low melting point bonding material can be held in a molten state by being brought into contact without being applied, and further cooled to be solidified.

その結果、電子部品にダメージを生じることなく、低融点接合材の高さ又は/及び相手材の高さにばらつきがあっても確実に接合でき、接合に要する加熱時間を短縮して接合部における金属間化合物の生成を抑制しかつ実装基板の熱変形も低減できる。   As a result, even if there is a variation in the height of the low melting point bonding material and / or the height of the mating material without causing damage to the electronic components, it is possible to reliably bond, shortening the heating time required for the bonding, Generation of intermetallic compounds can be suppressed and thermal deformation of the mounting substrate can also be reduced.

上記した実装方法においては、前記非接触状態で前記低融点接合材を加熱して溶融させ、この溶融状態のまま、前記電子部品と前記実装基板とを互いに接触させるか又は、前記非接触状態で前記低融点接合材を加熱して軟化させ、この軟化状態のまま、前記電子部品と前記実装基板とを互いに接触させることが、前記接触後の低融点接合材の昇温時間を省き又は短縮できる点で望ましい。 In the mounting method described above, the low-melting-point bonding material is heated and melted in the non-contact state, and the electronic component and the mounting substrate are brought into contact with each other in the molten state, or in the non-contact state. Heating and softening the low-melting-point bonding material and keeping the electronic component and the mounting substrate in contact with each other in this softened state can save or shorten the temperature rise time of the low-melting-point bonding material after the contact. Desirable in terms.

この場合、前記電子部品の電極上に前記低融点接合材を被覆してバンプを形成し、このバンプの少なくとも最上層を前記軟化点以上に加熱した後に、前記バンプを前記実装基板の配線ランドに接触させることが望ましい。   In this case, a bump is formed by covering the electrode of the electronic component with the low melting point bonding material, and after heating at least the uppermost layer of the bump to the softening point or higher, the bump is applied to the wiring land of the mounting substrate. It is desirable to contact.

そして、前記電子部品を保持具に保持し、この保持具から前記軟化点以上の加熱を行うことが望ましい。   And it is desirable to hold | maintain the said electronic component in a holder, and to heat more than the said softening point from this holder.

この場合、前記低融点接合材を前記固化させた後に、前記電子部品を保持している保持具を前記電子部品から離脱させることが望ましい。   In this case, it is preferable that the holder holding the electronic component is detached from the electronic component after the low melting point bonding material is solidified.

また、前記実装基板上にアンダーフィル材を予め付着させておき、前記低融点接合材を配した前記電子部品を前記実装基板に接触させることが望ましい。   In addition, it is preferable that an underfill material is attached in advance on the mounting substrate, and the electronic component on which the low melting point bonding material is disposed is brought into contact with the mounting substrate.

また、前記軟化点以上の加熱を前記実装基板から行うようにしてもよい。   Further, heating above the softening point may be performed from the mounting substrate.

また、前記電子部品として、チップ状電子部品、又はチップ状電子部品に個片化されるべきウェーハを用い、このウェーハを用いる場合には、前記低融点接合材の前記固化後に前記ウェーハをチップ状電子部品に個片化することもできる。   Further, as the electronic component, a chip-shaped electronic component or a wafer to be separated into chip-shaped electronic components is used, and when this wafer is used, the wafer is chip-shaped after the solidification of the low melting point bonding material. It can also be separated into electronic parts.

そして、前記電子部品と前記実装基板との少なくとも一方に、これらの前記接触を検知するセンサー手段を設けることが、接触による圧力を防止できる点で望ましい。   In addition, it is desirable that at least one of the electronic component and the mounting board be provided with sensor means for detecting the contact, because pressure due to contact can be prevented.

この場合、前記電子部品に前記センサー手段を突出して設け、このセンサー手段が前記実装基板に接触したことを検知して、前記電子部品と前記実装基板との前記接触時の位置を決めることが望ましい。   In this case, it is desirable to project the sensor means on the electronic component, and to detect that the sensor means has contacted the mounting substrate, and to determine the position at the time of contact between the electronic component and the mounting substrate. .

ここにおいて、上記の「導電性の低融点接合材」とは、はんだ等の低融点金属、例えばSn−Pb、Sn−Ag、Sn、Pb、In、Sn−Ag−In等の如く、導電性、低融点であって、導電性の相手材との合金接合を形成しうる材料を指す。   Here, the above “conductive low melting point bonding material” is a low melting point metal such as solder, for example, Sn—Pb, Sn—Ag, Sn, Pb, In, Sn—Ag—In, etc. A material having a low melting point and capable of forming an alloy joint with a conductive counterpart.

次に、上記した本発明の好ましい実施の形態を図面参照下で具体的に説明する。   Next, the preferred embodiments of the present invention will be described in detail with reference to the drawings.

実施の形態1
図1及び図2は本実施の形態の実装プロセスを示す概略図であるが、基本的なプロセスは既述した従来例(図18及び図19)と同様である。
Embodiment 1
1 and 2 are schematic diagrams showing the mounting process of the present embodiment, but the basic process is the same as the conventional example (FIGS. 18 and 19) already described.

即ち、まず図1(a)に示すように、基板1表面の配線2A上にパターン印刷によって絶縁膜3を部分的に配し、被覆することにより、被覆のないランド2を形成した後に、図1(b)に示すように、ランド間及びランド2上にUF樹脂4を滴下する。   That is, first, as shown in FIG. 1A, an insulating film 3 is partially arranged on a wiring 2A on the surface of a substrate 1 by pattern printing and covered to form an uncovered land 2; As shown in 1 (b), the UF resin 4 is dropped between lands and on the lands 2.

次に、図1(c)に示すように、実装するICチップ10の電極11にCuスタッドバンプ12を設けてこの上にはんだボール14を形成し、このICチップ10をヒーター9によって加熱された吸着ヘッド8で把持してはんだボールを80℃に加熱し、この状態のICチップを基板1の上方に配置する。   Next, as shown in FIG. 1 (c), Cu stud bumps 12 are provided on the electrodes 11 of the IC chip 10 to be mounted, solder balls 14 are formed thereon, and the IC chip 10 is heated by the heater 9. The solder ball is heated to 80 ° C. by being held by the suction head 8, and the IC chip in this state is disposed above the substrate 1.

次に、図1(d)に示すように、はんだボール14が配線ランド2に接触する前に、吸着ヘッド8に内設のヒーター9でヘッド8を220℃〜250℃に昇温してはんだボール14を加熱し、スタッドバンプ12上のはんだボール14を溶融する。この場合、溶融したはんだの酸化を防止するために、窒素雰囲気中での接合が望ましい。   Next, as shown in FIG. 1 (d), before the solder balls 14 contact the wiring lands 2, the temperature of the head 8 is raised to 220 ° C. to 250 ° C. with the heater 9 provided in the suction head 8. The balls 14 are heated to melt the solder balls 14 on the stud bumps 12. In this case, in order to prevent the molten solder from being oxidized, bonding in a nitrogen atmosphere is desirable.

次に、図2(e)に示すように、はんだボール14が溶融状態のICチップを下降させて基板1に接触させる。従って、溶融状態のはんだボール14が、これよりも低粘性で流動性のUF樹脂4をはじきながら、加圧なしで基板1の配線ランド2に接触する。従って、UF樹脂4も加熱されて硬化する。この場合、はんだボール14及び基板1の配線ランド2の高さばらつきを考慮し、ばらつき範囲以上にICチップ10を下降させることが重要である。   Next, as shown in FIG. 2E, the IC chip in which the solder balls 14 are in the molten state is lowered and brought into contact with the substrate 1. Accordingly, the molten solder ball 14 comes into contact with the wiring land 2 of the substrate 1 without applying pressure while repelling the fluid UF resin 4 having a lower viscosity than that. Accordingly, the UF resin 4 is also heated and cured. In this case, it is important to lower the IC chip 10 beyond the variation range in consideration of variations in the heights of the solder balls 14 and the wiring lands 2 of the substrate 1.

次に、図2(g)に示すように、吸着ヘッド8によるはんだ14の加熱を止め、例えば冷風を吹きつけてはんだ14を冷却して結合させる。約150℃に冷却後、図2(h)に示すように、吸着ヘッドを離脱し、実装を完了する。実装後、吸着ヘッド8は未冷却状態(約180℃)で次のICチップを把持するのではんだボールを早く溶融することができる。これらの場合、吸着ヘッド8で把持するチップ数は、1チップ/1ヘッド又は複数チップ/1ヘッドとすることができる。後述する他の実施の形態及び変形例も同様。   Next, as shown in FIG. 2G, the heating of the solder 14 by the suction head 8 is stopped, and for example, cold air is blown to cool and bond the solder 14. After cooling to about 150 ° C., the suction head is detached as shown in FIG. After mounting, the suction head 8 holds the next IC chip in an uncooled state (about 180 ° C.), so that the solder ball can be melted quickly. In these cases, the number of chips held by the suction head 8 can be 1 chip / 1 head or a plurality of chips / 1 head. The same applies to other embodiments and modifications described later.

上記したように、本実施の形態の特徴は、既述した従来例(図18及び図19参照)が、はんだボール14を配線ランド2に接触後に加熱溶融していることとは異なり、はんだボール14を接触させる前に加熱溶融させ、溶融状態で配線ランド2に接触させることである。その結果、−25℃と125℃との間での1000回の温度サイクル試験(加速テスト)においても結合部にクラックは生じていない。   As described above, the feature of this embodiment is that, unlike the conventional example described above (see FIGS. 18 and 19), the solder ball 14 is heated and melted after contacting the wiring land 2. 14 is brought into contact with the wiring land 2 in a molten state by heating and melting before contacting. As a result, no cracks occurred in the joint even in 1000 temperature cycle tests (acceleration test) between −25 ° C. and 125 ° C.

図3は、本実施の形態における各工程の所要時間とはんだ温度の関係を示すグラフである。   FIG. 3 is a graph showing the relationship between the time required for each step and the solder temperature in the present embodiment.

即ち、はんだボール14は220℃に加熱され、溶融状態で基板1の配線ランド2に接触するので、接触後の昇温・溶融に要する時間が省かれている。そして接触後に溶融状態を2秒間保持させ、しかる後に加熱を止めて2秒間冷却することにより結合する。そして、約150℃に降温後吸着ヘッド8を離脱する。従って、この場合もはんだボール14を融点温度まで昇温に要する時間は必要であるが、非接触状態で空気中において昇温するので、接触後に昇温する従来に比べて接触後の工程が短時間ですみ、金属間の拡散現象が起こる時間を大幅に短縮することができる。   That is, since the solder ball 14 is heated to 220 ° C. and comes into contact with the wiring land 2 of the substrate 1 in a molten state, the time required for temperature rise and melting after the contact is saved. After the contact, the molten state is maintained for 2 seconds, and then the heating is stopped and the mixture is cooled for 2 seconds to bond. Then, after the temperature is lowered to about 150 ° C., the suction head 8 is detached. Therefore, in this case as well, it takes time to raise the temperature of the solder ball 14 to the melting point temperature. However, since the temperature is raised in the air in a non-contact state, the post-contact process is shorter than in the conventional case where the temperature is raised after contact. In time, the time for the diffusion phenomenon between metals can be greatly shortened.

その結果、図4(従来例における図21に対応)に示すように、チップ電極11上のCuスタッドバンプ12と、配線ランド2を構成しているCu層5及びNi層6、Au層7との間における金属拡散が抑制され、図示の如く、合金層15を従来(図21)に比べて薄く形成させることができる。   As a result, as shown in FIG. 4 (corresponding to FIG. 21 in the conventional example), the Cu stud bump 12 on the chip electrode 11, the Cu layer 5 and the Ni layer 6 and the Au layer 7 constituting the wiring land 2 As shown in the figure, the alloy layer 15 can be formed thinner than in the prior art (FIG. 21).

図5は、上述したICチップ10の個片化後の単体を誇張した拡大図を示すものである。即ち、上記したICチップ10の実装前における形状を明示したものであり、このように、チップ電極11上にCuからなるスタッドバンプ12が突設され、このスタッドバンプ12の先端部にはんだボール14が形成される。但し、このスタッドバンプはなくてもよい。   FIG. 5 shows an enlarged view exaggerating a single unit after the above-described IC chip 10 is separated. That is, the shape of the IC chip 10 before mounting is clearly shown. Thus, the stud bump 12 made of Cu protrudes from the chip electrode 11, and the solder ball 14 is formed at the tip of the stud bump 12. Is formed. However, this stud bump may not be present.

また、図6は、吸着ヘッド8の構造の詳細図を示す。即ち、セラミックスからなる吸着ヘッド8の本体は下部8aと上部8bとで構成され、上部8bは中空部18を有し、下部8aは複数(この図では簡略図示する。)の吸気孔13が形成されている。そして、簡略図示した上部8bが図示省略した吸引機構によって真空引きされることにより、ICチップ10が吸着ヘッド8に吸着される。   FIG. 6 shows a detailed view of the structure of the suction head 8. That is, the main body of the suction head 8 made of ceramic is composed of a lower part 8a and an upper part 8b, the upper part 8b has a hollow part 18, and the lower part 8a is formed with a plurality of intake holes 13 (illustrated in this figure). Has been. The IC chip 10 is sucked by the suction head 8 by evacuating the upper portion 8b shown in a simplified manner by a suction mechanism (not shown).

そして、上部8bの壁部内を経由した配線により、下部8a内にヒーター9が形成され、このヒーター9の熱がヘッド8に吸着把持されているICチップに伝わってはんだボール14を加熱する。このヒーター9により吸着ヘッド8を400℃まで昇温可能であり、セラミックスは蓄熱作用があるため、はんだボール14に対して良好な加熱を行うことができる。また、吸着しているICチップ10上のはんだボール14の温度は、吸着ヘッド8の温度よりも約30℃低いため、この温度差を目安にはんだボール14を所望の温度に加熱できる。   Then, a heater 9 is formed in the lower portion 8 a by wiring passing through the wall portion of the upper portion 8 b, and the heat of the heater 9 is transmitted to the IC chip adsorbed and held by the head 8 to heat the solder balls 14. The heater 9 can raise the temperature of the suction head 8 to 400 ° C., and the ceramic has a heat storage function, so that the solder ball 14 can be heated satisfactorily. Moreover, since the temperature of the solder ball 14 on the IC chip 10 being sucked is lower by about 30 ° C. than the temperature of the suction head 8, the solder ball 14 can be heated to a desired temperature by using this temperature difference as a guide.

本実施の形態によれば、吸着ヘッド8によってはんだボール14を加熱し、はんだボール14が配線ランド2に接触する前にはんだボール14を溶融させ、はんだボール14が溶融状態で接触させるので、次のような顕著な効果を発揮することができる。
1.リフロー炉を用いなくてよいので、基板1の反りが発生しない。
2.接合時に加圧しないで接合が可能となり、ICチップ10にダメージを与えない。
3.はんだボール14及び配線ランド2の高さのばらつきを吸収して、均一に接合でき る。
4.接合の所要時間を短縮できることにより、接合部の合金の生成を抑えることができ る。その結果、基板側に伝わる熱が小さいため、基板1を反らせることがない。
According to the present embodiment, the solder ball 14 is heated by the suction head 8, the solder ball 14 is melted before the solder ball 14 contacts the wiring land 2, and the solder ball 14 is contacted in the molten state. Such a remarkable effect can be exhibited.
1. Since it is not necessary to use a reflow furnace, the substrate 1 is not warped.
2. Bonding is possible without applying pressure during bonding, and the IC chip 10 is not damaged.
3. The variation in the heights of the solder balls 14 and the wiring lands 2 can be absorbed and uniform bonding can be achieved.
4). By shortening the time required for joining, it is possible to suppress the formation of alloys at the joint. As a result, since the heat transmitted to the substrate side is small, the substrate 1 is not warped.

実施の形態2
図7は、本実施の形態による各工程の所要時間とはんだ温度の関係を示すグラフであり、上記した実施の形態1におけるグラフ(図3)に対応する図である。
Embodiment 2
FIG. 7 is a graph showing the relationship between the time required for each step and the solder temperature according to the present embodiment, and corresponds to the graph (FIG. 3) in the first embodiment described above.

本実施の形態は、はんだボール14を配線ランド2に接触させる時のはんだボール14の温度が異なるのみで、その他は実施の形態1と同様であるので、プロセス図等は省略し、図1又は図2の一部を用いて説明する。   This embodiment is the same as the first embodiment except that the temperature of the solder ball 14 when the solder ball 14 is brought into contact with the wiring land 2 is the same as that of the first embodiment. This will be described with reference to a part of FIG.

即ち、図1(d)の工程において、実施の形態1は、はんだボール14を220℃に加熱させて溶融状態にしているが、本実施の形態の場合は、はんだボール14を軟化点の150℃に加熱して軟化させ、この軟化状態で図2(e)のようにはんだボール14を配線ランド2に接触させる。そして、この接触後に220℃に昇温してはんだボール14を溶融させ、これ以後は実施の形態1と同様に、2秒間の溶融保持時間後に、加熱を止めて2秒間冷却し、約150℃に降温させて吸着ヘッド8を離脱させる。この場合も、吸着ヘッド8は未冷却状態であるので、次に把持するICチップのはんだボールを早く軟化させることができる。   That is, in the process of FIG. 1D, in the first embodiment, the solder ball 14 is heated to 220 ° C. to be in a molten state, but in the present embodiment, the solder ball 14 has a softening point of 150. It softens by heating to ° C., and in this softened state, the solder balls 14 are brought into contact with the wiring lands 2 as shown in FIG. Then, after this contact, the temperature is raised to 220 ° C. to melt the solder ball 14, and thereafter, after the melting and holding time of 2 seconds, the heating is stopped and the cooling is performed for 2 seconds as in the first embodiment. Then, the suction head 8 is detached. Also in this case, since the suction head 8 is in an uncooled state, the solder ball of the IC chip to be gripped next can be softened quickly.

従って、本実施の形態によれば、はんだボール14を予め軟化点の温度に加熱した後に配線ランド2に接触させ、それからはんだを融点温度に昇温させるので、この昇温に要する時間を短縮することができるため、従来例(図20)に比べて接合の所要時間を短縮できることにより、実施の形態1とほぼ同様に顕著な効果を発揮することができると共に、軟化しているのみであるのではんだ14が垂れ落ちる心配がなく、隣接のはんだボール14同士が接触して結合し合うこともないため、ハンドリングが容易であり、はんだの酸化防止のための窒素雰囲気を要しない等のメリットがある。   Therefore, according to the present embodiment, the solder ball 14 is heated in advance to the temperature of the softening point, and then brought into contact with the wiring land 2, and then the solder is heated to the melting point temperature. Therefore, since the time required for joining can be shortened as compared with the conventional example (FIG. 20), a remarkable effect can be exhibited in substantially the same manner as in the first embodiment, and only the softening is achieved. There is no fear that the solder 14 will sag, the adjacent solder balls 14 do not come into contact with each other, and therefore, handling is easy, and there is an advantage that a nitrogen atmosphere is not required for preventing oxidation of the solder. .

以下、上記した各実施の形態の変形例を説明する。   Hereinafter, modifications of the above-described embodiments will be described.

図8は、配線ランド2に接触させたはんだボール14を、より良好なフィレット形に形成する方法を示す変形例である。   FIG. 8 is a modification showing a method of forming the solder balls 14 brought into contact with the wiring lands 2 into a better fillet shape.

図8(a)(図2(e)に対応)は、溶融状態のはんだボール14を配線ランド2に接触させた後、矢印で示すように吸着ヘッド8を僅かに上方へ引き上げることにより、図8(b)に示すように、溶融状態のはんだ14が追随して変形し、下部が良好に広がったフィレット形に形成することができる。   FIG. 8 (a) (corresponding to FIG. 2 (e)) is obtained by bringing the molten solder ball 14 into contact with the wiring land 2 and then lifting the suction head 8 slightly upward as indicated by the arrow. As shown in FIG. 8B, the solder 14 in a molten state follows and deforms, and can be formed into a fillet shape in which the lower part is well spread.

また、図9及び図10は、はんだボール14の配線ランド2への接触を検知する方法の変形例である。   9 and 10 show a modification of the method for detecting the contact of the solder ball 14 to the wiring land 2.

既述した実施の形態における検知にはカメラを用いているが、図9に示すようにセンサー手段を用いて検知してもよい。   Although a camera is used for detection in the above-described embodiment, detection may be performed using sensor means as shown in FIG.

図9は、例えば個片化する前のウェーハ状態における電子部品25を示し、その一方の端縁に接触センサー17を固定設置した図である。この接触センサー17の先端はCuスタッドバンプ12よりは突出し、はんだボール14の高さよりは低い位置になっている。実装後のセンサー17は残しておいてもよい。   FIG. 9 shows the electronic component 25 in a wafer state before, for example, separation into individual pieces, and is a view in which the contact sensor 17 is fixedly installed on one edge thereof. The tip of the contact sensor 17 protrudes from the Cu stud bump 12 and is at a position lower than the height of the solder ball 14. The sensor 17 after mounting may be left.

図10(a)は、吸着ヘッド8に把持された状態の図9の一部分(センサー側)の拡大図を示し、基板1に実装している状態である。従って、吸着ヘッド8を下降させることにより、図10(b)に示すように、はんだボール14がUF樹脂4をはじきながら配線ランド2に接触すると共に、接触センサー17の先端が配線ランド2に接触することにより、電子部品25と基板1との接触位置を決めることができる。   FIG. 10A shows an enlarged view of a part (sensor side) of FIG. 9 held by the suction head 8 and is mounted on the substrate 1. Accordingly, by lowering the suction head 8, the solder ball 14 contacts the wiring land 2 while repelling the UF resin 4 as shown in FIG. 10B, and the tip of the contact sensor 17 contacts the wiring land 2. By doing so, the contact position of the electronic component 25 and the board | substrate 1 can be determined.

図11及び図12は、上記した実施の形態1におけるUF樹脂4の代りに、熱硬化性の樹脂(例えばエポキシ樹脂)を用いた変形例を示す。従って、この樹脂以外は実施の形態1とほぼ同様であるので、実施の形態1と基本的に同様のプロセスの図11及び図12(図1及び図2に対応)により説明する。   FIG. 11 and FIG. 12 show a modification using a thermosetting resin (for example, epoxy resin) instead of the UF resin 4 in the first embodiment. Therefore, since this resin is substantially the same as that of the first embodiment, the process basically similar to that of the first embodiment will be described with reference to FIGS. 11 and 12 (corresponding to FIGS. 1 and 2).

即ち、まず図11(a)に示すように、実施の形態1と同様に、基板1表面の配線2A上に絶縁膜3をパターン印刷によって部分的に配し、被覆することにより、被覆のないランド2を形成し、次に、図11(b)に示すように、配線ランド2と2との間に熱硬化性樹脂19を滴下する。   That is, as shown in FIG. 11 (a), as in the first embodiment, the insulating film 3 is partially arranged by pattern printing on the wiring 2A on the surface of the substrate 1 and covered so that there is no covering. The land 2 is formed, and then a thermosetting resin 19 is dropped between the wiring lands 2 and 2 as shown in FIG.

次に、図11(c)に示すように、実施の形態1と同様にICチップ10の電極11にCuスタッドバンプ12を設けてこの上にはんだボール14を形成し、このICチップ10をヒーター9によって加熱された吸着ヘッド8で把持してはんだボールを80℃に加熱し、この状態のICチップ10を基板1の上方に配置する。   Next, as shown in FIG. 11C, similarly to the first embodiment, Cu stud bumps 12 are provided on the electrodes 11 of the IC chip 10 and solder balls 14 are formed thereon, and this IC chip 10 is heated. The solder ball is heated to 80 ° C. with the suction head 8 heated by 9, and the IC chip 10 in this state is placed above the substrate 1.

次に、図11(d)に示すように、はんだボール14が配線ランド2に接触する前に、吸着ヘッド8に内設のヒーター9でヘッド8を220℃〜250℃に昇温してはんだボール14を加熱し、スタッドバンプ12上のはんだボール14を溶融する。この場合も、溶融したはんだの酸化を防止するために、窒素雰囲気中での接合が望ましい。   Next, as shown in FIG. 11 (d), before the solder balls 14 come into contact with the wiring lands 2, the head 8 is heated to 220 ° C. to 250 ° C. by the heater 9 provided in the suction head 8 and soldered. The balls 14 are heated to melt the solder balls 14 on the stud bumps 12. In this case as well, joining in a nitrogen atmosphere is desirable to prevent oxidation of the molten solder.

次に、図12(e)に示すように、はんだボール14が溶融状態のICチップを下降させて基板1に接触させる。これにより、溶融状態のはんだボール14を、加圧なしで基板1の配線ランド2に接触させることができる。従って、樹脂19がICチップ10と基板1との間に充満されながら加熱されて硬化し、固定材として機能する。この場合もはんだボール14及び基板1の配線ランド2の高さばらつきを考慮し、ばらつき範囲以上にICチップ10を下降させることが重要である。   Next, as shown in FIG. 12 (e), the IC chip in which the solder balls 14 are melted is lowered and brought into contact with the substrate 1. As a result, the molten solder balls 14 can be brought into contact with the wiring lands 2 of the substrate 1 without applying pressure. Accordingly, the resin 19 is heated and cured while being filled between the IC chip 10 and the substrate 1 and functions as a fixing material. Also in this case, it is important to lower the IC chip 10 beyond the variation range in consideration of the height variation of the solder ball 14 and the wiring land 2 of the substrate 1.

次に、図12(f)に示すように、上記の接触後、実施の形態1と同様に、はんだ14の溶融状態を例えば2秒間保持する。   Next, as shown in FIG. 12F, after the above contact, the molten state of the solder 14 is held, for example, for 2 seconds as in the first embodiment.

次に、図12(g)に示すように、吸着ヘッド8によるはんだ14の加熱を止め、例えば冷風を吹きつけてはんだ14を冷却することにより、結合することができる。そして、約150℃に冷却後、図12(h)に示すように、吸着ヘッドを離脱し、実装を完了する。   Next, as shown in FIG. 12G, the heating can be performed by stopping the heating of the solder 14 by the suction head 8 and cooling the solder 14 by blowing cold air, for example. Then, after cooling to about 150 ° C., the suction head is detached as shown in FIG.

この場合、加熱ステージ(図示省略)上に基板1を載置し、加熱ステージによる加熱と吸着ヘッド8からの加熱とを併用することにより、ICチップ10と基板1との固定力を一層高めることができる。この場合、エポキシ樹脂19は熱容量が大きく、しかも短時間の加熱であるので問題ない。   In this case, the fixing force between the IC chip 10 and the substrate 1 is further increased by placing the substrate 1 on a heating stage (not shown) and using the heating by the heating stage and the heating from the suction head 8 together. Can do. In this case, there is no problem because the epoxy resin 19 has a large heat capacity and is heated for a short time.

図13及び図14は、上記した実施の形態1や変形例がICチップ10の電極11側にはんだボール14を設けたのとは異なり、はんだボール14を基板1の配線ランド2側に配し、UF樹脂4等は実装後に設ける点が異なる変形例を示す。従って、この場合も異なる点以外は実施の形態1とほぼ同様であるので、実施の形態1と基本的に同様のプロセスの図13及び図14(図1及び図2に対応)により説明する。   13 and 14 are different from the first embodiment and the modified example in which the solder ball 14 is provided on the electrode 11 side of the IC chip 10, and the solder ball 14 is arranged on the wiring land 2 side of the substrate 1. The UF resin 4 and the like are modified examples in that they are provided after mounting. Accordingly, in this case as well, except for the differences, this embodiment is substantially the same as the first embodiment, and will be described with reference to FIGS. 13 and 14 (corresponding to FIGS. 1 and 2) which are basically the same as the first embodiment.

即ち、まず図13(a)に示すように、実施の形態1と同様に、基板1表面の配線2A上に絶縁膜3をパターン印刷によって配し、部分的に被覆することにより、被覆のないランド2を形成し、次に図13(b)に示すように、配線ランド2上にはんだボール14を形成する。この場合、基板1は加熱ステージ30上に配置されている。   That is, as shown in FIG. 13 (a), similarly to the first embodiment, the insulating film 3 is arranged on the wiring 2A on the surface of the substrate 1 by pattern printing and partially covered, so that there is no covering. The land 2 is formed, and then solder balls 14 are formed on the wiring land 2 as shown in FIG. In this case, the substrate 1 is disposed on the heating stage 30.

次に、図13(c)に示すように、実装するICチップ10の電極11にCuスタッドバンプ12を設ける。そして、このICチップ10を吸着ヘッド8で把持して基板1の上方に配置する。   Next, as shown in FIG. 13C, Cu stud bumps 12 are provided on the electrodes 11 of the IC chip 10 to be mounted. Then, the IC chip 10 is held by the suction head 8 and disposed above the substrate 1.

次に、図13(d)に示すように、加熱ステージ30を230℃〜240℃に数秒間昇温することによって基板1を加熱し、この基板1の熱が配線ランド2上のはんだボール14を融点温度に加熱し、溶融する。   Next, as shown in FIG. 13D, the substrate 1 is heated by raising the temperature of the heating stage 30 to 230 ° C. to 240 ° C. for several seconds, and the heat of the substrate 1 is applied to the solder balls 14 on the wiring lands 2. Is heated to the melting temperature and melted.

次に、図14(e)に示すように、ICチップを下降させて基板1に接触させる。従って、溶融状態のはんだボール14内にICチップ10のスタッドバンプ12が没入し、加圧なしで基板1の配線ランド2に接触させることができる。   Next, as shown in FIG. 14E, the IC chip is lowered and brought into contact with the substrate 1. Accordingly, the stud bumps 12 of the IC chip 10 are immersed in the molten solder balls 14 and can be brought into contact with the wiring lands 2 of the substrate 1 without applying pressure.

次に、図14(f)に示すように、上記の接触後、はんだ14の溶融状態を例えば2秒間保持する。   Next, as shown in FIG. 14F, after the above contact, the molten state of the solder 14 is held for 2 seconds, for example.

次に、図14(g)に示すように、加熱ステージ30によるはんだ14の加熱を止め、例えば冷風を吹き付けてはんだ14を冷却することにより、電極11と配線ランド2とを結合することができる。そして、約150℃に冷却後、図14(h)に示すように、吸着ヘッドを離脱し、実装を完了する。従って、リフローしないため基板1が反ることがない。この場合、接合後にICチップ10と基板1との間にUF樹脂を注入してもよい。   Next, as shown in FIG. 14G, the heating of the solder 14 by the heating stage 30 is stopped, and the solder 11 is cooled by blowing, for example, cold air, so that the electrode 11 and the wiring land 2 can be coupled. . Then, after cooling to about 150 ° C., the suction head is detached as shown in FIG. Therefore, the substrate 1 does not warp because it does not reflow. In this case, UF resin may be injected between the IC chip 10 and the substrate 1 after bonding.

図15は、更に他の変形例を示すものであり、このようにICチップ10は個片化する前に、ウェーハ20レベルで実装することも可能である。この図において、ウェーハ20は斜視図、基板1は断面図で示した。そして矢印方向にウェーハ20をマウントする。   FIG. 15 shows still another modified example. Thus, the IC chip 10 can be mounted at the wafer 20 level before being separated into individual pieces. In this figure, the wafer 20 is shown in a perspective view, and the substrate 1 is shown in a sectional view. Then, the wafer 20 is mounted in the direction of the arrow.

図16(a)は、実装後の基板1及びウェーハ20の概略断面図を示す。そして、この場合もウェーハ20上に配されている各チップ領域の電極11上には、既述した実施の形態1等と同様に、スタッドバンプ(図示省略)が設けられ、このスタッドバンプ上にはんだボールを形成する。そして、このはんだボールを予め加熱溶融した後に、溶融保持時間、冷却および固化工程を経て基板1の配線ランド2に接合する。即ち、実施の形態1と同様のプロセスで行ってよい。また、実施の形態2と同様に、はんだボールは軟化点温度で軟化した後に実施の形態2と同様のプロセスで実装することもできる。   FIG. 16A is a schematic cross-sectional view of the substrate 1 and the wafer 20 after mounting. In this case as well, stud bumps (not shown) are provided on the electrodes 11 of the respective chip regions arranged on the wafer 20 as in the first embodiment described above. Form solder balls. Then, after the solder balls are heated and melted in advance, the solder balls are bonded to the wiring lands 2 of the substrate 1 through a melting and holding time, a cooling and a solidifying process. That is, the same process as in the first embodiment may be performed. Similarly to the second embodiment, the solder ball can be mounted by the same process as the second embodiment after being softened at the softening point temperature.

図16(a)において、基板1は反った形状に誇張したものであるが、このように反りがあり、基板1とウェーハ20との間の距離が均一でない場合でも、上記した実施の形態1又は2の実装方法を適用することにより、図示の如く、はんだ14によって良好な接合を行うことができる。   In FIG. 16A, the substrate 1 is exaggerated in a warped shape. However, even when the substrate 1 is warped and the distance between the substrate 1 and the wafer 20 is not uniform, the first embodiment described above is used. Alternatively, by applying the mounting method 2, good bonding can be performed with the solder 14 as illustrated.

このようにウェーハ20レベルで実装した場合は、図16(b)に示すように、実装後に個片化することもできる。即ち、同図はウェーハ20をチップ単位に切断線20の位置をカッター23で切断し、例えば1チップ又は2チップを単位として個片化し、MCMを構成することもできる。   Thus, when mounted on the wafer 20 level, as shown in FIG. 16B, it can be separated into pieces after mounting. In other words, in the figure, the position of the cutting line 20 is cut by the cutter 23 in units of chips of the wafer 20, and for example, the MCM can be configured by dividing into pieces in units of one chip or two chips.

上記した各実施の形態等は、本発明の技術的思想に基づいて種々に変形することができる。   Each of the above-described embodiments and the like can be variously modified based on the technical idea of the present invention.

例えば、実施の形態1又は2と各変形例とを組み合せることも可能であり、実施の形態1又は2のプロセス及び条件等は適宜に変更することも可能であり、このことは変形例同士についても同様である。   For example, Embodiment 1 or 2 can be combined with each modification, and the process and conditions of Embodiment 1 or 2 can be changed as appropriate. The same applies to.

また、各実施の形態及び各変形例は、ICチップを実装の対象として説明したが、ICチップ以外の電子部品その他の部品の実装に適用してもよい。   Moreover, although each embodiment and each modification demonstrated the IC chip as the object of mounting, you may apply to mounting of electronic components other than IC chip other components.

また、はんだボール14を加熱溶融する手段は、上記した吸着ヘッド8や加熱ステージ30に限らず、例えばトーチによる加熱や熱風等適宜であってもよい。   The means for heating and melting the solder balls 14 is not limited to the suction head 8 and the heating stage 30 described above, and may be appropriate, for example, heating with a torch or hot air.

本実施の形態1よる実装プロセスを示す概略図である。It is the schematic which shows the mounting process by this Embodiment 1. FIG. 同、実装プロセスを示す概略図である。It is the schematic which shows a mounting process same as the above. 同、実施の形態1における接合時間とはんだ温度を示すグラフである。4 is a graph showing the joining time and solder temperature in the first embodiment. 同、実施の形態における金属間拡散状態を示す概略図である。It is the schematic which shows the diffusion state between metals in embodiment similarly. ICチップの概略拡大図である。It is a schematic enlarged view of an IC chip. 本発明の実施の形態2における接合時間とはんだ温度を示すグラフである。It is a graph which shows the joining time and solder temperature in Embodiment 2 of this invention. 変形例を示す概略図である。It is the schematic which shows a modification. 変形例を示す概略図である。It is the schematic which shows a modification. 変形例を示す概略図である。It is the schematic which shows a modification. 変形例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a modification. 変形例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a modification. 変形例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a modification. 変形例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a modification. 変形例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a modification. 変形例を示す概略図である。It is the schematic which shows a modification. 変形例を示す概略図である。It is the schematic which shows a modification. 従来例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a prior art example. 従来例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a prior art example. 従来例による実装プロセスを示す概略図である。It is the schematic which shows the mounting process by a prior art example. 従来例における接合時間とはんだ温度を示すグラフである。It is a graph which shows the joining time and solder temperature in a prior art example. 従来例における金属間拡散状態を示す概略図である。It is the schematic which shows the diffusion state between metals in a prior art example.

符号の説明Explanation of symbols

1…基板、2…配線ランド、2A…配線、3…絶縁膜、
4…UF(アンダーフィル)樹脂、5…Cu層、6…Ni層、7…Au層、
8…吸着ヘッド、8a…下部、8b…上部、9…ヒーター、10…ICチップ、
11…電極、12…スタッドバンプ、13…吸気孔、14…はんだボール又ははんだ、
15…合金層、17…センサー、18…中空部、19…樹脂、20…ウェーハ、
22…切断線、23…カッター、25…電子部品、30…加熱ステージ
DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Wiring land, 2A ... Wiring, 3 ... Insulating film,
4 ... UF (underfill) resin, 5 ... Cu layer, 6 ... Ni layer, 7 ... Au layer,
8 ... Adsorption head, 8a ... Lower part, 8b ... Upper part, 9 ... Heater, 10 ... IC chip,
DESCRIPTION OF SYMBOLS 11 ... Electrode, 12 ... Stud bump, 13 ... Intake hole, 14 ... Solder ball or solder,
15 ... alloy layer, 17 ... sensor, 18 ... hollow part, 19 ... resin, 20 ... wafer,
22 ... cutting line, 23 ... cutter, 25 ... electronic component, 30 ... heating stage

Claims (12)

電子部品と実装基板とを互いに接触させない非接触状態で、導電性の低融点接合材を 前記電子部品及び前記実装基板のいずれかに配して前記低融点接合材を軟化点以上の温 度に加熱する工程と、
前記加熱温度下で前記電子部品と前記実装基板とを互いに接触させる工程と、
この接触後に前記低融点接合材を溶融状態に保持する工程と、
前記溶融状態から降温して前記低融点接合材を固化させる工程と
を有する、実装方法。
In a non-contact state where the electronic component and the mounting substrate are not in contact with each other, a conductive low melting point bonding material is disposed on either the electronic component or the mounting substrate so that the low melting point bonding material is at a temperature equal to or higher than the softening point. Heating, and
Bringing the electronic component and the mounting substrate into contact with each other under the heating temperature;
Holding the low melting point bonding material in a molten state after this contact;
And a step of cooling the molten state to solidify the low-melting-point bonding material.
前記非接触状態で前記低融点接合材を加熱して溶融させ、この溶融状態のまま、前記電子部品と前記実装基板とを互いに接触させる、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein the low-melting-point bonding material is heated and melted in the non-contact state, and the electronic component and the mounting substrate are brought into contact with each other in the molten state. 前記非接触状態で前記低融点接合材を加熱して軟化させ、この軟化状態のまま、前記電子部品と前記実装基板とを互いに接触させる、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein the low-melting-point bonding material is heated and softened in the non-contact state, and the electronic component and the mounting substrate are brought into contact with each other in the softened state. 前記電子部品の電極上に前記低融点接合材を被覆してバンプを形成し、このバンプの少なくとも最上層を前記軟化点以上に加熱した後に、前記バンプを前記実装基板の配線ランドに接触させる、請求項1に記載した実装方法。   A bump is formed by covering the low melting point bonding material on the electrode of the electronic component, and after heating at least the uppermost layer of the bump to the softening point or higher, the bump is brought into contact with a wiring land of the mounting substrate. The mounting method according to claim 1. 前記電子部品を保持具に保持し、この保持具から前記軟化点以上の加熱を行う、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein the electronic component is held by a holder, and heating is performed at or above the softening point from the holder. 前記低融点接合材を前記固化させた後に、前記電子部品を保持している前記保持具を前記電子部品から離脱させる、請求項5に記載した実装方法。   The mounting method according to claim 5, wherein after the low-melting-point bonding material is solidified, the holder that holds the electronic component is detached from the electronic component. 前記実装基板上にアンダーフィル材を予め付着させておき、前記低融点接合材を配した前記電子部品を前記実装基板に接触させる、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein an underfill material is attached in advance on the mounting substrate, and the electronic component on which the low melting point bonding material is disposed is brought into contact with the mounting substrate. 前記軟化点以上の加熱を前記実装基板から行う、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein heating at or above the softening point is performed from the mounting substrate. 前記電子部品としてチップ状電子部品を用いる、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein a chip-shaped electronic component is used as the electronic component. チップ状電子部品に個片化されるべきウェーハを前記電子部品として用い、前記低融点接合材の前記固化後に前記ウェーハをチップ状電子部品に個片化する、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein a wafer to be separated into chip-shaped electronic components is used as the electronic component, and the wafer is separated into chip-shaped electronic components after the solidification of the low melting point bonding material. 前記電子部品と前記実装基板との少なくとも一方に、これらの前記接触を検知するセンサー手段を設ける、請求項1に記載した実装方法。   The mounting method according to claim 1, wherein at least one of the electronic component and the mounting substrate is provided with sensor means for detecting the contact. 前記電子部品に前記センサー手段を突出して設け、このセンサー手段が前記実装基板に接触したことを検知して、前記電子部品と前記実装基板との前記接触時の位置を決める、請求項11に記載した実装方法。   12. The sensor means is provided so as to protrude from the electronic component, and the position at the time of the contact between the electronic component and the mounting board is determined by detecting that the sensor means has contacted the mounting board. Implementation method.
JP2004068483A 2004-03-11 2004-03-11 Mounting method Pending JP2005259925A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009124047A (en) * 2007-11-16 2009-06-04 Renesas Technology Corp Apparatus and method for manufacturing semiconductor device
JP2013539921A (en) * 2010-10-14 2013-10-28 ストラ エンソ オーワイジェイ Method and apparatus for attaching a chip to a printed conductive surface

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009124047A (en) * 2007-11-16 2009-06-04 Renesas Technology Corp Apparatus and method for manufacturing semiconductor device
JP2013539921A (en) * 2010-10-14 2013-10-28 ストラ エンソ オーワイジェイ Method and apparatus for attaching a chip to a printed conductive surface
US9629255B2 (en) 2010-10-14 2017-04-18 Stora Enso Oyj Method and arrangement for attaching a chip to a printed conductive surface
KR20170130614A (en) * 2010-10-14 2017-11-28 스토라 엔소 오와이제이 Method and arrangement for attaching a chip to a printed conductive surface
KR101941679B1 (en) * 2010-10-14 2019-01-24 스토라 엔소 오와이제이 Method and arrangement for attaching a chip to a printed conductive surface
USRE48018E1 (en) 2010-10-14 2020-05-26 Stora Enso Oyj Method and arrangement for attaching a chip to a printed conductive surface

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