JPH07226094A - Information holding circuit - Google Patents

Abstract

PURPOSE:To unnecessitate battery for backup and to hold information before occurence of power interruption until the power is recovered, by using an EEPROM as a memory element for holding information even when power interrupts occurs at standby time. CONSTITUTION:An EEPROM 1 is used as the memory element, held information is stored in the leading address (0 address). A driver circuit 2 supplies a control signal to the EEPROM 1, a buffer circuit 3 receives data to be set from a CPU and supplies it to the EEPROM 1, while held information outputted from the EEPROM 1 is temporarily stored. When power interruption occurs, a whole circuit becomes invalid, but a power supply is recovered to a standby state after power is sent again. Contents of address 0 is outputted from a data port again. Since information written in the address 0 once is not lost even if a power supply is interrupted, information before power interruption can be outputted again by specifying this address 0 at the time of recovering of power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information holding circuit.

[0002]

2. Description of the Related Art Normal electronic equipment has three power states. That is, the power-off state in which all the circuits are powered off, the standby state in which only some circuits are supplied with the standby sub-power and the other circuits are not supplied with power, and all circuits including the CPU. Power is on There is a power on state.

Of these, the standby state is set to prevent the information accumulated in a predetermined circuit when the power is off from being lost when the power is off, and the standby power is supplied only to the circuits that need to retain information. However, even if the power supply used for the normal operation is turned off, the standby power is supplied only to this circuit, so that the operation is secured and the information can be retained.

Conventionally, a D-type flip-flop has been generally used as a memory element used as an information holding circuit in this kind of standby state. Information of "1" or "0" is set in this D-type flip-flop, and standby power is supplied to hold this information. Standby power is constantly supplied to the D-type flip-flop, and when the power is turned on, the CPU inputs data and a data set signal to the D-type flip-flop to set the data. Retention information is retrieved from the output. The data once set is retained without being lost even if the main power is cut off as long as the standby power is supplied.

[0005]

However, in the conventional information holding circuit, since the standby power supply is required, when a power failure occurs, the standby power supply is turned off and the information held in the standby state is lost. There is a problem that it ends up. In order to prevent this, it is necessary to equip the battery as a standby power supply and back up the circuit. When the backup battery is installed, the device becomes large and the backup battery must be replaced over the life of the device.

[0006]

SUMMARY OF THE INVENTION The present invention provides an EEPROM circuit to which standby power is supplied, and the EEPROM.
Address supply means for designating a predetermined address of the circuit irrespective of the interruption of the standby power supply, control signal fixing means for fixing the level of the control signal of the EEPROM circuit so as to be in the read mode in the normal operation, and the EEPROM.
The M circuit is provided with a driver circuit that supplies the level of the control signal required in the read mode and the write mode, and a data input unit that writes data to the predetermined address in the write mode.

[0007]

In the present invention, an EEPROM is used instead of the flip-flop circuit, which does not lose the stored contents even if the power supply is cut off once the information is stored electrically. The information to be held is stored at a predetermined address of this EEPROM, that is, usually at the head address (0 address).
Therefore, the address input is set so that the predetermined address designated for this purpose is always designated in the read mode. Normally, all address input terminals are connected to the ground via a predetermined resistor.

As a result, the start address 0 is always designated. Further, the control input terminal of this EEPROM has a structure in which the level of the control signal is fixed so as to be in the reading mode during the normal operation. Therefore, EEPRO
When the standby power supplied to M is cut off and the power is restored after a certain time, this EEPROM is in the read mode by the control signal fixing means, and the address supplying means always selects a predetermined address, that is, 0 address. The holding information previously written in the predetermined address is output.

[0009]

1 is a circuit diagram of an information holding circuit according to an embodiment of the present invention. In the present invention, the EEPROM 1 is used as a storage element for holding information. And this EEPROM1
The retained information is stored in the first address (address 0) of the. A standby power supply 5VS is supplied to the EEPROM 1. Further, a driver circuit 2 for supplying a control signal to the EEPROM 1 and a buffer circuit 3 for temporarily storing the hold information output from the EEPROM 1 are provided. The driver circuit 2 and the buffer circuit 3 are normally supplied with 5V.

Address terminals A _{0 to} A _{n of the} EEPROM ₁
Is pulled down to ground via a resistor 4. The chip enable signal CE (B), the output enable signal OE (C), and the write enable signal WE (D) from the CPU (not shown) to the EEPROM 1 are input to the driver circuit 2 and their inverted output bars CE, O are output.
E and bar WE are the corresponding input terminals F, G and H of the EEPROM.
Are configured to be input respectively. Further, the chip enable signal bar CE terminal F and the output enable signal bar OE terminal G are pulled down to the ground via the resistors 5 and 6, and the write enable signal bar WE
The terminal H is pulled up to the standby power supply 5VS via the resistor 7.

As a result, the EEPROM is in the read mode in the normal use state. The data output from the data port of the EEPROM 1 is supplied to other circuits as holding information I. Further, the CPU can read and write this held information I via the buffer circuit 3.

Next, the circuit operation of FIG. 1 will be described. First, a case where information to be held when the power is turned on is set in this circuit will be described. FIG. 2 shows a timing chart of the information set. First, address input terminals A0 to An
Since (A) is grounded via the pull-down resistor 4, it is always at a low level. Therefore, the address 0, which is usually the head address, is selected. Therefore, the information to be held is written in this address 0.

The chip enable bar CE terminal F and the output enable bar OE terminal G have resistors 5 and 6, respectively.
It is normally driven low as it is pulled to ground via. Further, the write enable bar WE terminal H is driven at a high level.
Therefore, the EEPROM is in the read mode, and the contents of address 0 are output.

Here, when shifting to the write cycle, the output enable bar OE terminal G is first set to a high level to stop the output of the held information from the data port. In this state, the data port is in a high impedance state. Next, the write enable bar WE terminal H is driven to a low level, the data to be set is input from the CPU to the data port via the buffer circuit 3, and the EEPROM 1
To enter. This information has the address 0 as described above.
Since it is fixed at the address, it is stored at address 0.

Information is set in the EEPROM 1 in this way, and when the write cycle is completed, the set data is output again from the data port of the EEPROM 1 as holding information I. How the information set in this way changes in the standby state will be described.

FIG. 3 is a timing chart showing a sequence when a power failure occurs from the standby state and the power is restored again to restore the standby state. In the standby state, the standby power supply voltage 5VS is supplied only to the EEPROM 1, and the voltage of the driver circuit 2 and the buffer circuit 3 is 0.
It becomes V. Further, since the chip enable bar CE terminal F, the output enable bar OE terminal G and the write enable bar WE terminal H have high impedance, the level of each signal is defined by the pull-down resistors 5 and 6 and the pull-up resistor. In this case, the EEPROM 1 is in the read mode and the contents at address 0 are output.

When a power failure occurs next time, the standby voltage 5VS also becomes 0V and all circuits are disabled. When the power failure is restored and the power is restored in this state, the power source returns to the standby state, and the content of the address 0 of the EEPROM 1 is output again from the data port. As described above, the information once written in the address 0 is not lost even when the power is cut off. Therefore, by designating this address 0 when the power is restored, the information before the power failure is output again.

[0018]

As described above in detail with reference to the embodiments, in the present invention, the non-volatile EEPROM is used to retrieve the information held in the standby state even after a power failure. No longer need. Further, even if a power failure occurs in the standby state, when the power is restored and returns to the standby state, the same state as before the power failure is restored, so that it is expected that the reliability of the device can be improved when the power failure occurs.

By using the information holding circuit of the present invention as a circuit for turning on the power by remote power supply control in response to an external request when the device is in the standby state, after the power is restored with the same setting as that set before the power failure. Since the power can be restored, the remote power control function can be configured to be effective even if a power failure occurs as long as the power is restored.

[Brief description of drawings]

FIG. 1 is an information holding circuit showing an embodiment of the present invention.

FIG. 2 is a timing chart explaining the state of the information set of the present invention.

FIG. 3 is a timing chart for explaining a state when power is restored after a power failure of the present invention.

[Explanation of symbols]

 1 EEPROM 2 driver circuit 3 buffer circuit 4, 5, 6 pull-down resistor 7 pull-up resistor bar CE chip enable signal bar OE output enable signal bar WE write enable signal

Claims (4)

[Claims] 1. An EEPRO to which standby power is supplied
M circuit, address supply means for designating a predetermined address of the EEPROM circuit irrespective of interruption of the standby power supply, and control signal fixing means for fixing the level of the control signal of the EEPROM circuit to a read mode during normal operation. Information characterized in that the EEPROM circuit is provided with a driver circuit for supplying a level of the control signal required in a read mode and a write mode, and a data input means for writing data to the predetermined address in the write mode. Holding circuit. 2. The address supply means is the EEPRO.
The information holding circuit according to claim 1, wherein the information holding circuit is configured to supply a ground potential to all the address terminals of the M circuit. 3. The predetermined address is the start address (address 0)
The information holding circuit according to claim 1, wherein 4. The control signal fixing means is the EEPRO.
2. The information holding circuit according to claim 1, wherein the potential of the chip enable terminal and the output enable terminal of the M circuit is fixed to the ground potential and the potential of the write enable terminal is fixed to the potential of the standby power supply.