JPH0150926B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data retention device, and more particularly to a data retention device that can reliably retain data even when power is cut off or when power is resupplied.

BACKGROUND ART In recent years, with the rapid development of electronic technology, there is a tendency for various devices to be computerized. For example, in an automobile, a microcomputer controls the ignition of the engine and controls various parts, and is also responsible for counting the cumulative distance. Since it is necessary to keep this accumulated distance count value even when the power switch is turned off, it is stored in the memory provided inside the microcomputer using the backup power supply when the power switch is turned off. However, if the battery as the main power source is removed, data is stored in nonvolatile memory using a backup power source that turns off after a certain period of time.

However, since non-volatile memory consumes a relatively large amount of current, if it is constantly connected to a backup power source, the generator will not be running when the power switch is turned off, so the car will not run for a relatively long period of time. If the battery is not used, the battery will continue to discharge, making it difficult to start the engine.

On the other hand, it is possible to eliminate power consumption when the power switch is turned off by storing data in non-volatile memory each time the power switch is turned off and then turning off the backup power supply, but non-volatile memory Such a configuration cannot be used because it has the problem that the retention time of stored data becomes shorter as the number of writes increases.

DISCLOSURE OF THE INVENTION Accordingly, an object of the present invention is to provide a data holding device that can significantly reduce power consumption when the power switch is turned off without affecting data holding operations.

In order to achieve this object, the present invention supplies power to the nonvolatile memory from the backup power supply only for a short period when the main power supply is turned off and on and when data is written and read.

By using such a configuration, it is possible to prevent the nonvolatile memory from consuming power when the power switch is turned off, and this has the excellent effect of preventing unnecessary discharge of the battery.

BEST MODE FOR CARRYING OUT THE INVENTION The figure is a circuit diagram showing an embodiment of a data holding device according to the present invention, and is particularly applied to calculating and displaying the distance traveled by a car. In the figure, 1 is a power supply circuit, which connects the output of battery 2 as a power source to the main power supply +B _M (+12V).
It is used as Then, the main power supply +B _M is supplied to the first regulator 4 via the key switch 3 as a power switch, and the switch output power supply +B _S (+
12V), the first regulator 3 outputs the drive power +B (+5V) via the backflow prevention diode 5. Also, a part of the main power supply +B _M is output as a +5V power supply via the second regulator 6, and is further smoothed in a relatively large capacity capacitor 7 to become a backup power supply +B.
Output as B _B. Reference numeral 8 denotes a microprocessor to which the drive power +B generated from the power supply circuit 1 is inputted as the power supply _VDD , and the backup power supply +B _B is inputted as the power supply _VCC . This microprocessor 8 is connected to an output port P ₁ that generates a read signal R, an output port P ₂ that generates a write signal W, an output port P ₃ to which an address bus AB is connected, and a data bus DB. Input/output port P ₄ , input port that receives reset signal RS
P ₅ , an input port P ₆ into which a data write command signal is input, and an input port P ₇ into which a data read command signal is input. A non-volatile memory 9 is connected to the microprocessor 8 via an address bus AB and a data bus DB, and stores data in response to a read signal R and a write signal W supplied from the microprocessor 8. and reading is performed.
10 is a power supply circuit for non-volatile memory, which inputs a signal obtained by dividing the main power supply +B _M of the power supply circuit 1 by resistors 11 and 12, and outputs only when the main power supply +B _M is equal to or higher than a set level. It has a buffer circuit 13 for generating. The output of this buffer circuit 13 is supplied via a resistor 15 to the base of a switching transistor 14 connected between the backup power supply + _BB and the power supply _VDD of the nonvolatile memory 9. 16 and 17 are resistors that divide the voltage of the main power supply +B _M , and 18 is a capacitor that is charged by this divided voltage output. Together with the resistor 16, they constitute an integrating circuit. 19
is an inverter that inverts the output of this integrating circuit,
A transistor 20 is connected between the base of the transistor 14 and the ground, and its base is connected to the output terminal of the inverter 19 via a resistor 21. 22 supplies a reset signal to the microprocessor 8 to put the microprocessor 8 into standby mode when the reset signal is an "L"signal;
This circuit releases standby mode when RS is an "H" signal. This standby mode release circuit 22 receives a signal obtained by dividing the voltage of the switch output power supply + _BS by resistors 23 and 24 as a positive terminal input, and a signal obtained by dividing the voltage of the backup power supply + _BS by resistors 25 and 26 as a negative terminal. A comparator 27 to be compared as an input, and a transistor whose collector is connected to the backup power supply +B _B via a resistor 28 and whose emitter is connected to ground, and whose base input is the output of the comparator 27 via a resistor 29. 30 and transistor 30
A transistor 32 is driven by connecting the input port P ₅ of the microprocessor 8 to ground by connecting the output of the microprocessor 8 to ground through a resistor 31 as a base input.
, a capacitor 33 connected between the collector of the transistor 32 and the ground, and a signal obtained by dividing the output of the nonvolatile memory power supply circuit 10 by resistors 34 and 35 as the base input, and a base input for the transistor 30. and a transistor 36 connected in parallel. 37 is a data write command circuit that generates a data write command signal, which takes the divided voltage output of the main power supply +B _M by resistors 38 and 39 as its positive input, and connects the resistor 40 and zener connected between the backup power supply +B _B and the ground. A comparator 42 whose negative input is the potential across the diode 41 as a constant voltage source.
and an integrating circuit consisting of a resistor 43 and a capacitor 44, which integrate the output of the comparator 42 to generate a data write command signal. Reference numeral 45 denotes a data read command circuit, which includes a series body of a resistor 46 and a capacitor 47 that integrate the backup power supply +B _B , a buffer circuit 48 that receives the integrated output as input, and outputs a data read command signal, and a buffer circuit 48 that outputs a data read command signal for the resistor 46. A diode 49 is connected in parallel to form a discharge path for the capacitor 47.

In the circuit configured as described above, under normal conditions, the battery 2 is connected to generate main power +B _M , and along with this, backup power +B _B is generated from the second regulator 6. . Furthermore, since the key switch 3 is closed, switch output power +B _S and drive power +B are generated. Therefore, the microprocessor 8 operates by using the drive power supply +B and the backup power supply + _B as the power supplies V _DD and V _CC (the signal is "H"), and the odometer pulse supplied for each unit travel is activated. The operation is to sequentially count and display the cumulative distance.

Next, when the key switch 3 is opened, the switch output power supply +B _S and the drive power supply +B generated from the first regulator 4 are turned off. As a result, the reset signal becomes "L" and the microprocessor 8 goes into standby mode, inputting the backup power supply +B _B supplied from the power supply circuit 1 as the power supply V _CC and setting the cumulative distance count value internally. continues to be held in memory. Then, when the key switch 3 is closed again, the driving power +B is generated again, so the microprocessor 8 continues reading out the stored value of the accumulated distance held in the memory, and outputs the mileage signal that is sequentially supplied from then on. Execute the operation of integrating and displaying. In this case, when the key switch 3 is turned on, the divided voltage output of the switch output power supply +B _S by the resistors 23 and 24 supplied to the positive terminal of the comparator 27 increases, so that the output of the comparator 27 becomes "H". As a result, transistor 30 is turned on.
When the transistor 30 is turned on, the transistor 32, which is turned on by the backup power supply + _B and supplies a reset signal to the input port _P5 of the microprocessor 8, is turned off and reset control for the microprocessor 8 is performed. (standby mode) is canceled.

Next, when the battery 2 is removed for some reason, the switch output power supply +B _S and the drive power supply +B are cut off if the main power supply +B _M and the key switch 3 are closed. here,
When the main power supply +B _M is turned off, the output of the buffer circuit 13 which receives the divided voltage output becomes "L", and the transistor 14 is accordingly turned on. In this case, the backup power supply + _B
The capacitor 7 provided on the output side of the regulator 6 allows the output to continue only for a period of time _t1 even if the main power supply +B _M is cut off. As a result, this backup power supply +B _B is supplied to the nonvolatile memory 9 and the microprocessor 8 as a power supply V _DD via the transistor 14 .

Here, when an output is generated from the nonvolatile memory power supply circuit 10, a part of it is supplied to the standby mode release circuit 22, and the transistor 36 is turned on. When transistor 36 is turned on, transistor 32 is turned off to stop generating the reset signal and release the standby mode for microprocessor 8. On the other hand, in the data write command circuit 37, the main power supply +
Since the buffer power supply +B _B decreases with a delay in the disconnection of B _M , the main power supply +B _M due to resistors 38 and 39
At the point when the voltage becomes lower than the constant voltage generated across the Zener diode 41, the output of the comparator 42 becomes "L". The output signal of the comparator 42 is supplied to the input port _P6 of the microprocessor 8 as a data write command signal via an integrating circuit including a resistor 43 and a capacitor 44. When the microprocessor 8 receives this data write command signal, it generates a write signal W from the output port P ₂ and also generates an address signal and integrated data from the output ports P ₃ and P ₄ to write the data into the nonvolatile memory 9. Write necessary data to and hold it. Here, backup power supply +B _B is main power supply +B _M
Since the power is turned off after a delay of t ₁ time, the power supply time to the nonvolatile memory 9 is also approximately a fraction of this t ₁ period.

Further, the time _t1 is set to the time required for the microprocessor 8 to write necessary data to the nonvolatile memory 9.

Next, when the battery 2 is connected, the main power supply +B _M is turned on, and along with this, the backup power supply +B _B becomes "H" after a delay of _t1 hour. On the other hand, the output of the integrating circuit made up of the resistor 16 and capacitor 18 is "L" within t ₂ hours (t ₁ < t ₂ ).
becomes. Therefore, the output of the inverter 19 which receives the output of the integrating circuit becomes "H" within time _t2 , and the transistor 20 is turned on. When the transistor 20 is turned on, the transistor 14 is also turned on, and the backup power supply + _B is connected to the nonvolatile memory 9 and the microprocessor 8.
Supplied as power +V _DD .

On the other hand, in the data read command circuit 45, an integrating circuit including a resistor 46 and a capacitor 47 integrates the backup power supply +B _B , and outputs the integrated output as a data read command signal B via a buffer circuit 48. In addition, the standby mode release circuit 22 uses the output of the nonvolatile memory power supply circuit 10 to operate the transistor 3 as in the case described above.
6 turns on, the reset release signal is set to "H" and the reset is released. The microprocessor 8 then uses its input port
When a data read command signal is supplied to _P7 , a read signal R is generated from the output port _P1 , and the data held in the nonvolatile memory 9 is read out and taken in, thereby continuing the mileage accumulation operation. Here, nonvolatile memory power supply circuit 1
0 output generation period, that is, the power consumption period of the nonvolatile memory 9, is only a short period (t ₂ - t ₁ ) from the generation of the backup power supply + _B to the start of output generation of the integrating circuit formed by the resistor 16 and capacitor 18. becomes. This (t ₂ −t ₁ ) time is the time required for the microprocessor 8 to read the necessary data from the nonvolatile memory 9. Therefore, during the off period of the key switch 3, the non-volatile memory 9
As a result, the battery 2 is prevented from discharging even when the vehicle is not running for a long period of time.
This makes it easier to start the engine.

Furthermore, in the above-mentioned embodiment, the case where it is used as a mileage meter of a car was explained, but the present invention is not limited to this, and can be applied to any circuit that requires data retention. This is something that can be done.

[Brief explanation of drawings]

The figure is a circuit diagram showing an embodiment of a data holding device according to the present invention. DESCRIPTION OF SYMBOLS 1... Power supply circuit, 2... Battery, 3... Key switch, 4, 6... First and second regulator, 8...
Microprocessor, 9...Nonvolatile memory, 1
0...Nonvolatile memory power supply circuit, 11, 12, 1
5, 16, 17, 21...Resistor, 13...Buffer circuit, 14,20...Transistor, 18...Capacitor, 19...Inverter, 22...Standby mode release circuit, 37...Data write command circuit, 4
5...Data reading command circuit.

Claims (1)

[Claims] 1 The battery output is used as a main power source, the main power source is taken out via a power switch as a switch output power source, the switch output power source is stabilized via a first regulator to output a drive power source, and the main power source is used as a second source source. A power supply circuit that stabilizes through a regulator and then smoothes it with a capacitor and outputs it as a backup power supply, a microprocessor that operates with the drive power and backup power generated from this power supply circuit, and a processing of this microprocessor. a nonvolatile memory that retains data when the main power is turned off; and a nonvolatile memory power supply that supplies the backup power to the microprocessor and the nonvolatile memory for a short time when the main power is turned off and when supply starts. By comparing the standby mode release circuit that releases the reset of the microprocessor for a short time when the main power supply is cut off and the nonvolatile memory power supply circuit generates an output, the main power supply and the backup power supply. a data write command circuit that detects disconnection of the main power supply and instructs the microprocessor to write and retain necessary data in the nonvolatile memory; and a data write command circuit that detects disconnection of the main power supply and instructs the microprocessor to write necessary data to the nonvolatile memory and store the data; A data holding circuit includes a data reading command circuit that instructs the microprocessor to read and import the data.