SU1083236A1 - Non-volatile storage - Google Patents

Abstract

STORAGE DEVICE WITH PRESERVATION OF INFORMATION DURING POWER DISTRIBUTION, containing a storage device, interface unit, threshold, separating, filtering and restricting elements, backup power source, the first input of the storage device is connected through the filtering element to the zero potential bus, through the restriction element to the backup source output power supply and one of the outputs of the separation element, the other output of which is connected to the input of the threshold element, the first input of the interface block and the power bus, The second input and output of the accumulator are connected respectively to the first output and the second input of the interface unit, the third input of which is addressable, the fourth input - informational, the fifth and sixth inputs - control inputs of the device, the second output of the interface unit characterized in that, in order to increase reliability, it contains an address register, an OR element, first and second AND elements, first and second pulse shapers, and a delay element, with the third output of the interface block connected the first input of the address register, the fourth output to the first input of the OR element, the fifth output to the second input of the OR element and the first input of the second AND element, the second input of which is connected to the first input of the first AND element and the output of the threshold element, the second input i of the first element And connected to the output of the OR element, the third input of which is soy (Linen is connected to the power bus, the output of the first element AND is connected to the first input of the first pulse generator, the output of which is connected to the second input of the address register and the first input of the deeper element The output of which is connected to the first input of the second pulse generator, the output of which is connected to the third input of the accumulator with the phone, the outputs of the address register and the second element And are connected respectively to the fourth and fifth inputs of the drive, the address input of the first and second elements And, the second inputs of the pulse form and delay element are connected to the first drive input.

Description

This invention relates to memory devices.

A storage device is known with preservation of information when the power is turned off, which contains a drive, a coupling unit, a main and backup power sources, a current stabilizer, separation elements, a group of galvanic isolation elements 1.

The disadvantage of this device is the possibility of destroying the information recorded in the drive on the CMOS structures, when the signals at the address input of the device change and when the main power supply is switched.

It is also known a storage device with preservation of information when the power is turned off, which contains a drive, a resident power source, a gateway, threshold elements, switches, a trigger, a delay element, and an OR 2 element.

The disadvantage of this device is the possibility of destroying the information recorded in the storage on CMOS structures, when the signals at the address input of the device change.

The closest in technical essence to the present invention is a storage device with a backup power source comprising a storage device, a interface unit, a threshold element, a separating, filtering and restricting elements, and a backup power supply, the storage power input of the storage device being connected to the zero potential terminal, through the limiting element to the output of the backup power source and directly to one of the terminals of the separation element, the other output of which is the input threshold the element and the input of the interface unit are connected to the input of the main power supply of the device, the information input and output of accumulators are connected respectively to the first output and input of the interface unit, the second, third, fourth and fifth inputs and the second output of which are address, read, write and information inputs and information output devices, respectively 3.

A disadvantage of this device is the possibility of destroying information stored in a drive made on CMOS structures when the signals at the address input of the device change.

This disadvantage is due to the fact that at a nominal voltage of a primary power source, the drive input is constantly under the resolving potential and therefore when changing the address signals, or if there is interference on the device’s input address at a fixed address,

storage information, ie, its destruction.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that - into a storage device with information preserved when power is turned off, containing a drive, interface block, threshold filtering and limiting elements, a backup power source, the first drive input connected via a filtering element to the zero potential terminal, through restrictive element to the output of the backup power source and to one

5 of the terminals of the separation element, another terminal of which is connected to the input of the threshold element, the first input of the interface unit and the power supply panel, the second input and output of the storage device are connected respectively to the first output and the second input

0 interface block, the third input, which is address, the fourth input is information, the fifth and sixth inputs are control inputs of the device, the second output of the interface block is the informational output of the device, the address register, the OR element, the first and the second elements are AND, the first and second pulse formers and the delay element, the third output of the interface block is connected to the first input of the register of the address, the fourth output to the first input of the OR element, the fifth output to the second input of the OR element and the first input of the second second AND gate, a second input coupled to a first input of the first AND gate and the output of the threshold element,

the second input of the first element AND is connected to the output of the OR element, the third input of which is connected to the power supply, the output of the first element AND is connected to the first input of the first pulse generator,

Q output of which is connected to the second input of the address register and the first input of the delay element, the output of which is connected to the first input of the second pulse shaper, the output of which is connected to the third input of the accumulator, the outputs of the address register

5 and the second element And are connected respectively to the fourth and fifth inputs of the accumulator, the third inputs of the address register, the first and second elements And, the second inputs of the pulse shapers and the delay element are connected to the first input of the accumulator.

FIG. 1 shows a functional diagram of the device; in fig. 2 - an example of the implementation of the threshold element; in fig. 3 temporary diagram of the device.

5 The device contains a storage unit 1, a conjugation unit 2, a separating element 3, for example, a diode, a backup power source 4, made, for example, as a block of ionics CI1 -1 or KI1-2 restricting element 5, for example, a resistor, filtering element 6 for example, capacitor, threshold element 7, address register 8, element OR 9, first element 10, first pulse generator 11, delay element 12, second pulse generator 13 and second element 4, zero potential bus 15, power 16, addresses 17, read 18, write 19, informational input 20 and output 21 devices. va.

The threshold element 7 (Fig. 2) contains a Zener diode 22, transistors 23 and 24 and resistors 25-31. At the output of the threshold element, at a certain value of the supply voltage, there is a high voltage level (logical "1), and when the voltage drops below this value, a low voltage level (logical" O). Thus, at the output there is a logical "1 at such a value of the voltage of the main power source, at which the interface block 2 and the element OR 9 correctly perceive and convert the input signals of the device, i.e., do not introduce their own interference into the device.

The device works as follows.

The main supply voltage of the device from the input 16 is supplied to the interface 2, the threshold element 7, the element OR 9 directly and through the separating element 3 to the drive 1, the address register 8, the drivers 11 and 13 pulses, the delay element 12 and the elements And 10 and 14. In this way, all the elements of the device are powered and, through the limiting element 5, the backup power source 4 (ionistor unit) is charged with a nominal charging current.

For the nominal operation of the device, it is necessary that the read and write signals at the device input appear after the address signal with a delay determined by the switching time of the address register 8.

At a certain voltage level at the device input 16, the output signal of the logical 1 from the threshold element 7 allows the input or input signal of the read or write signal coming from the input 18 or 19 of the device through the interface 2 and the OR element to pass through the element 10 to the trigger input of the shaper. 9. In this case, the driver P generates a signal C (Fig. 3), the duration Tf. Sigu Cj is used to lock the address register 8, ensuring that the signals at its output remain constant when the signals at the information input change. In addition, the signal Cf arrives at the element 12, which delays it by the time Tj, determined by the switching time of the address register 8. In order to increase the speed of the device, the delay element 12 can be made so that it only delays the leading edge of the incoming signal Q (shown in Fig. 3 by a dashed line). The signal C from the output of the delay element 12 starts the driver 13 to form a signal C; duration T, which is the resolution signal for storage 1.

Signal formation Cj with a delay of time T is intended to delay the appearance of the permissive signal at the same input of accumulator 1 when switching signals at its address input caused by the appearance of an interference signal at address address 17 of the device before blocking the address register 8. The formers 11 and 13 pulses and the delay element 12 must ensure the condition T, Tg + Tz.

The impact of signal C on the input of the accumulator 1 resolution, passing after the end of the transient processes in the address register 8, i.e., with unchanged signals at the input of the address of the accumulator 1, completely protects the information in the accumulator from destruction, even if the correct sequence of signals on the address An input 17 and an input 18 of the device or interferences to the indicated inputs of the device interfere with the correct sequence of input signals.

In the information recording mode, the input control signal of the recording from the input 19 of the device through the block 2 interface and the element 14, unblocked by the logic signal "1 from the output of the threshold element 7, the drive 1 at the mode selection input is set to record information, at other times reading information.

When the voltage goes down while the main power supply is turned off to the value of switching off the threshold element 7, the latter locks the And 14 element with a logic signal “O”, prohibiting the element in recording mode and And 10, prohibiting the trigger signal to enter the driver 11. Since the blocking of the element 10 can occur during its operation at the second input of the trigger signal, a shortened signal can be sent to the input of the pulse shaper 11, which is equivalent to the internal interference of the device. This internal disturbance cannot distort the Q-Cj signal generation cycle that has already begun, since the duration of the output signal C of the driver 11 of the pulse does not depend on the duration of the signal at its input, and the drivers of the 11 and 13 pulses and the element

12 delays are powered by backup power source 4. The impact of the signals Cj on the address register 8 and Cz on drive 1 and in this case, as in the operation of the device at the nominal voltage of the main power source, prevents switching signals at the address input of drive 1 when there is an enable signal at the same input of drive 1, t. e. prevents the destruction of information in the drive 1.

After the generation of Cj-Cz signals is completed, the storage device 1 is switched to information storage mode (there is no Cz signal at the input of the drive 1) with the minimum power consumption at its power input.

Register 8 addresses, elements 10 and 14, drivers 11 and 13 pulses and delay element 12 can be performed, like drive 1, on CMOS elements with a minimum current consumption. it

allows you to store information recorded in the memory 1 for a long period of time when the main power source is not powered.

When the voltage increases while the main power source is turned on to the threshold element 7's on value, the latter signal unlocks the AND 10 and 14 elements by a signal, allowing both reading and writing of information to the drive 1. A possible occurrence in this case at the output of the AND 10 shortened trigger pulse, which can be considered as an internal interference of the device, will not lead

to the destruction of information in drive 1, because in this case, as well as turning off the main power source, the timing diagram of the GI-Ce signals is not disturbed.

When using the proposed device, it is possible to save the recorded information without destroying when the signals at its address input change.

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Claims (1)

STORING INFORMATION WITH STORING INFORMATION WHEN POWER OFF, containing a drive, interface unit, threshold, isolation, filtering and limiting elements, a backup power source, the first input of the drive connected through the filter element to the zero potential bus, through the restrictive element to the output of the backup power source and to one of the terminals of the separation element, the other terminal of which is connected to the input of the threshold element, the first input of the interface unit and the power bus, the second input d and the drive output are connected respectively to the first output and the second input of the interface unit, the third input of which is addressable, the fourth input is informational, the fifth and sixth inputs are the control inputs of the device, the second output of the interface unit is the information output of the device, characterized in that , in order to increase reliability, it contains an address register, an OR element, first and second AND elements, first and second formers ¹ pulse drivers and a delay element, and the third output of the interface unit is connected to the first at the input of the address register, the fourth output is to the first input of the OR element, the fifth output is to the second input of the OR element and the first input of the second AND element, the second input of which is connected to the first input of the first AND element and the output of the threshold element, the second input is the first AND element connected to the output $ of the OR element, the third input of which is connected to the power bus, the output of the first element And is connected to the first input of the first pulse shaper, the output of which is connected to the second input of the address register and the first input of the delay element, the output is It is connected to the first input of the second pulse shaper, the output of which is connected to the third input of the drive, the outputs of the address register and the second element And are connected respectively to the fourth and fifth inputs of the drive, the third inputs of the address register, the first and second elements AND, the second inputs of the pulse shaper and element delays are connected to the first input of the drive. SU „, 1083236