SU783991A1 - Nonvolatile device - Google Patents

Description

one

The invention relates to the field of automation and computer technology and can be used in control complexes for automated process control systems.

A device is known in which the preservation of information during power outage occurs at the expense of the charge accumulated by capacitor 1.

The disadvantages of the known device are, firstly, the limited storage time of information, determined by the capacitor capacitance k, and secondly, the speed limit of the constant-time device of the capacitor discharge circuit.

It is also known a device that stores information when the power is turned off, contains a control bus, a setup device, a pulse generator, a memory, an output register, and a recording register, the outputs of which are connected to the inputs of the output register through the e-nomination element.

By using memory cells of the semi-permanent type as electric memory overwriting information, the known device can store information indefinitely, but its speed is not high enough. This is due to the fact that the read time from memory cells of a semi-permanent type with an electric rewriting of information does not exceed 1 microsecond, and the time for recording information in them in several orders of magnitude: for example,

1 in 0.3 ms is in memory cells based on ferrite cores and numerical rulers with a rectangular hysteresis loop, and 10–20 m sec. - in amorphous storage cells

f5 semiconductors and MNOPs - transistors. The known device is used for intermediate storage of information and issuing it for further processing or to the executive devices. In this case, the transmitted information goes to the recording register, from which it is copied to the storage element, then the output register 12 goes to the output of the device 2 .

A disadvantage of the known device is the low speed, since the output information with respect to

30 to the input appears with a delay of

the time of writing it to the storage element.

The aim of the invention is to increase speed.

To achieve this goal, a device that stores information when the power is turned off, contains a control bus, a storage element, a issuing register and a register, and the outputs of which are connected to the inputs of the register through the memory element, entered and issued and issued a group of elements OR element and NOT, the output of which is connected to the first inputs of the group of elements AND the issue, the second inputs of which are connected respectively to the outputs of the register of the issue, the input of the element is NOT connected to the pulse input A control unit, with the first inputs of a group of elements AND records, the second inputs of which are connected respectively to the outputs of the record register, the outputs of a group of elements AND records are connected respectively to the first inputs of a group of elements OR, the second inputs of which are connected, with the corresponding outputs of the group of elements AND issuing.

The drawing shows a block diagram of a device storing power-off power-off information.

A circuit consists of a register, issuing 1 register of record 2; storage element 3f group of elements And 4 records; a group of elements And 5 issuance j bus control b; element NOT 7 and group of elements OR 8

The outputs of the register of record 2 are connected to the inputs of the storage element 3, the outputs of which are connected to the inputs of the output register 1, the outputs of which are connected to the first inputs of the corresponding elements AND of the output group 5, the second inputs of which are connected to the output of the HE element 7, whose input is connected to the pulse input of the storage element 3, with the control bus bis the first inputs of the group of elements AND 4 records, the second inputs of which are connected to the corresponding outputs of the register of record 2, the outputs of the group of elements AND 4 of the record are connected respectively the first inputs of the elements of the group OR 8, whose second inputs are connected to respective outputs of the AND group

issuing ..

The operation of the device is as follows. .

In the storage mode, when the voltage is turned off by the power supply, the information is stored in. the memory cells of the memory element 3. After turning on the supply voltage, the output signals of the memory element 3 set the issue register 1 to the state corresponding to § 9Ж11 ((The information element 3 of information is sent to the control bus. No signal is sent to the control bus).

Bring records corresponding to a logical zero, which is inverted by the element NOT 7, thus allowing the output of information from the outputs of register 1 issuance through a group of 5 elements AND, a group of elements OR 8 to the outputs of the device.

When the information contained in register 2 of the record is changed, the control signal 6 receives a write signal corresponding to the logical unit. With the presence of this signal, the information recorded at the outputs of register 2 is stored in memory element 3, which lasts from 0, 3 ms to 20 ms, depending on the type of memory element 3. At this time, the output of the element is HE 7 and the level of logical zero and without changing the information from the outputs of the output register 1 does not pass through the group of elements AND 5 Hci inputs of the group of elements OR 8. When a level of logical unit appears at the combined inputs of the group of elements AND 4, the device outputs are connected to the outputs of the register 2 recording via gr upp elements 4 and a group of elements OR 8.

At the end of the recording of information in the storage element 3 on the control bus 6, the logic device level appears in the information storage mode.

Thus, the proposed device, in comparison with the known ones, makes it possible to shorten the time for transferring information from the register to the outputs of the device by 0.3–20 ms, depending on the type of storage element used, which significantly increases its speed.

Claims (2)

1. Author's certificate of the USSR 320931, H 03 K 17/22, 1974. 2. Author's certificate of the USSR 321946, H 03 K 17/22, 1974.