JP2692641B2 - Non-volatile memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a nonvolatile memory cell,
In particular, it relates to a non-volatile memory cell using a ferroelectric material.

[0002]

2. Description of the Related Art In recent years, a ferroelectric material having hysteresis characteristics such as PZT (lead zirconate titanate) has been used for a memory cell, and a nonvolatile memory having a function of retaining memory even when power is turned off has been realized. There is. Among such non-volatile memories, various non-volatile memory cells having a structure in which a ferroelectric capacitor is connected to a volatile memory cell of SRAM (static random access memory) type have been conventionally proposed.

FIG. 9 shows a conventional non-volatile memory cell in which a ferroelectric capacitor is connected to a node of the memory cell.
A configuration example of the non-volatile memory cell disclosed in Japanese Patent Laid-Open No. 64-66899 is shown. This is a circuit commonly referred to as "Shadow RAM".

In FIG. 9, 7 and 8 are bit lines, 9 is a word line, and 10 to 14 are clock input signals. 101 and 102 are P-channel transistors, 103 and 104 are N-channel transistors, and the transistors 101 to 104 form flip-flops (CMOS static RAM cells) that store data in the memory cells. 107 and 108 are ferroelectric capacitors, 109 and 110 are access transistors that connect the internal nodes of the flip-flops to the bit lines 7 and 8, and 11
Reference numerals 1 and 112 are isolation transistors, and reference numerals 113 and 114 are short-circuit transistors. Note that the isolation transistors 111 and 112 are turned off during normal operation, and the voltage transition that occurs at the input / output node of the memory cell section during normal operation does not occur in the ferroelectric capacitor 10.
Not directly transmitted to 7,108.

FIG. 10 shows an example of the structure of a ferroelectric non-volatile memory cell disclosed in Japanese Patent Laid-Open No. 5-242667. FIG.
In 0, 9 is a word line, 10, 11, 12, 13, and 14 are clock input signals, 15 and 16 are two data input / output signals, 17 is an input signal of the pass transistor 118, and 18 is an output of the pass transistor 118. Signal, 115 is an inductive non-volatile memory cell, 10
1, 102 are P-channel field effect transistors, 103, 104
Is an N-channel field effect transistor, 107 and 108 are ferroelectric capacitors, 109 and 110 are access transistors, 11
Reference numerals 1 and 112 are isolation transistors, 113 and 114 are short-circuit transistors, 116 and 117 are paraelectric capacitors, and 118 is a pass transistor connected to the ferroelectric non-volatile memory cell 114.

In the case of the circuit of FIG. 10, the output node of the ferroelectric non-volatile memory cell 115 is connected to the gate of the pass transistor 118, and the pass transistor 118 is turned on / off depending on the stored contents of the non-volatile memory cell 115. Can be controlled. Therefore, by using such a non-volatile memory cell, PLA (Pro
grammable Logic Array) can be realized.

FIG. 11 shows an example of the structure of the ferroelectric non-volatile memory cell disclosed in Japanese Patent Laid-Open No. 4-367120. FIG.
In 1, 1 is a short circuit control signal, 7 and 8 are bit lines, and 9
Is a word line, 10, 11, 12, and 14 are clock input signals, 10
1, 102, 103, 104 are transistors forming a flip-flop, 119 is a short-circuit transistor, 107, 108 are ferroelectric capacitors, 109, 110 are access transistors, 111, 1
Reference numeral 12 is a separation transistor. This circuit is obtained by removing the transistors 113 and 114 that short-circuit the ferroelectric capacitor and the ground potential from the circuits shown in FIGS. 9 and 10 and adding a transistor 119 that short-circuits the output nodes of the flip-flops.

[0008]

In the future, for example, when the contents of a register in a processor are stored in a non-volatile manner, it is conceivable to use the above ferroelectric non-volatile memory cell.

However, in the ferroelectric non-volatile memory cells shown in FIGS. 9 to 11, since the access transistors 109 and 110 and the isolation transistors 111 and 112 are required, the area per unit memory cell is small. There is a problem of getting bigger.

Therefore, it is an object of the present invention to solve the above problems and provide a ferroelectric non-volatile memory cell having a smaller area.

[0011]

To achieve the above object, the present invention relates to a volatile memory circuit which is driven by first and second control inputs and outputs a complementary signal, and a first volatile memory circuit. First and second ferroelectric capacitors respectively connected between a first and a second input / output terminal and a third control input; and the first and second input / output terminals of the memory circuit and the A non-volatile memory cell, comprising: a first switch element and a second switch element respectively connected to a third control input.

In the nonvolatile memory cell of the present invention,
Preferably, the memory circuit has a first P channel having a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. -Type transistor and a second P-type transistor having a source connected to the first control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal.
A channel type transistor and a third N-type transistor having a source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal.
A fourth N-channel transistor having a channel type transistor, a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal.
And a channel type transistor.

In the nonvolatile memory cell of the present invention,
Preferably, the first and second P-channel transistors are TFTs.

In the nonvolatile memory cell of the present invention,
Preferably, the memory circuit has a first P channel having a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. -Type transistor, a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal.
A channel type transistor, a first resistance element connected between the second control input and the first input / output terminal,
A second resistance element may be connected between the second control input and the second input / output terminal.

In the nonvolatile memory cell of the present invention,
Preferably, the memory circuit includes a first resistance element connected between the first control input and the first input / output terminal, the first control input and the second input / output terminal. A second resistance element connected between the two, a source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. First
A second N-channel transistor having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal And a transistor.

In the nonvolatile memory cell of the present invention,
Preferably, the memory circuit has a first P channel having a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. -Type transistor, a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal.
A channel transistor, a first capacitor connected between the second control input and the first input / output terminal, and a connection between the second control input and the second input / output terminal And a second capacitor described above.

In the nonvolatile memory cell of the present invention,
Preferably, the memory circuit includes a first capacitor connected between the first control input and the first input / output terminal, the first control input and the second input / output terminal. A second capacitor connected in between, a source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal
A second N-channel transistor having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal And a transistor.

In the nonvolatile memory cell of the present invention,
Preferably, the capacitor is formed from a ferroelectric material.

In the nonvolatile memory cell of the present invention,
Preferably, when the power is turned on, (a) the potential of the first control input is set to the ground potential, and the potential of the second control input is set to the power supply potential to inactivate the memory circuit, b) precharging the electric potential of the third control input to the first electric potential, and (c) setting the first and second switch elements in a conductive state, and first and second input / output terminals of the memory circuit. Potential of the third control input is made equal to (d)
Setting the first and second switch elements in a non-conducting state, (e)
A second potential different from the first potential on the third control input;
To generate a potential difference between the ferroelectric capacitors and generate a potential difference on the first and second input / output terminals due to a difference in the spontaneous polarization state of the ferroelectric substance,
(f) The potential of the first control signal is set to the power supply potential, the potential of the second control signal is set to the ground potential to activate the memory circuit, and the first and second input / output terminals are set. Is amplified and stably output, and the data stored in the ferroelectric capacitor is read out.

In the nonvolatile memory cell of the present invention,
Preferably, when the power is turned off, (a) the potential of the first control input is set to the power supply potential and the potential of the second control input is set to the ground potential to activate the memory circuit, and (b) ) Changing the potential of the third control input from the second potential to the first potential, (c) setting the potential of the first control input to a ground potential, and By setting the potential to the power supply potential, the memory circuit is deactivated, and (d) the first and second switch elements are brought into conduction, and the potentials of the first and second input / output terminals of the memory circuit are set. Is made equal to the potential of the third control input, and the data stored in the memory circuit is written to the ferroelectric capacitor. When the power is turned on and off, the first potential is preferably ground potential, and the second potential is preferably power supply potential.

[0021]

According to the present invention, the area of the memory cell is made smaller than that of the conventional example by removing the access transistor and the isolation transistor from the ferroelectric non-volatile memory cell. And in the present invention,
Preferably, when the power is turned on, the switching elements are short-circuited to reduce the potential difference between the ferroelectric capacitors to zero, and then the third
By increasing the potential of the control input of, the data stored in the ferroelectric capacitor is read as a potential difference and amplified by the memory circuit including the flip-flop.
When the power is turned off, the potential of the third control input is lowered,
After writing the potential difference of the flip-flop circuit to the ferroelectric capacitor, the potential difference between the ferroelectric capacitors is set to zero by the switch element.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of one embodiment of the present invention.

In FIG. 1, reference numerals 1 and 2 are two complementary data input / output signals, first and second, 3 is a first control input, 4 is a second control input, 5 is a third control input, and 6 is a control input. Is a short-circuit control signal, 101 and 102 are P-channel field effect transistors, 10
Reference numerals 3 and 104 are N-channel field effect transistors, and the transistors 101 to 104 form a flip-flop circuit 100. Reference numerals 105 and 106 are N-channel field effect transistors (also referred to as “short-circuit switches”), and 107 and 108 are ferroelectric capacitors. N-channel field effect transistor 10
Reference numerals 5 and 106 are connected in parallel to the ferroelectric capacitors 107 and 108 between the input / output node of the flip-flop circuit 100 and the third control input 5, and the short-circuit control signal is connected to the gates.

Referring to FIG. 1, the flip-flop circuit 100 of this embodiment is a P-channel field effect transistor 10.
Although it is composed of four transistors 1 and 102 and N-channel field effect transistors 103 and 104, various structures as described below may be adopted.

For example, as shown in FIG. 2, the P-channel field effect transistors 101 and 102 of FIG. 1 may be constituted by TFTs (thin film transistors).

Further, as shown in FIG. 2, two resistance elements 120 and 121 may be inserted instead of the N-channel field effect transistors 103 and 104 of FIG.

Further, as shown in FIG. 3, two resistance elements 120 and 121 may be inserted instead of the P-channel field effect transistors 101 and 102 of FIG.

As shown in FIG. 4, two capacitors 122 and 123 may be inserted instead of the N-channel field effect transistors 103 and 104 of FIG.

Further, as shown in FIG. 5, two capacitors 122 and 123 may be inserted instead of the P-channel field effect transistors 101 and 102. A ferroelectric material such as PZT may be used as the capacitors 122 and 123 in the circuits of FIGS. 4 and 5.

Next, referring to the waveform diagrams of FIGS. 6 and 7,
The operation of this embodiment shown in FIG. 1 will be described. FIG. 6 is an operation waveform when the power is turned on, and FIG. 7 is an operation waveform when the power is turned off.

In the ferroelectric non-volatile memory cell of the present embodiment, the access transistor and the isolation transistor provided in the conventional example are omitted, and the ferroelectric capacitors 107 and 108 are changed to the flip-flop circuit 100. Data transfer, that is, loading from the non-volatile portion to the volatile portion is performed at power-on, and conversely, the flip-flop circuit.
Data transfer from 100 to the ferroelectric capacitors 107 and 108, that is, restoration from the volatile portion to the non-volatile portion is performed when the power is turned off.

When the power is turned on, referring to FIG. 6, a period T1
Then, the first control input 3 is set to the ground potential, the second control input 4 is set to the power supply potential, the third control input 5 is set to the ground potential, and the short-circuit control signal 6 is set to the power supply potential. At this time, the flip-flop circuit 100 is deactivated and does not amplify the difference potential between the two outputs 1 and 2.

In the period T2, when the potential of the short-circuit control signal 6 exceeds the threshold voltage V _th of the N-channel field effect transistors 105 and 106, the N-channel field effect transistor 10 is detected.
The transistors 5 and 106 become conductive and act as a short-circuit switch, and the outputs 1 and 2 of the flip-flop circuit 100 are both made equal to the potential of the third control input 5 (= ground potential).

In the periods T1 and T2, the ferroelectric capacitor
The potential difference applied between 107 and 108 is suppressed to the threshold voltage V _th at the maximum by the action of the short-circuit switch, so that the information stored in the ferroelectric capacitors 107 and 108 is not destroyed during this time.

Next, in the period T3, the short-circuit control signal 6 is lowered to a low level, and the N-channel field effect transistors 105, 1
06 is turned off. Then, the third control input 5 is raised to a high level (= power supply potential).

Here, it is assumed that data "1" is stored in the ferroelectric capacitor 107 and data "0" is stored in the ferroelectric capacitor 108 before the power is turned on, and the hysteresis characteristic thereof is as shown in FIG. It is assumed that it is

At this time, the polarization of the ferroelectric capacitor 107 changes from a to b, and the polarization of the ferroelectric capacitor 108 changes from c to b.
And the potentials V ₁ and V ₀ proportional to the charges Q ₁ and Q ₀ are read out to the outputs 1 and 2 of the flip-flop circuit 100, respectively.

In the period T4, the flip-flop circuit 100 is activated by setting the first control input 3 to the power supply potential and the second control input 4 to the ground potential. As a result, the potential difference between the two outputs 1 and 2 of the flip-flop circuit 100 is amplified, and the loading of the data stored in the ferroelectric capacitors 107 and 108 into the flip-flop circuit 100 is completed.

Next, referring to FIG. 7, the operation when the power is turned off will be described.

In the period T5, the first control input 3 is set to the power supply potential and the second control input 4 is set to the ground potential, so that the flip-flop circuit 100 is activated.

In the period T6, the third control input 3 is lowered from the power supply potential to the ground potential, the polarization of the ferroelectric capacitor 107 is moved from b to d, and the polarization of the ferroelectric capacitor 108 is moved from c to b ( (See FIG. 8).

In the period T7, the first control input 3 falls from the power supply potential to the ground potential, and the second control input 4 rises from the ground potential to the power supply potential. As a result, the flip-flop circuit 100 is deactivated.

In the period T8, the short-circuit control signal 6 rises to the power supply potential, and the outputs 1 and 2 of the flip-flop circuit 100 are both made equal to the potential of the third control input 3 (= ground potential).

As a result, the polarization of the ferroelectric capacitor 107 moves from d to a, and the polarization of the ferroelectric capacitor 108 remains b. Therefore, the ferroelectric capacitor 107
The data "1" is written to the ferroelectric capacitor 108 and the data "0" is written to the ferroelectric capacitor 108, and the restoration of the data from the flip-flop circuit 100 to the ferroelectric capacitors 107 and 108 is completed.

As described above, the present invention has been described with reference to the above embodiments. However, the present invention is not limited to the above embodiments, but includes various embodiments according to the principle of the present invention.

[0046]

As described above, by using the ferroelectric non-volatile memory cell of the present invention, the circuit overhead for non-volatilely storing the contents of the register in the processor can be made smaller than before.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a nonvolatile ferroelectric memory cell according to an embodiment of the present invention.

FIG. 2 is a diagram showing a second mode of the flip-flop circuit 100 in FIG.

FIG. 3 is a diagram showing a third mode of the flip-flop circuit 100 in FIG.

FIG. 4 is a diagram showing a fourth mode of the flip-flop circuit 100 in FIG.

5 is a diagram showing a fifth mode of the flip-flop circuit 100 in FIG.

FIG. 6 is a diagram showing operation waveforms of the nonvolatile ferroelectric memory cell according to one embodiment of the present invention when the power is turned on.

FIG. 7 is a diagram showing operation waveforms of the nonvolatile ferroelectric memory cell according to the embodiment of the present invention when the power is turned off.

FIG. 8 is a diagram for explaining hysteresis characteristics of two ferroelectric capacitors in FIG.

FIG. 9 is a diagram showing a configuration of a first conventional example of a nonvolatile ferroelectric memory cell.

FIG. 10 is a diagram showing a configuration of a second conventional example of a nonvolatile ferroelectric memory cell.

FIG. 11 is a diagram showing a configuration of a third conventional example of a nonvolatile ferroelectric memory cell.

[Explanation of symbols]

1, 2 First and second two complementary data input / output signals 3 First control input signal 4 Second control input signal 5 Third control input signal 6 Short circuit control signal 7, 8 Bit line 9 Word line 10 , 11, 12, 13, 14 Clock input signal 15, 16 Data input / output signal 17 Input signal of pass transistor 118 18 Output signal of pass transistor 118 100 Flip-flop circuit 101, 102 P channel field effect transistor 103, 104 N channel Field effect transistor 105, 106 Short-circuit transistor 107, 108 Ferroelectric capacitor 109, 110 Access transistor 111, 112 Separation transistor 113, 114 Short-circuit transistor 116, 117 Paraelectric transistor 118 Pass transistor 119 Short-circuit transistor 120, 121 Resistor element 122, 123 capacitor V _th N-channel field effect transistor 105, 1 of FIG.
06 threshold voltage a, b, c, d position V ₁ and V ₀ in the hysteresis curve of the ferroelectric capacitors 105 and 106 From the ferroelectric capacitors 105 and 106 corresponding to data “1” and “0” Electric potential to be read

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/11 29/788 29/792

Claims (11)

(57) [Claims] 1. A volatile memory circuit which is driven by first and second control inputs and outputs complementary signals; first and second input / output terminals of the memory circuit; and a third control input. And a first and second ferroelectric capacitors respectively connected between the first and second input / output terminals of the memory circuit and the third control input. 1. A non-volatile memory cell comprising: a first and a second switch element. 2. A first memory circuit having a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. A P-channel transistor and a second P-channel transistor having a source connected to the first control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal. A source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal, and a source connected to the third N-channel type transistor. A fourth N-channel transistor connected to the second control input, having a drain connected to the second input / output terminal, and having a gate connected to the first input / output terminal. According to claim 1, Nonvolatile memory cell. 3. The non-volatile memory cell according to claim 2, wherein the first and second P-channel transistors are TFTs. 4. A first memory circuit having a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. A P-channel transistor and a second P-channel transistor having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal. A first resistance element connected between the second control input and the first input / output terminal; and a first resistance element connected between the second control input and the second input / output terminal. The non-volatile memory cell according to claim 1, further comprising: 5. The memory circuit includes a first resistance element connected between the first control input and the first input / output terminal, the first control input and the second input / output. A second resistance element connected to the terminal, a source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. And a second N-channel transistor having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal. The non-volatile memory cell according to claim 1, further comprising: 6. A first circuit wherein the memory circuit has a source connected to the first control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. A P-channel transistor and a second P-channel transistor having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal. A first capacitor connected between the second control input and the first input / output terminal; and a second capacitor connected between the second control input and the second input / output terminal. The non-volatile memory cell according to claim 1, further comprising: 7. The memory circuit includes a first capacitor connected between the first control input and the first input / output terminal, the first control input and the second input / output terminal. A second capacitor connected between the second input and output terminals, a source connected to the second control input, a drain connected to the first input / output terminal, and a gate connected to the second input / output terminal. A first N-channel transistor and a fourth N-channel having a source connected to the second control input, a drain connected to the second input / output terminal, and a gate connected to the first input / output terminal. The non-volatile memory cell according to claim 1, further comprising a type transistor. 8. The non-volatile memory cell according to claim 6, wherein the capacitor contains a ferroelectric material. 9. When the power is turned on, (a) the potential of the first control input is set to the ground potential, and the potential of the second control input is set to the power supply potential to inactivate the memory circuit. , (B) pre-charging the potential of the third control input to the first potential, and (c) setting the first and second switch elements in a conductive state,
The electric potentials of the first and second input / output terminals of the memory circuit are made equal to the electric potential of the third control input, (d) the first and second switch elements are made non-conductive, and (e) the The potential of the third control input is set to a second potential different from the first potential to generate a potential difference between the ferroelectric capacitors, and the ferroelectric capacitors are formed on the first and second input / output terminals. (F) The potential of the first control signal is set to the power supply potential, and the potential of the second control signal is set to the ground potential, and the potential difference caused by the difference in the spontaneous polarization state of the body is generated. 2. The memory circuit is activated, the potential difference between the first and second input / output terminals is amplified and stably output, and the data stored in the ferroelectric capacitor is read. Non-volatile memory cell. 10. When the power is turned off, (a) the potential of the first control input is set to the power supply potential and the potential of the second control input is set to the ground potential to activate the memory circuit, (b) changing the potential of the third control input from the second potential to the first potential, (c) setting the potential of the first control input to a ground potential, and the second control Setting the input potential to the power supply potential to inactivate the memory circuit, and (d) bring the first and second switch elements into conduction,
The first of the memory circuit, the claims of the potential of the second input-output terminal is equal to the potential of said third control input, and writes the stored data of the memory circuit to the ferroelectric capacitors 1. The nonvolatile memory cell according to 1. 11. The first potential is a ground potential, and the second potential is a power supply potential.
Alternatively, the nonvolatile memory cell according to 10 above.