SU600739A1 - Counter keeping information at power supply breaks - Google Patents

Description

one

The invention relates to computing and can be used in estimates, max automation and remote control.

Counters are known that store information during power interruptions, contain triggers, memory elements, a generator of single-pulse pulses, the output of a single pulse generator is connected to one of the trigger inputs, and the output of memory elements is connected to the second trigger input 1.

However, a common drawback of the known devices is that the recording of information in the memory elements is performed on a special signal that comes from external control devices.

In this case, there is a probability of loss of information in the event of power failure before the arrival of the recording signal from the control device.

The closest in technical essence to the invention is a counting device, containing two delay lines, triggers connected in series, prohibition circuits, memory elements and a single pulse generator, the output of which is connected to one of the trigger inputs and through the delay line memory elements 2.

The main disadvantage of the counting device

is that information is written to the memory elements at the end of the counting signal, and there is a possibility that information is lost if H1 tann is turned off before the end of the counting process. In addition, the real possibility of re-turning off the power before the next counting cycle is real, and the information recorded in the meter triggers will not be overwritten into memory elements, but destroyed.

The goal of the 11300 is to increase the reliability of the device. In this case, it is possible to expand the field of application of the device.

This is achieved by the fact that in a device containing two delay lines, triggers connected in succession to the inhibit circuit, memory elements ii a single pulse generator, the output of which is connected to one of the trigger inputs and through the delay line to the memory read inputs, regeneration circuit separation unit, information recording permission blocks in the memory elements and information clearing permission blocks in the memory elements, the signal inputs of the information recording permission blocks are connected to the direct the trigger outputs, the inversion outputs of which are connected to the signal inputs of the resolution clearing blocks in the memory elements, and the control inputs of the recording resolution blocks and the information in the memory and Olokova clearing and shaping elements in the memory elements are connected to two headers connected in succession. emulsions, as well as through a split circuit of the regeneration circuits are connected to the counting input of the device, while the outputs of the blocks permit clearances and OLOKOB erasure and erasure in the memory elements are connected respectively to the inputs of the recording and the inputs of the memory element storage, the outputs of which are connected to the signal inputs of the inhibit circuits, and the control inputs of the inhibit circuits through the delay line are connected to the generator of single pulses, and the outputs of the inhibit keys to the second trigger inputs .

The drawing shows the block diagram of the device.

The account input 1 of the device is connected to the trigger 2 of the counter, while the direct outputs of the trigger 2 are connected to the signal inputs of the blocks for enabling information to be recorded, and the inverted outputs of the trigger 2 are connected to the signal inputs of the blocks 4 enabling erasure of information. In this case, the outputs of the recording permission units 3 are connected to the recording inputs of the memory elements 5, and the outputs of the erase resolution units 4 are connected to the erase inputs of the memory elements 5. The control inputs of the recording resolution blocks 3 and the erasure resolution blocks 4 are connected through the regeneration circuit separation block b to the device 1 counting device, and also connected through a series of delay lines 7 and 8 are connected to the generator U of single pulses.

The generator 9 is also connected to the ustaiochi inputs of the flip-flops 2 and, via the delay line 8, to the inputs of the memory of the 5 memory elements.

In addition, the generator 9 is connected via a delay line 8 to the control inputs of the circuits 10, the signal inputs of which are connected to the outputs of the memory 5. In this case, the outputs of the prohibition circuit 10 are connected to the second setup inputs of the flip-flops 2.

The device works as follows. Its counting input 1 receives impulses of definite (positive) field, the number of which is considered to be triggers 2, while at the present time the flashing trigger 2 is in the state "O or" 1, i.e. a certain combination is present in its para-phase outputs output level levels. If trigger 2 is in the state "1, then at its forward output a high voltage level (conventionally adopted as logical" 1), while the corresponding recording resolution block is turned on and writes "1 to memory element 5, so as its control input, through the block 6 of the regeneration circuits is divided, a pulse of positive polarity also comes from the counting input 1 of the device.

At the same time, unit 4 allowing the erasure of the corresponding bit of the counter is turned off, since its control and signal inputs contain a difference in the signal level combinations.

If the trigger 2 of this counter counter is switched to the state of "About the counting pulse, then at the sequential input of block 4 of this counter counter Io there is a potential" 1, and the control signal is a pulse of positive polarity. At this, the erase unit 4 of the day discharge is switched on and executes the recording "and in the element 5 and the typing of this bit of the counter.

All bits of the counting device work in the same way.

If at some point the device turns off and then turns on, then the generator of 9 single impulses is activated. The impulse from the output of the heater 9 sets all the trigger 2 of the counter to “O” and after a time determined by the delay line 8 performs the reading of the information previously recorded in memory elements 5. In addition, the pulse from the output of the generator 9 is also fed to the control inputs of the prohibition circuits 10. In this case, the prohibition schemes 1U of those bits of the counter, in the memory elements 5 of which were previously recorded as "1", are opened as a result of the influence of both inputs of monopole pulses that overlap in time. Opening the prohibition schemes 10 causes the matching of the corresponding triggers 2 to complete; logical "1", i.e., the information recorded before the power is turned off in the meter triggers, is restored.

Next, the output impulse of the geierator 9 through the iromel time duct, defined by the 7 line of the transducer, enters the control inputs of the recording units 3 and the information erasure units 4. In this case, the elements 5 of the memory of those bits of the counter, trigger 2 of which are switched to the state "1," are recorded as "1 - a similar recording process occurring in the counting mode and described above.

In order to prevent the counter from shifting the counter to +1 in the elements 5 and these data recovery process, the regeneration circuit separation unit 6 is introduced. Further operation of the device is performed in the counting mode.

In the experimental verification of the performance of the proposed device, the logical part was completely made on integrated circuits of wide use, and plug-in transformers on ferrite toroidal cores were used as memory elements.

The proposed counting device ensures the proper operation of the power supply switching unit at any time during the counting cycle.

Claims (2)

1. USSR author's certificate number 321946, cl. H OZK 17/22, 01.27.71. 2.Avtirskoe certificate of the USSR No. 364112. N OZK 23/10, 25.12.72.