JPH0722358A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0722358A JPH0722358A JP14339393A JP14339393A JPH0722358A JP H0722358 A JPH0722358 A JP H0722358A JP 14339393 A JP14339393 A JP 14339393A JP 14339393 A JP14339393 A JP 14339393A JP H0722358 A JPH0722358 A JP H0722358A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- tape
- protective
- dicing
- reinforcing tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方
法、特に、パッケージ厚が０．５ｍｍ以下の樹脂封止型
半導体装置の製造方法に関するものであり、更に詳しく
は、該半導体装置に用いられるウエハーの裏面研磨工程
〜ダイシング工程に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a resin-sealed semiconductor device having a package thickness of 0.5 mm or less. Wafer back surface polishing process to dicing process.
【０００２】[0002]
【従来の技術】現在、図１１のメモリーカードにおけ
る、現在の樹脂封止型半導体装置及び本発明を用いて製
造された樹脂封止型半導体装置の実装状態図に示すよう
に、メモリーカードの厚さに関しては、規格が決まって
いる。例えば、現在のメモリーカードに搭載されている
パッケージ厚が、１．０ｍｍの樹脂封止型半導体装置の
場合、ＪＥＩＤＡ規格が３．３ｍｍｔでは両面実装、ま
た、２．２ｍｍｔでは片面実装が行われている。そし
て、このパッケージ厚１．０ｍｍの樹脂封止型半導体装
置に用いられるウエハーは、厚さが４００μｍ程度のも
のが用いられている。一方、ウエハー径は、取り数アッ
プを目的として、ますます大口経化され、８インチ径が
主流になりつつある。2. Description of the Related Art Currently, as shown in the mounting state diagram of the present resin-encapsulated semiconductor device and the resin-encapsulated semiconductor device manufactured by using the present invention in the memory card of FIG. With regard to this, the standard has been decided. For example, in the case of a resin-sealed semiconductor device with a package thickness of 1.0 mm mounted on a current memory card, double-sided mounting is performed when the JEIDA standard is 3.3 mmt, and single-sided mounting is performed when the JEIDA standard is 2.2 mmt. There is. A wafer having a thickness of about 400 μm is used as a wafer used in the resin-sealed semiconductor device having a package thickness of 1.0 mm. On the other hand, the wafer diameter is becoming larger and larger, and the 8-inch diameter is becoming the mainstream.
【０００３】以下に、図９及び図１０を用いて、従来の
厚さ４００μｍ、８インチ径のウエハーについての、ウ
エハーの裏面研磨からダイシング工程までを説明する。Hereinafter, the processes from the back surface polishing of the wafer to the dicing process for a conventional wafer having a thickness of 400 μm and a diameter of 8 inches will be described with reference to FIGS. 9 and 10.
【０００４】図９は従来のウエハーの裏面研磨からダイ
シング工程までのプロセスフローチャートであり、図１
０は同プロセスフローチャートに伴うウエハーの加工状
態の断面図である。FIG. 9 is a process flowchart from the conventional wafer back surface polishing to the dicing process.
Reference numeral 0 is a sectional view of a processed state of the wafer according to the process flowchart.
【０００５】まず、裏面の研磨前のウエハー１の回路形
成面である表面の保護を目的として、エチレン酢酸ビニ
ル共重合体（以下、「ＥＶＡ」とする。）等から成るプ
ラスチックフィルム（以下、「ベースフィルム」とす
る。）（１４０μｍ）の片面にアクリル系接着剤（１０
μｍ）をラミネートした保護用テープ１０を研磨前のウ
エハー１の表面に貼り付け（図９（ａ）、図１０
（ａ））、研磨前のウエハー１の裏面を研磨した後（図
９（ｂ）、図１０（ｂ））、研磨完了後のウエハー３の
表面から保護用テープ１０を剥離して（図９（ｄ）、図
１０（ｄ））、ウエハー３の洗浄を行う（図９（ｅ）、
図１０（ｅ））。この際、保護用テープ１０の剥離方法
としては、図１０ｄに示すように、保護用テープ１０の
接着剤塗布面と反対側の表面との接着力が、保護用テー
プ１０とウエハー３の表面との接着力よりも大きい剥離
用テープ９を用いて引き剥がす方法が多く用いられてい
る。First, a plastic film (hereinafter, referred to as "EVA") made of an ethylene-vinyl acetate copolymer (hereinafter, referred to as "EVA") or the like for the purpose of protecting the front surface of the wafer 1 which is a circuit forming surface before polishing the back surface. Base film ”) (140 μm) on one side with an acrylic adhesive (10
The protective tape 10 laminated with (μm) is attached to the surface of the wafer 1 before polishing (FIG. 9A, FIG.
(A)), after polishing the back surface of the wafer 1 before polishing (FIGS. 9 (b) and 10 (b)), the protective tape 10 is peeled off from the surface of the wafer 3 after polishing (FIG. 9). (D), FIG. 10 (d), the wafer 3 is washed (FIG. 9 (e),
FIG. 10 (e)). At this time, as a method for peeling off the protective tape 10, as shown in FIG. 10d, the adhesive force between the protective tape 10 and the surface on the opposite side to the adhesive application surface is different between the protective tape 10 and the surface of the wafer 3. A method of peeling off using a peeling tape 9 having a larger adhesive strength than the above is often used.
【０００６】その後、研磨の終了したウエハー３はプロ
ービングによる電気テスト（以下、「ウエハーテスト」
とする。）を行い（図９（ｔ）、図１０（ｔ））、アセ
ンブリ工程に投入される。After that, the polished wafer 3 is subjected to an electrical test by probing (hereinafter, "wafer test").
And ) Is performed (FIG. 9 (t), FIG. 10 (t)), and the assembly process is performed.
【０００７】アセンブリ工程では、まず、金属のキャリ
アフレーム５を介して、ウエハー３の裏面をダイシング
用テープ４に貼り付ける（図９（ｃ）、図１０
（ｃ））。その状態でフルカット又はハーフカットにダ
イシングされ（図９（ｆ）、図１０（ｆ））、洗浄・乾
燥した後、ダイボンド工程に投入される。ダイボンド工
程では、テープ４を介してウエハー３の裏面からピンに
より一のチップ７だけ突き上げ、ダイボンドコレットに
よりダイボンドされる。なお、ハーフカットされたウエ
ハー３はブレイクされた後、ダイボンド工程に投入され
る。In the assembly process, first, the back surface of the wafer 3 is attached to the dicing tape 4 via the metal carrier frame 5 (FIGS. 9C and 10).
(C)). In that state, the wafer is diced into full cuts or half cuts (FIG. 9 (f), FIG. 10 (f)), washed and dried, and then put into a die bonding step. In the die-bonding process, only one chip 7 is pushed up from the back surface of the wafer 3 via the tape 4 by a pin and die-bonded by a die bond collet. The half-cut wafer 3 is broken and then put into a die bonding process.
【０００８】[0008]
【発明が解決しようとする課題】上記規格のメモリーカ
ードの容量アップを、パッケージ厚を薄くすることによ
って実現しようとする場合、１．０ｍｍ厚のパッケージ
を０．７〜０．８ｍｍ厚にしても、ＪＥＩＤＡ規格が
３．３ｍｍｔにおいては、３段実装しかできず、また、
ＪＥＩＤＡ規格が２．２ｍｍｔにおいては、パッケージ
厚１．０ｍｍの場合と同様に、片面（１段）実装しかで
きず、コスト面で問題があり、実用性に乏しい。 そこ
で、ＪＥＩＤＡ規格が３．３ｍｍｔにおける４段実装、
又は、ＪＥＩＤＡ規格が２．２ｍｍｔにおける２段実装
を行い、メモリカードの容量アップを図るためには、パ
ッケージ厚は、０．５ｍｍ以下となり、０．５ｍｍ厚の
パッケージに搭載可能な厚さが２００μｍ以下のチップ
を製造する必要が生じる。In order to increase the capacity of the memory card of the above standard by reducing the package thickness, even if the 1.0 mm thick package is 0.7 to 0.8 mm thick. , JEIDA standard is 3.3mmt, only 3 stages can be mounted.
When the JEIDA standard is 2.2 mmt, as in the case where the package thickness is 1.0 mm, only one side (1 step) can be mounted, there is a problem in terms of cost, and practicability is poor. Therefore, the JEIDA standard has a 4-stage mounting at 3.3 mmt,
Alternatively, in order to increase the capacity of the memory card by performing the two-stage mounting in the JEIDA standard of 2.2 mmt, the package thickness is 0.5 mm or less, and the mountable thickness in the 0.5 mm thick package is 200 μm. The following chips need to be manufactured.
【０００９】しかし、上述の製造方法を用いて、現在主
流になりつつある８インチ径のウエハーを０．２ｍｍ以
下の厚さに研磨すると、ウエハー強度が極端に低下する
ため、その後のウエハーテスト工程、ダイシング用工程
における取り扱いや工程間搬送等でウエハーの割れる危
険性が非常に高くなるという問題点がある。However, when the above-mentioned manufacturing method is used to polish an 8 inch diameter wafer, which is becoming the mainstream at present, to a thickness of 0.2 mm or less, the strength of the wafer is extremely lowered. However, there is a problem that the risk of breaking the wafer becomes extremely high during handling in the dicing process, transportation between processes, and the like.
【００１０】そこで、本発明では、ウエハー裏面の研磨
からダイシングまでの間で、ウエハーを破壊することな
く加工でき、パッケージ厚が０．５ｍｍ以下の樹脂封止
型半導体装置の製造工程の歩留りを向上させる手段を提
供することを目的とする。Therefore, according to the present invention, the wafer can be processed from the back surface polishing to dicing without breaking the wafer, and the yield in the manufacturing process of the resin-sealed semiconductor device having a package thickness of 0.5 mm or less is improved. The purpose is to provide a means to do so.
【００１１】[0011]
【課題を解決するための手段】本発明では、上記課題を
解決するため、樹脂封止型半導体装置を製造するに当た
り、ウエハーの回路形成面である表面に、保護・補強用
テープを貼り付け、上記ウエハーの裏面研磨を行い、上
記保護・補強用テープを上記ウエハーの表面に張り付け
た状態で、最終ウエハー厚になった上記ウエハーを搬送
し、上記ウエハーの裏面をダイシング用テープに貼り付
けた後、上記保護・補強用テープを剥離し、ダイシング
することを特徴としている。In order to solve the above problems, in the present invention, when manufacturing a resin-sealed semiconductor device, a protective / reinforcing tape is attached to the surface of a wafer, which is a circuit forming surface, After the back surface of the wafer is polished and the protection / reinforcement tape is attached to the front surface of the wafer, the wafer having the final wafer thickness is conveyed, and the back surface of the wafer is attached to the dicing tape. The above-mentioned protective / reinforcing tape is peeled off and dicing is performed.
【００１２】上記ウエハーの裏面研磨は、最終ウエハー
厚が２００μｍ以下になるまで行われる。The backside polishing of the wafer is performed until the final wafer thickness becomes 200 μm or less.
【００１３】上記保護・補強用テープを剥離するには、
上記保護・補強用テープの接着剤塗布面と反対側の表面
に、紫外線を照射することにより、該保護・補強用テー
プの接着強度を低下させた後に剥離するという手段がと
られる。To peel off the protective / reinforcing tape,
By irradiating the surface of the protective / reinforcing tape opposite to the adhesive-coated surface with ultraviolet rays, the adhesive strength of the protective / reinforcing tape is reduced, and then the tape is peeled off.
【００１４】更に、上記ウエハーの裏面との接着力が上
記ウエハーの表面と上記保護・補強用テープとの接着力
より大きい上記ダイシング用テープに、上記ウエハーの
裏面を張り付け、上記保護・補強用テープの表面との接
着力が、上記ウエハーの表面と上記保護・補強用テープ
との接着力より大きい剥離用テープを、上記保護・補強
用テープの表面に張り付け、上記剥離用テープを剥離す
ることにより、上記保護・補強用テープを剥離すること
を特徴としている。Further, the back surface of the wafer is attached to the dicing tape whose adhesive strength with the back surface of the wafer is larger than the adhesive strength between the front surface of the wafer and the protective / reinforcing tape, and the protective / reinforcing tape is attached. By attaching a peeling tape whose adhesive strength to the surface of the wafer is larger than the adhesive strength between the surface of the wafer and the protective / reinforcing tape to the surface of the protective / reinforcing tape, and peeling the peeling tape. The protective / reinforcing tape is peeled off.
【００１５】更に、ウエハーテストは、最終ウエハー厚
に研磨するまでに行う。又は、上記ウエハーをダイシン
グ用テープに貼り付け、上記保護・補強用テープを剥離
した後に行うという工程がとられる。Further, the wafer test is conducted until the final wafer thickness is polished. Alternatively, a step of attaching the wafer to a dicing tape and peeling off the protection / reinforcement tape is performed.
【００１６】[0016]
【作用】本発明では、ウエハー裏面の研磨完了後に、最
終ウエハー厚（２００μｍ以下）のウエハー表面に保護
・補強用テープを貼り付けたままでダイシング工程へ搬
送し、このウエハー裏面にダイシング用テープを貼り付
けた後、剥離用テープを用いて保護・補強用テープを剥
離して、ダイシングにより１チップづつに切り分けられ
る。この結果、ウエハー研磨後はチップ状にダイシング
されるまで、保護・補強用テープまたはダイシング用テ
ープのいずれかによってウエハーが補強されているの
で、ウエハーハンドリングや搬送中にウエハーが破損す
る危険性が大幅に低減される。In the present invention, after polishing the back surface of the wafer, the wafer having the final wafer thickness (200 μm or less) is conveyed to the dicing step with the protection / reinforcement tape still attached, and the dicing tape is attached to the back surface of the wafer. After attaching, the protective / reinforcing tape is peeled off using a peeling tape, and the chips are cut into chips by dicing. As a result, after wafer polishing, the wafer is reinforced by either the protective / reinforcing tape or the dicing tape until it is diced into chips, so there is a significant risk of wafer damage during wafer handling and transportation. Is reduced to.
【００１７】さらに、従来ウエハー研磨後に実施してい
たウエハーテストを、（１）最終ウエハー厚（２００μ
ｍ以下）まで研磨する前に、又は（２）ウエハー裏面の
研磨完了後ダイシング用テープに貼り付け、その後保護
・補強用テープを剥離した状態で実施することにより、
ウエハーテスト工程でのウエハー破損を防止することが
できる。Further, the wafer test, which was conventionally performed after the wafer was polished, was (1) final wafer thickness (200 μm).
m) or less) or (2) after the back surface of the wafer is completely polished, it is attached to a dicing tape, and then the protective / reinforcing tape is peeled off.
It is possible to prevent wafer damage in the wafer test process.
【００１８】また、紫外線を照射することにより、ウエ
ハーとダイシング用テープの接着力を維持したまま保護
・補強用テープ剥離することができる。Further, by irradiating with ultraviolet rays, the protective / reinforcing tape can be peeled off while maintaining the adhesive force between the wafer and the dicing tape.
【００１９】[0019]
【実施例】本発明による４実施例を下記に示す。EXAMPLES Four examples according to the present invention are shown below.
【００２０】実施例１ 図１及び図２に，ウエハーの加工工程のプロセスフロー
チャートとそれに伴うウエハーの加工状態を示す。Embodiment 1 FIGS. 1 and 2 show a process flow chart of a wafer processing step and a wafer processing state accompanied therewith.
【００２１】（ｔ）所定の金属配線・パッシベーション
膜形成工程が完了し、裏面の研磨前の８インチ径ウエハ
ー１（ウエハー厚：７２５μｍ）の状態でウェハーテス
トを実施する。(T) A wafer test is carried out in a state of a wafer 1 (wafer thickness: 725 μm) of 8 inch diameter before polishing of the back surface after the predetermined metal wiring / passivation film forming step is completed.
【００２２】（ａ）裏面研磨前にウエハー１（以下、
「ウエハー１」とする。）表面に保護・補強用テープ２
を貼り付ける。保護・補強用テープ２は例えば、ポリエ
チレンテレフタレート（ＰＥＴ）フィルム（５００μｍ
厚）にアクリル系保護・補強用テープ接着剤（１０μ
ｍ）をラミネートしたものであり、４０℃程度に加熱し
た状態でウエハー１表面に貼り付ける。(A) Wafer 1 (hereinafter,
This is “wafer 1”. ) Tape 2 for protection and reinforcement on the surface
Paste. The protective / reinforcing tape 2 is, for example, a polyethylene terephthalate (PET) film (500 μm).
Acrylic-based protective / reinforcing tape adhesive (10μ)
m) is laminated and is attached to the surface of the wafer 1 while being heated to about 40 ° C.
【００２３】（ｂ）ウエハー１裏面を約５２５μｍ研磨
し（ウエハー厚：２００μｍ）、研磨完了後に、最終ウ
エハー厚（２００μｍ）のウエハー３（以下、「ウエハ
ー３」とする。）表面に保護・補強用テープ２を貼り付
けたままでウエハー３をダイシング工程へ搬送し、 （ｃ）保護・補強用テープ２を貼り付けた状態のウエハ
ー３裏面を金属キャリアフレーム５を介してダイシング
用テープ４に貼り付ける。ダイシング用テープ４は、例
えば、塩化ビニルフィルムに接着剤をラミネートしたも
のであり、テープ厚は８０μｍである。(B) The back surface of the wafer 1 is polished by about 525 μm (wafer thickness: 200 μm), and after the polishing is completed, the surface of the wafer 3 (hereinafter referred to as “wafer 3”) having the final wafer thickness (200 μm) is protected and reinforced. The wafer 3 is conveyed to the dicing step with the tape 2 for attaching is attached, and (c) the back surface of the wafer 3 with the tape 2 for protection / reinforcement attached is attached to the dicing tape 4 via the metal carrier frame 5. . The dicing tape 4 is, for example, a vinyl chloride film laminated with an adhesive, and has a tape thickness of 80 μm.
【００２４】（ｄ）図２に示すように、保護・補強用テ
ープ２を、保護・補強用テープ２裏面とウエハー３表面
の接着力よりも保護・補強用テープ２表面との接着力が
大きい剥離用テープ９を用いて引きはがす。この時、ウ
エハー３裏面を真空吸着により固定しておく。剥離用テ
ープ９は、ベースフィルムにＰＥＴを用い、これにアク
リル系接着剤より接着力が大きい天然ゴム系接着剤をラ
ミネートしたものを使用する。(D) As shown in FIG. 2, the protective / reinforcing tape 2 has a larger adhesive force between the rear surface of the protective / reinforcing tape 2 and the surface of the wafer 3 than that of the front surface of the wafer 3. It peels off using the peeling tape 9. At this time, the back surface of the wafer 3 is fixed by vacuum suction. For the peeling tape 9, a base film made of PET and a natural rubber adhesive having a larger adhesive strength than an acrylic adhesive is laminated on the PET.
【００２５】（ｅ）純水による超音波洗浄によりウエハ
ー３表面の接着剤の残りを洗い落とす。(E) The remaining adhesive on the surface of the wafer 3 is washed off by ultrasonic cleaning with pure water.
【００２６】（ｆ）ダイヤモンドホイールを用いてウエ
ハー３をダイシングし、所定のサイズのチップ７を形成
する。(F) The wafer 3 is diced using a diamond wheel to form chips 7 of a predetermined size.
【００２７】（ｇ）ダイボンド工程に移る。(G) Move to the die bonding step.
【００２８】本発明に用いるウエハー３表面の保護・補
強用テープ２の目的は、 研磨時のウエハー表面保護
と、 研磨後からウエハー３裏面をダイシング用テー
プ４に貼り付けるまでのウエハー３の補強である。The purpose of the protective / reinforcing tape 2 on the surface of the wafer 3 used in the present invention is to protect the wafer surface during polishing and to reinforce the wafer 3 from after polishing until the back surface of the wafer 3 is attached to the dicing tape 4. is there.
【００２９】従来は、上記だけの目的で保護用テープ
を用いていたが、本発明のウエハー補強効果を最大限に
引き出すにはベースフィルムの合成を高める必要があ
る。フィルムの合成は、弾性率と厚みが大きくなるほど
高くなるので、ウエハー裏面研磨厚精度、テープ剥離性
に影響を及ぼさない範囲で弾性率を高く、厚膜化するこ
とが望ましい。Conventionally, the protective tape has been used only for the above purpose, but it is necessary to enhance the synthesis of the base film in order to maximize the wafer reinforcing effect of the present invention. Since the film synthesis increases as the elastic modulus and thickness increase, it is desirable to increase the elastic modulus within a range that does not affect the wafer back surface polishing thickness accuracy and tape peeling property, and to increase the film thickness.
【００３０】そこで、本発明では、従来の１４０μｍ厚
さのＥＶＡ（弾性率３５０ｋｇ／ｃｍ2 ）の代わりに、
例えば、５００μｍ厚さのＰＥＴ（ポリエチレンテレフ
タレート弾性率１，０００ｋｇ／ｃｍ2 ）をベースフィ
ルムとして用いることにより、補強効果をより高めるこ
とができる。接着剤については、従来と同様なもので対
応できる。Therefore, in the present invention, instead of the conventional EVA (elastic modulus 350 kg / cm 2 ) having a thickness of 140 μm,
For example, by using PET (polyethylene terephthalate elastic modulus of 1,000 kg / cm 2 ) having a thickness of 500 μm as the base film, the reinforcing effect can be further enhanced. The adhesive may be the same as the conventional one.
【００３１】次に、本発明では、ウエハー３裏面をダイ
シング用テープ４に接着した状態で、ウエハー３表面に
添付した保護・補強用テープ２を剥離するが、この場
合、ウエハー３裏面をダイシング用テープ４を介して真
空吸着固定し、保護・補強用テープ２裏面とウエハー３
表面の接着力よりも、保護・補強用テープ２表面との接
着力が大きい剥離用テープ９を用いて引き剥がす。この
時点での各テープの接着力は、次の関係を有していなく
てはならない。Next, in the present invention, the protection / reinforcement tape 2 attached to the front surface of the wafer 3 is peeled off with the back surface of the wafer 3 adhered to the dicing tape 4. In this case, the back surface of the wafer 3 is used for dicing. Vacuum adsorption and fixing via tape 4, backside of protection / reinforcement tape 2 and wafer 3
The peeling tape 9 having a larger adhesion to the surface of the protection / reinforcement tape 2 than the adhesion to the surface is used for peeling. The adhesive strength of each tape at this point must have the following relationship.
【００３２】［剥離用テープ９と保護・補強用テープ２
表面の接着力］＞［保護・補強用テープ２裏面とウエハ
ー３表面の接着力］ ［ウエハー３裏面とダイシング用テープ４の接着力］＞
［保護・補強用テープ２裏面とウエハー３表面の接着
力］ 例えば、シリコンウエハーとのピール接着力（２０ｍｍ
長さの剥離に必要な力）において、 ［剥離用テープ９と保護・補強用テープ２表面の接着
力］が ２０００ｇ ［保護・補強用テープ２裏面とウエハー３表面の接着
力］が ７５ｇ ［ウエハー３裏面とダイシング用テープ４の接着力］が
１００ｇ の関係にあるテープを用いることで、本発明の実施が可
能である。[Peeling tape 9 and protective / reinforcing tape 2
Adhesive force on the surface]> [Adhesive force between the back surface of the protective / reinforcing tape 2 and the front surface of the wafer 3] [Adhesive force between the rear surface of the wafer 3 and the dicing tape 4]>
[Adhesive force between the back surface of the protective / reinforcing tape 2 and the front surface of the wafer 3] For example, the peel adhesive force with a silicon wafer (20 mm
[Adhesive force between the peeling tape 9 and the surface of the protective / reinforcing tape 2] is 2000 g [Adhesive force between the rear surface of the protective / reinforcing tape 2 and the surface of the wafer 3] is 75 g 3 Adhesive force between the back surface and the dicing tape 4] is 100 g, the present invention can be carried out.
【００３３】実施例２ この実施例は実施例１に対してウエハー３表面の保護・
補強用テープ２の剥離工程において紫外線照射による接
着剤硬化により接着性を低下させ、剥離時にウエハー３
に与えるストレスを低下させる方法について説明する。Example 2 This example is different from Example 1 in that the surface of the wafer 3 is protected.
In the peeling process of the reinforcing tape 2, the adhesiveness is lowered by curing the adhesive by ultraviolet irradiation, and the wafer 3 is peeled at the time of peeling
The method of reducing the stress given to is explained.
【００３４】図３及び図４にウエハーの加工工程のプロ
セスフローチャートとそれに伴うウエハーの加工状態を
示す。FIG. 3 and FIG. 4 show a process flowchart of a wafer processing step and a wafer processing state associated therewith.
【００３５】（ｔ）裏面の研磨前の８インチ径ウエハー
１（ウエハー厚：７２５μｍ）の状態でウエハーテスト
を実施する。(T) A wafer test is carried out in the state of an 8-inch diameter wafer 1 (wafer thickness: 725 μm) before polishing the back surface.
【００３６】（ａ）裏面の研磨前のウエハー１表面に、
保護・補強用テープ２を貼り付ける。この場合の保護・
補強用テープ２の接着剤は、紫外線照射により硬化反応
が起こり接着性が低下するタイプ、例えば、アクリル系
接着剤（ＵＶ反応架橋剤）である。(A) On the front surface of the wafer 1 before polishing the back surface,
Attach the protection / reinforcement tape 2. Protection in this case
The adhesive of the reinforcing tape 2 is of a type in which a curing reaction occurs due to ultraviolet irradiation and the adhesiveness is lowered, for example, an acrylic adhesive (UV reactive crosslinking agent).
【００３７】（ｂ）ウエハー１裏面を約５２５μｍ研磨
し（ウエハー厚：２００μｍ）、研磨完了後に、最終ウ
エハー厚（２００μｍ）のウエハー３表面に保護・補強
用テープ２を貼り付けたままでウエハー３をダイシング
工程へ搬送し、 （ｃ）保護・補強用テープ２を貼り付けた状態の研磨後
のウエハー３裏面を金属キャリアフレーム５を介してダ
イシング用テープ４に貼り付ける。(B) The back surface of the wafer 1 is polished by about 525 μm (wafer thickness: 200 μm), and after the completion of polishing, the wafer 3 having the final wafer thickness (200 μm) on which the protective / reinforcing tape 2 is attached is attached to the wafer 3. The wafer 3 is conveyed to a dicing step, and (c) the back surface of the wafer 3 after polishing with the protection / reinforcement tape 2 attached is attached to the dicing tape 4 via the metal carrier frame 5.
【００３８】（ｄ）ウエハー３表面側から強度２００〜
３００ｍＪ／ｃｍ2 の紫外線を２〜３ｓｅｃ照射して接
着力を低下させる。その後、剥離用テープ９を用いて引
きはがす。(D) Strength of the wafer 3 from the surface side of 200 to
The adhesive force is reduced by irradiating with ultraviolet rays of 300 mJ / cm 2 for 2 to 3 seconds. After that, the tape for peeling 9 is used for peeling.
【００３９】（ｅ）純水による超音波洗浄によりウエハ
ー３表面の接着剤の残りを洗い落とす。(E) The remaining adhesive on the surface of the wafer 3 is washed off by ultrasonic cleaning with pure water.
【００４０】（ｆ）ダイヤモンドホイールを用いてウエ
ハー３をダイシングし、所定のサイズのチップ７を形成
する。(F) The wafer 3 is diced using a diamond wheel to form chips 7 of a predetermined size.
【００４１】（ｇ）ダイボンド工程に移る。(G) Move to the die bonding step.
【００４２】実施例３ この実施例は最終ウエハー厚（この場合、２００μｍ
厚）まで研磨する前にウエハーテストを実施する場合の
製造方法について説明する。これはウエハーテスト時に
ウエハーのバルク電位を測定回路に組み込む必要がある
場合に用いる製造方法に関する。Example 3 This example shows the final wafer thickness (200 μm in this case).
A manufacturing method in the case of performing a wafer test before polishing to a thickness) will be described. This relates to a manufacturing method used when it is necessary to incorporate the bulk potential of a wafer into a measurement circuit during a wafer test.
【００４３】また、ウエハー３表面の保護・補強用テー
プ２剥離後の純水洗浄をダイシング後の洗浄工程で兼用
する方法について説明する。A method will be described in which the pure water cleaning after the protection / reinforcement tape 2 is peeled off from the surface of the wafer 3 is also used in the cleaning step after dicing.
【００４４】図５及び図６にウエハーの加工工程のプロ
セスフローチャートとそれに伴うウエハーの加工状態を
示す。FIG. 5 and FIG. 6 show a process flow chart of a wafer processing step and a wafer processing state accompanying it.
【００４５】（ａ）８インチ径ウエハー１（ウエハー
厚：７２５μｍ）の表面に、実施例１と同じ保護・補強
用テープ２を貼り付ける。(A) The same protective / reinforcing tape 2 as in Example 1 is attached to the surface of an 8-inch diameter wafer 1 (wafer thickness: 725 μm).
【００４６】（ｂ）ウエハー１裏面を約５０μｍ研磨す
る（ウエハー厚：６７５μｍ）。(B) The back surface of the wafer 1 is polished by about 50 μm (wafer thickness: 675 μm).
【００４７】（ｄ）実施例１と同じ剥離用テープ９を用
いて、６７５μｍ厚の一次研磨後のウエハー８（以下
「ウエハー８」とする。）から保護・補強用テープ２を
剥離する。(D) Using the same peeling tape 9 as in Example 1, the protective / reinforcing tape 2 is peeled off from the wafer 8 (hereinafter referred to as "wafer 8") after primary polishing having a thickness of 675 μm.
【００４８】（ｅ）純水超音波洗浄を行う。(E) Ultrasonic cleaning with pure water is performed.
【００４９】（ｔ）ウエハーテストを行う。(T) A wafer test is conducted.
【００５０】（ａ）再度、ウエハー８に保護・補強用テ
ープ２を貼り付ける。(A) Again, the protective / reinforcing tape 2 is attached to the wafer 8.
【００５１】（ｂ）ウエハー８裏面を約４７５μｍ研磨
し（ウエハー厚：２００μｍ）、研磨完了後に、最終ウ
エハー厚（２００μｍ）のウエハー３表面に保護・補強
用テープ２を貼り付けたままでウエハー３をダイシング
工程へ搬送し、 （ｃ）保護・補強用テープ２を貼り付けた状態の研磨後
のウエハー３裏面を金属キャリアフレーム５を介してダ
イシング用テープ４に貼り付ける。(B) The back surface of the wafer 8 is polished by about 475 μm (wafer thickness: 200 μm), and after the polishing is completed, the wafer 3 is attached to the front surface of the wafer 3 having the final wafer thickness (200 μm) with the protective / reinforcing tape 2 attached. The wafer is conveyed to a dicing step, and (c) the back surface of the wafer 3 after polishing with the protection / reinforcement tape 2 attached is attached to the dicing tape 4 via the metal carrier frame 5.
【００５２】（ｄ）実施例１と同じ剥離用テープ９を用
いて保護・補強用テープ２を引きはがす。(D) The protective / reinforcing tape 2 is peeled off using the same peeling tape 9 as in Example 1.
【００５３】（ｆ）ダイヤモンドホイールを用いてウエ
ハー３をダイシングし、所定のサイズのチップ７を形成
し、その後の純水洗浄でダイシングのシリコン切屑と一
緒にウエハー３表面の保護・補強用テープ２の接着剤残
渣を除去する。(F) The wafer 3 is diced by using a diamond wheel to form chips 7 of a predetermined size, and the subsequent cleaning with pure water together with the silicon chips for dicing protects and reinforces the tape 2 on the surface of the wafer 3. Remove the adhesive residue from.
【００５４】（ｇ）ダイボンド工程に移る。(G) Move to the die bonding step.
【００５５】実施例４ この実施例はウエハーテストをウエハー裏面の研磨完了
後ダイシング用テープ４に貼付し、保護・補強用テープ
２を剥離した状態で実施する製造方法について説明す
る。Example 4 This example describes a manufacturing method in which the wafer test is applied to the dicing tape 4 after completion of polishing of the back surface of the wafer, and the protective / reinforcing tape 2 is peeled off.
【００５６】この方法は最終ウエハー厚まで研磨した状
態でウエハーテストできるのでウエハー３に加わるスト
レス等を考慮するとフローチャート上では最も好ましい
と言える。This method can be said to be the most preferable in the flow chart in consideration of the stress applied to the wafer 3 since the wafer test can be performed in the state where the wafer is polished to the final wafer thickness.
【００５７】図７及び図８にウエハーの加工工程のプロ
セスフローチャートとそれに伴うウエハーの加工状態を
示す。FIG. 7 and FIG. 8 show a process flowchart of a wafer processing step and a wafer processing state associated therewith.
【００５８】（ａ）裏面の研磨前の８インチ径ウエハー
１（ウエハー厚：７２５μｍ）表面に、実施例１と同じ
保護・補強用テープ２を貼り付ける。(A) The same protective / reinforcing tape 2 as in Example 1 is attached to the front surface of an 8-inch diameter wafer 1 (wafer thickness: 725 μm) before polishing the back surface.
【００５９】（ｂ）ウエハー１裏面を約５２５μｍ研磨
し（ウエハー厚：２００μｍ）、研磨完了後に、最終ウ
エハー厚（２００μｍ）のウエハー３表面に保護・補強
用テープ２を貼り付けたままでウエハー３をダイシング
工程へ搬送し、 （ｃ）保護・補強用テープ２を貼り付けた状態でウエハ
ー３裏面を金属キャリアフレーム５を介してダイシング
用テープ４に貼り付ける。(B) The back surface of the wafer 1 is polished by about 525 μm (wafer thickness: 200 μm), and after the completion of polishing, the wafer 3 having the final wafer thickness (200 μm) on which the protective / reinforcing tape 2 is attached is attached to the wafer 3. The wafer 3 is conveyed to the dicing step, and (c) the back surface of the wafer 3 is attached to the dicing tape 4 via the metal carrier frame 5 with the protection / reinforcement tape 2 attached.
【００６０】（ｄ）実施例１と同じ剥離用テープ９を用
いて保護・補強用テープ２を引きはがす。(D) The protective / reinforcing tape 2 is peeled off using the same peeling tape 9 as in the first embodiment.
【００６１】（ｅ）純水による超音波洗浄によりウエハ
ー３表面の接着剤の残りを洗い落とす。(E) The remainder of the adhesive on the surface of the wafer 3 is washed off by ultrasonic cleaning with pure water.
【００６２】（ｔ）ウエハーテストを実施する。(T) A wafer test is carried out.
【００６３】（ｆ）ダイヤモンドホイールを用いてウエ
ハー３をダイシングし、所定のサイズのチップ７を形成
する。(F) The wafer 3 is diced using a diamond wheel to form chips 7 of a predetermined size.
【００６４】（ｇ）ダイボンド工程に移る。(G) Move to the die bonding step.
【００６５】[0065]
【発明の効果】以上説明したように、本発明はウエハー
裏面の研磨完了後、最終ウエハー厚（２００μｍ）のウ
エハー表面に保護・補強用テープを貼り付けたままで次
工程であるダイシング工程へ搬送し、このウエハー裏面
にダイシング用テープを貼り付けた後、剥離用テープを
用いて保護・補強用テープを剥離して、ダイシングされ
る。この結果、ウエハー研磨後もウエハーはいつも保護
・補強用テープ又はダインシング用テープのいずれかに
よって補強されているので、ウエハーハンドリングや搬
送中にウエハーの割れることがない安定した製造方法を
得ることができる。As described above, according to the present invention, after completion of polishing of the back surface of the wafer, the wafer having the final wafer thickness (200 μm) is transferred to the dicing step which is the next step with the protective / reinforcing tape attached. After the dicing tape is attached to the back surface of the wafer, the protection / reinforcement tape is peeled off by using the peeling tape and dicing is performed. As a result, since the wafer is always reinforced by either the protective / reinforcing tape or the dicing tape even after the wafer is polished, it is possible to obtain a stable manufacturing method in which the wafer is not cracked during wafer handling or transportation. .
【００６６】さらに加えて、従来ウエハー研磨後に実施
していたウエハーテストを、（１）最終ウエハー厚（２
００μｍ）まで研磨する前に、又は（２）ウエハー裏面
の研磨完了後ダイシング用テープに貼り付け、その後、
保護・補強用テープを剥離した状態で実施するため、ウ
エハーテスト工程でのウエハー破損も防止することがで
きる。In addition, the wafer test which was conventionally performed after polishing the wafer was performed as follows: (1) Final wafer thickness (2
Before polishing to 100 μm) or (2) after completion of polishing of the back surface of the wafer, affixing to a dicing tape, and then
Since the protection / reinforcement tape is peeled off, the wafer can be prevented from being damaged in the wafer test process.
【００６７】以上のことにより、パッケージ厚０．５ｍ
ｍ以下の半導体装置の製造工程の歩留りを向上させるこ
とできる。As a result of the above, the package thickness is 0.5 m.
It is possible to improve the yield of the semiconductor device manufacturing process of m or less.
【図１】本発明の実施例１のウエハー裏面の研磨からダ
イシング工程までのプロセスフローチャートである。FIG. 1 is a process flowchart from polishing of a back surface of a wafer to a dicing process according to a first embodiment of the present invention.
【図２】本発明の実施例１のウエハー裏面の研磨からダ
イシング工程に伴うウエハーの加工状態の断面図であ
る。FIG. 2 is a cross-sectional view of the processed state of the wafer in the processes from polishing the back surface of the wafer to dicing in Example 1 of the present invention.
【図３】本発明の実施例２のウエハー裏面の研磨からダ
イシング工程までのプロセスフローチャートである。FIG. 3 is a process flow chart from polishing of the back surface of a wafer to dicing in Example 2 of the present invention.
【図４】本発明の実施例２のウエハー裏面の研磨からダ
イシング工程に伴うウエハーの加工状態の断面図であ
る。FIG. 4 is a cross-sectional view of a processed state of the wafer in the processes from polishing of the back surface of the wafer to dicing in Example 2 of the present invention.
【図５】本発明の実施例３のウエハー裏面の研磨からダ
イシング工程までのプロセスフローチャートである。FIG. 5 is a process flowchart from polishing of the back surface of a wafer to dicing in Example 3 of the present invention.
【図６】本発明の実施例３のウエハー裏面の研磨からダ
イシング工程に伴うウエハーの加工状態の断面図であ
る。FIG. 6 is a cross-sectional view of a processed state of the wafer in the steps from polishing the back surface of the wafer to dicing in Example 3 of the present invention.
【図７】本発明の実施例４のウエハー裏面の研磨からダ
イシング工程までのプロセスフローチャートである。FIG. 7 is a process flowchart from polishing of the back surface of a wafer to dicing in Example 4 of the present invention.
【図８】本発明の実施例４のウエハー裏面の研磨からダ
イシング工程に伴うウエハーの加工状態の断面図であ
る。FIG. 8 is a cross-sectional view of the processed state of the wafer in the steps from polishing the back surface of the wafer to dicing in Example 4 of the present invention.
【図９】従来のウエハー裏面の研磨からダイシング工程
までのプロセスフローチャートである。FIG. 9 is a process flow chart from a conventional wafer back surface polishing to a dicing process.
【図１０】従来のウエハー裏面の研磨からダイシング工
程までのプロセスフローチャートに伴うウエハーの加工
状態の断面図である。FIG. 10 is a cross-sectional view of a processed state of a wafer according to a process flowchart from a conventional wafer back surface polishing to a dicing process.
【図１１】パッケージの薄型化と高密度化の関係の説明
図である。FIG. 11 is an explanatory diagram of a relationship between thinning and high density of the package.
１ 研磨前のウエハー ２ 保護・補強用テープ ３ 最終厚まで研磨後のウエハー ４ ダイシング用テープ ５ 金属製キャリアフレーム ７ チップ ８ １次研磨後のウエハー ９ 剥離用テープ 1 Wafer before polishing 2 Protection / reinforcement tape 3 Wafer after polishing to final thickness 4 Dicing tape 5 Metal carrier frame 7 Chip 8 Wafer after primary polishing 9 Stripping tape
Claims (6)
護・補強用テープを貼り付け、上記ウエハーの裏面研磨
を行い、上記保護・補強用テープを上記ウエハーの表面
に張り付けた状態で、最終ウエハー厚になった上記ウエ
ハーを搬送し、上記ウエハーの裏面をダイシング用テー
プに貼り付けた後、上記保護・補強用テープを剥離し、
ダイシングすることを特徴とする、半導体装置の製造方
法。1. A final step in a state where a protective / reinforcing tape is attached to the surface of a wafer on which a circuit is formed, the back surface of the wafer is polished, and the protective / reinforcing tape is attached to the front surface of the wafer. The wafer having a wafer thickness is conveyed, the back surface of the wafer is attached to a dicing tape, and then the protection / reinforcement tape is peeled off,
A method of manufacturing a semiconductor device, which comprises dicing.
まで、上記ウエハーの裏面研磨を行うことを特徴とす
る、請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the back surface of the wafer is polished until the final wafer thickness becomes 200 μm or less.
と反対側の表面に、紫外線を照射することにより、該保
護・補強用テープの接着強度を低下させた後、上記保護
・補強用テープを剥離することを特徴とする、請求項１
記載の半導体装置の製造方法。3. A protective / reinforcing tape, which has a surface opposite to an adhesive-coated surface, is irradiated with ultraviolet rays to reduce the adhesive strength of the protective / reinforcing tape. The tape is peeled off, Claim 1 characterized by the above-mentioned.
A method for manufacturing a semiconductor device as described above.
エハーの表面と上記保護・補強用テープとの接着力より
大きい上記ダイシング用テープに、上記ウエハーの裏面
を張り付け、上記保護・補強用テープの表面との接着力
が、上記ウエハーの表面と上記保護・補強用テープとの
接着力より大きい剥離用テープを、上記保護・補強用テ
ープの表面に張り付け、上記剥離用テープを剥離するこ
とにより、上記保護・補強用テープを剥離することを特
徴とする、請求項１記載の半導体装置の製造方法。4. The protective / reinforcing tape, wherein the rear surface of the wafer is attached to the dicing tape, the adhesive strength of which is higher than that of the front surface of the wafer and the protective / reinforcing tape. By attaching a peeling tape whose adhesive strength to the surface of the wafer is larger than the adhesive strength between the surface of the wafer and the protective / reinforcing tape to the surface of the protective / reinforcing tape, and peeling the peeling tape. The method for manufacturing a semiconductor device according to claim 1, wherein the protective / reinforcing tape is peeled off.
するまでに行うことを特徴とする、請求項１記載の半導
体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer test is performed before polishing to a final wafer thickness.
に貼り付け、上記保護・補強用テープを剥離した後、ウ
エハーテストを行うことを特徴とする、請求項１記載の
半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer is attached to the dicing tape, the protective / reinforcing tape is peeled off, and then a wafer test is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14339393A JPH0722358A (en) | 1993-06-15 | 1993-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14339393A JPH0722358A (en) | 1993-06-15 | 1993-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0722358A true JPH0722358A (en) | 1995-01-24 |
Family
ID=15337724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14339393A Pending JPH0722358A (en) | 1993-06-15 | 1993-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722358A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997008745A1 (en) * | 1995-08-31 | 1997-03-06 | Nitto Denko Corporation | Method and apparatus for peeling protective adhesive tape from semiconductor wafer |
| JPH09148280A (en) * | 1995-11-08 | 1997-06-06 | Samsung Electron Co Ltd | Manufacture of semiconductor element in which rear surface of wafer is polished by uv oversensitive tape |
| KR19990017672A (en) * | 1997-08-25 | 1999-03-15 | 윤종용 | Semiconductor chip package manufacturing method |
| EP1026725A2 (en) * | 1999-02-05 | 2000-08-09 | Sharp Kabushiki Kaisha | Manufacturing method for a semiconductor device |
| US6297131B1 (en) | 1999-04-22 | 2001-10-02 | Fujitsu Limited | Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer |
| US6425971B1 (en) * | 2000-05-10 | 2002-07-30 | Silverbrook Research Pty Ltd | Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes |
| WO2003060972A1 (en) * | 2002-01-15 | 2003-07-24 | Sekisui Chemical Co., Ltd. | Ic chip manufacturing method |
| WO2003063219A1 (en) * | 2002-01-25 | 2003-07-31 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electronic component |
| JP2003332267A (en) * | 2002-05-09 | 2003-11-21 | Lintec Corp | Method for working semiconductor wafer |
| JP2005039114A (en) * | 2003-07-17 | 2005-02-10 | Disco Abrasive Syst Ltd | Semiconductor wafer shifting device |
| JPWO2003085714A1 (en) * | 2002-04-11 | 2005-08-18 | 積水化学工業株式会社 | Manufacturing method of semiconductor chip |
| US6982184B2 (en) | 2001-05-02 | 2006-01-03 | Silverbrook Research Pty Ltd | Method of fabricating MEMS devices on a silicon wafer |
| US7122447B2 (en) | 2002-10-25 | 2006-10-17 | Renesas Technology Corp. | Fabrication method of semiconductor circuit device |
| WO2010038717A1 (en) * | 2008-09-30 | 2010-04-08 | パナソニック電工株式会社 | Method for manufacturing functional device, and method for manufacturing semiconductor device provided with functional device |
| JP2012114265A (en) * | 2010-11-25 | 2012-06-14 | Shin Etsu Polymer Co Ltd | Semiconductor wafer holder and semiconductor wafer handling method |
| JP2015098565A (en) * | 2013-11-20 | 2015-05-28 | 東京応化工業株式会社 | Processing method |
-
1993
- 1993-06-15 JP JP14339393A patent/JPH0722358A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997008745A1 (en) * | 1995-08-31 | 1997-03-06 | Nitto Denko Corporation | Method and apparatus for peeling protective adhesive tape from semiconductor wafer |
| JPH09148280A (en) * | 1995-11-08 | 1997-06-06 | Samsung Electron Co Ltd | Manufacture of semiconductor element in which rear surface of wafer is polished by uv oversensitive tape |
| KR19990017672A (en) * | 1997-08-25 | 1999-03-15 | 윤종용 | Semiconductor chip package manufacturing method |
| EP1026725A2 (en) * | 1999-02-05 | 2000-08-09 | Sharp Kabushiki Kaisha | Manufacturing method for a semiconductor device |
| US6730579B1 (en) | 1999-02-05 | 2004-05-04 | Sharp Kabushiki Kaisha | Method of manufacturing a semiconductor dice by partially dicing the substrate and subsequent chemical etching |
| US6297131B1 (en) | 1999-04-22 | 2001-10-02 | Fujitsu Limited | Semiconductor device manufacturing method for grinding and dicing a wafer from a back side of the wafer |
| US6846692B2 (en) | 2000-05-10 | 2005-01-25 | Silverbrook Research Pty Ltd. | Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes |
| US6425971B1 (en) * | 2000-05-10 | 2002-07-30 | Silverbrook Research Pty Ltd | Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes |
| US7285437B2 (en) | 2001-05-02 | 2007-10-23 | Silverbrook Research Pty Ltd | Method of separating MEMS devices from a composite structure |
| US6982184B2 (en) | 2001-05-02 | 2006-01-03 | Silverbrook Research Pty Ltd | Method of fabricating MEMS devices on a silicon wafer |
| WO2003060972A1 (en) * | 2002-01-15 | 2003-07-24 | Sekisui Chemical Co., Ltd. | Ic chip manufacturing method |
| CN1322554C (en) * | 2002-01-15 | 2007-06-20 | 积水化学工业株式会社 | Method for producing IC chip |
| US6939741B2 (en) | 2002-01-15 | 2005-09-06 | Sekisui Chemical Co., Ltd. | IC chip manufacturing method |
| US6984572B2 (en) | 2002-01-25 | 2006-01-10 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electronic component |
| WO2003063219A1 (en) * | 2002-01-25 | 2003-07-31 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electronic component |
| JPWO2003085714A1 (en) * | 2002-04-11 | 2005-08-18 | 積水化学工業株式会社 | Manufacturing method of semiconductor chip |
| JP4791693B2 (en) * | 2002-04-11 | 2011-10-12 | 積水化学工業株式会社 | Manufacturing method of semiconductor chip |
| JP2003332267A (en) * | 2002-05-09 | 2003-11-21 | Lintec Corp | Method for working semiconductor wafer |
| US7122447B2 (en) | 2002-10-25 | 2006-10-17 | Renesas Technology Corp. | Fabrication method of semiconductor circuit device |
| US7968428B2 (en) | 2002-10-25 | 2011-06-28 | Renesas Electronics Corporation | Fabrication method of semiconductor circuit device |
| JP2005039114A (en) * | 2003-07-17 | 2005-02-10 | Disco Abrasive Syst Ltd | Semiconductor wafer shifting device |
| WO2010038717A1 (en) * | 2008-09-30 | 2010-04-08 | パナソニック電工株式会社 | Method for manufacturing functional device, and method for manufacturing semiconductor device provided with functional device |
| JP2010087280A (en) * | 2008-09-30 | 2010-04-15 | Panasonic Electric Works Co Ltd | Manufacturing method of functional device and manufacturing method of semiconductor device, which uses functional device manufactured by the same |
| JP2012114265A (en) * | 2010-11-25 | 2012-06-14 | Shin Etsu Polymer Co Ltd | Semiconductor wafer holder and semiconductor wafer handling method |
| JP2015098565A (en) * | 2013-11-20 | 2015-05-28 | 東京応化工業株式会社 | Processing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5476566A (en) | Method for thinning a semiconductor wafer | |
| JPH0722358A (en) | Manufacture of semiconductor device | |
| KR100468748B1 (en) | Dicing tape mounter applicable a pre-cut dicing tape and general dicing tape and In-line system having the dicing tape mounter | |
| JP4762671B2 (en) | Dicing tape and semiconductor wafer dicing method | |
| JP3485525B2 (en) | Method for manufacturing semiconductor device | |
| AU729849B2 (en) | Methods of processing semiconductor wafer and producing IC card, and carrier | |
| US7968428B2 (en) | Fabrication method of semiconductor circuit device | |
| JP4392732B2 (en) | Manufacturing method of semiconductor chip | |
| JP2001044144A (en) | Semiconductor chip manufacturing process | |
| JP2001156027A (en) | Method of manufacturing semiconductor device | |
| US20040203188A1 (en) | Method and apparatus for forming thin microelectronic dies | |
| JP4312419B2 (en) | Semiconductor wafer processing method | |
| JP2000306875A (en) | Manufacture of semiconductor device | |
| JP2000129227A (en) | Semiconductor wafer protective pressure-sensitive adhesive sheet and use thereof | |
| JP2003209160A (en) | Method for manufacturing semiconductor device using semiconductor wafer | |
| KR102155028B1 (en) | Mask-integrated surface protection tape | |
| JP2005109433A (en) | Method for abrading semiconductor wafer and protecting member of bump for abrading | |
| JP2006342330A (en) | Pressure-sensitive adhesive sheet for dicing and method for dicing using the same | |
| JP2004146761A (en) | Protective structure for semiconductor wafer, protective method for semiconductor wafer, lamination protecting sheet used for the same, and method for processing semiconductor wafer | |
| JP2003197567A (en) | Method of manufacturing semiconductor device | |
| JP2005019435A (en) | Method of polishing wafer | |
| JP4614700B2 (en) | Wafer dicing method, semiconductor device and manufacturing method thereof, circuit board, and electronic equipment | |
| JPH1174230A (en) | Manufacture of thin-film semiconductor device | |
| JP2001060591A (en) | Manufacture of semiconductor device | |
| JPH06302572A (en) | Manufacture of semiconductor device and tape adhering and peeling apparatus |