JPH07221112A - Manufacture of semiconductor wafer - Google Patents

Abstract

PURPOSE:To obtain an Si wafer which is very reliable near the surface of the wafer since it has a non-defect layer near the surface of the wafer and to increase the characteristics of the device such as a gate withstand strength by depositing an a-Si (amorphous silicon) layer in a specified thickness at a specified temperature on the rear face of the Si wafer. CONSTITUTION:First, an Si wafer 1 is prepared. Nextly, due to thermal decomposition of silane (SiH4), an a-Si layer 2 is formed in the thickness of about 1mum at 570-580 deg.C on the rear face of the Si wafer 1 which is a second primary face. When the wafer 1 is heat-treated, crystal defects and an oxygen deposit 6, which exist in the wafer 1, absorb impurities (a gettering action) or extinguish crystal defects due to a grain boundary generated near an interface between the wafer 1 and the a-Si layer 2, a stress of the interface such as crystallization, and a distortion field of dislocation which accompanies the stress of the interface, since the a-Si layer 2 exists on the rear face of the wafer 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing, and more particularly to a crystal manufacturing process.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, when an oxide film (SiO ₂ ) is formed on the surface of a Si (silicon) wafer by thermal oxidation, impurities, precipitates of oxygen and crystal defects are generated near the surface of the Si wafer. There was a drawback that occurred. Therefore, the presence of these affects the quality of the oxide film and causes deterioration of the gate breakdown voltage of the semiconductor device.

A method for solving the above problem is disclosed in Japanese Patent Application Laid-Open No. 52-69571. That is,
Technology to remove impurities near the Si wafer surface by forming a Poly-Si layer on the back surface of the Si wafer and utilizing the stress between the Si substrate and the Poly-Si layer interface, grain boundaries of the film, strain fields such as dislocations ( Gettering technology) is known.

[0004]

However, as described above, Poly-Si is deposited on the back surface of the Si wafer to getter impurities, but in order to enhance the gettering ability, the Poly-Si film Although it is possible to increase the thickness, conversely, the heat treatment in the deposition step increases the amount of oxygen precipitation inside the Si wafer,
Precipitates and defects easily exist near the surface of the Si wafer, which may affect the device characteristics.

That is, an object of the present invention is to provide a defect-free Si wafer having a higher reliability in the vicinity of the wafer surface while solving the above-mentioned problems and to improve device characteristics such as gate breakdown voltage. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a-Si is formed on the back surface of the Si wafer.
(Amorphous silicon) layer about 1 μm, 570-58
Characterized by deposition at 0 ° C.

[0009]

According to the above-mentioned means, the heat treatment during the semiconductor device manufacturing process causes a change in the shape of a-Si on the back surface of the wafer, generation of grain boundaries, crystallization, and a strain field such as dislocation accompanying it. Impurities, dislocations, and oxygen precipitates collect on the back surface side, and a high gettering effect is obtained.
As a result, a defect-free layer near the surface of the Si wafer,
The gate breakdown voltage is improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on specific embodiments with reference to the drawings.

1 to 3 are sectional views of a wafer showing the outline of the present invention, and FIG.
It is the figure which formed the OS type transistor.

First, the Si wafer 1 shown in FIG. 1 is prepared. Then, as shown in FIG. 2, the a-Si layer 2 is deposited on the back surface, which is the second main surface of the Si wafer 1, by about 1 μm at a temperature of 570 to 580 ° C. by deposition by thermal decomposition of silane (SiH ₄ ). Form. The temperature range is the temperature at which a-Si is produced, and when the temperature is higher than this, Poly-Si is formed.

FIG. 3 is a semiconductor device manufacturing process step in which the wafer 1 is subjected to a heat treatment (for example, an oxide film (SiO 2 is formed on the surface of the first main surface facing the second main surface of the wafer 1 where a semiconductor element is formed). ₂ ) It is the figure which showed that it was formed.

In FIG. 3, since a-Si2 is present on the back surface of the wafer 1 during the heat treatment of the wafer 1, the crystal defects and oxygen precipitates 6 present in the wafer 1 are
The impurities are absorbed (gettering action) or crystal defects are eliminated by the grain boundary generated near the interface between the wafer 1 and the a-Si2, the stress at the interface such as crystallization, and the strain field of dislocation accompanying this.

Here, in order to improve the gettering effect which is the object of the present invention, a Poly-Si layer is formed on the back surface of the Si wafer 1 of the prior art (Polysilicon Back Coati).
ng crystal: hereinafter abbreviated as PBC crystal), the reason for forming the a-Si layer 2 will be described.

As described above, the gettering effect of the PBC crystal is considered to be due to the interface stress such as grain boundary, shape, and crystallization of Poly-Si during the heat treatment, and the strain field due to the dislocation accompanying it. Has been. In order to enhance the gettering effect of the PBC crystal, it is conceivable to increase the film thickness of Poly-Si, but the heat treatment in the deposition process affects oxygen precipitation inside the crystal and changes the bulk characteristics. There is a fear.

That is, when attention is paid to grain boundaries, shapes, crystallization, and dislocations associated therewith which are thought to bring about the gettering effect, a-Si has a larger effect than Poly-Si. In other words, a-Si is required to eliminate defects near the wafer surface.
Is more effective and the gate breakdown voltage is further improved. The formation temperature of a-Si is lower than that of Poly-Si,
The processing time is long, but the effect on bulk properties is small.

For the above reasons, a higher gettering effect is desired when the a-Si layer 2 is formed. Also, FIG.
As shown in FIG.
When the gate oxide film 10 of the OS type transistor is formed, the gate oxide film 10 has a good film quality, and thus the gate breakdown voltage is improved.

The invention made by the inventors of the present invention is not limited to the above-described embodiments, but various modifications can be made without departing from the scope of the invention.

[0020]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a formed on the back surface of the Si wafer
-Si undergoes heat treatment during the manufacturing process,
Impurities, minute defects, and oxygen precipitates in the wafer bulk collect on the back surface side due to the stress at the interface such as its shape, generation of grain boundaries, and crystallization, and the accompanying strain field of dislocations, and there are no defects near the wafer surface. Become a layer. As a result, the quality of the gate oxide film is improved, and improvement in device characteristics such as gate breakdown voltage can be expected.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a Si wafer.

FIG. 2 is a sectional view of a Si wafer showing an outline of the present invention.

FIG. 3 is a cross-sectional view of the Si wafer after the Si wafer shown in FIG. 2 has been subjected to heat treatment.

FIG. 4 is a sectional view showing a MOS transistor formed on the surface of a Si wafer according to the present invention.

[Explanation of symbols]

 1 ... Si wafer 2 ... a-Si 3 ... Crystal defects, oxygen precipitation nuclei 4 ... Defect-free layer 5 ... Oxide film 6 ... Crystal defects, oxygen Precipitate 7 ・ ・ ・ ・ Gate electrode 8 ・ ・ ・ ・ ・ ・ Source 9 ・ ・ ・ ・ Drain 10 ・ ・ ・ ・ Gate oxide film

Front Page Continuation (72) Inventor Norio Suzuki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (3)

[Claims] 1. A step of preparing a semiconductor wafer having a first main surface and a second main surface facing the first main surface, and a step of forming an amorphous silicon layer on the second main surface of the semiconductor wafer. A method of manufacturing a semiconductor device, comprising forming a semiconductor element region on the first main surface of the semiconductor wafer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a gate oxide film is formed by thermally oxidizing the first main surface, and a gate electrode is formed on the gate oxide film. . 3. The amorphous silicon layer formation is 57
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by deposition by thermal decomposition of silane at a temperature of 0 ° C to 580 ° C.