JPH07201985A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH07201985A
JPH07201985A JP33419093A JP33419093A JPH07201985A JP H07201985 A JPH07201985 A JP H07201985A JP 33419093 A JP33419093 A JP 33419093A JP 33419093 A JP33419093 A JP 33419093A JP H07201985 A JPH07201985 A JP H07201985A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor device
forming
manufacturing
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP33419093A
Other languages
Japanese (ja)
Other versions
JP3199942B2 (en
Inventor
Tadashi Matsunou
正 松能
Hideki Shibata
英毅 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP33419093A priority Critical patent/JP3199942B2/en
Publication of JPH07201985A publication Critical patent/JPH07201985A/en
Application granted granted Critical
Publication of JP3199942B2 publication Critical patent/JP3199942B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To avoid the fluctuation of an inter-wiring capacitance caused by the increase of a dielectric constant in a semiconductor device which has a plurality of insulating films having different dielectric constants are provided in layers between its upper and lower wiring layers. CONSTITUTION:A first insulating film 14 containing a number of Si-F bond groups and Si-OH bond groups is formed on an SiO2 insulating film 12 including a first metal wiring 13. Further, in a successive process, a second insulating film 15 containing Si-F bond groups less than the first insulating film 14 is formed on the first insulating film 14. Then the second insulating film 15 only is etched and levelled so as not to have the first insulating film 14 exposed from the surface. With this constitution, by protecting the first insulating film 14 from the atmosphere by the second insulating film 15, the increase of the dielectric constant of the first insulating film 14 caused by moisture absorption can be avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、たとえば多層配線構
造を有する半導体装置の製造方法に関するもので、特に
上下の配線層間に誘電率の異なる複数の絶縁膜を積層し
てなる半導体装置の製造に用いられるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having, for example, a multi-layer wiring structure, and more particularly, to manufacturing of a semiconductor device in which a plurality of insulating films having different dielectric constants are laminated between upper and lower wiring layers. Is used.

【0002】[0002]

【従来の技術】従来、多層配線構造を有する半導体装置
においては、配線間容量の低減を図るなどの目的で、上
下の配線層の相互間に誘電率の低い絶縁膜が設けられる
ようになっている。
2. Description of the Related Art Conventionally, in a semiconductor device having a multilayer wiring structure, an insulating film having a low dielectric constant has been provided between upper and lower wiring layers for the purpose of reducing the capacitance between wirings. There is.

【0003】図4は、従来の多層配線構造を有する半導
体装置の例を示すものである。たとえば、従来装置にお
いては、まず半導体基板1上に熱酸化によりSiO2絶
縁膜2を形成した後、下層配線としての第1の金属配線
3を形成する(同図(a))。
FIG. 4 shows an example of a conventional semiconductor device having a multilayer wiring structure. For example, in the conventional device, first, the SiO2 insulating film 2 is formed on the semiconductor substrate 1 by thermal oxidation, and then the first metal wiring 3 as the lower layer wiring is formed (FIG. 3A).

【0004】次いで、第1の金属配線3を含む上記Si
O2 絶縁膜2上に減圧プラズマ法により絶縁膜4を成膜
し、さらにその絶縁膜4の上に、Si−F結合基および
Si−OH結合基を多く含有する絶縁膜5を成膜する
(同図(b))。
Next, the Si containing the first metal wiring 3 is formed.
An insulating film 4 is formed on the O2 insulating film 2 by a low pressure plasma method, and further, an insulating film 5 containing a large amount of Si--F bond groups and Si--OH bond groups is formed on the insulating film 4 ( The same figure (b)).

【0005】そして、上記絶縁膜5の上面を、たとえば
ResistエッチバックRIE法やCMP法により平
坦化する(同図(c))。この後、平坦化された絶縁膜
5の上に、この絶縁膜5の吸湿を防止するための絶縁膜
6を減圧プラズマ法により成膜し、さらに上層配線とし
ての第2の金属配線などの形成が行われるようになって
いる(同図(d))。
Then, the upper surface of the insulating film 5 is flattened by, for example, the resist etch-back RIE method or the CMP method (FIG. 7C). After that, an insulating film 6 for preventing moisture absorption of the insulating film 5 is formed on the flattened insulating film 5 by a low pressure plasma method, and further a second metal wiring or the like as an upper wiring is formed. Is performed ((d) in the same figure).

【0006】しかしながら、上記した従来装置の場合、
Si−F結合基およびSi−OH結合基を多く含有する
絶縁膜5を表面に露出させた状態で、その平坦化を行う
ようになっている。
However, in the case of the above-mentioned conventional device,
The insulating film 5 containing a large amount of Si—F bond groups and Si—OH bond groups is planarized with the surface exposed.

【0007】通常、上記絶縁膜5は、Si−F結合基お
よびSi−OH結合基を多く含有することで、その誘電
率が低く抑えられるようになっている。このため、その
加工途中もしくは加工終了後においては、絶縁膜5は非
常に吸湿しやすく、膜中のSi−OH結合基ならびにH
−OH結合基の含有量を増加させる結果となる。
Usually, the insulating film 5 contains a large amount of Si--F bond groups and Si--OH bond groups, so that the dielectric constant thereof can be suppressed low. Therefore, during or after the processing, the insulating film 5 is very likely to absorb moisture, and the Si--OH bond group and H in the film are absorbed.
This results in an increased content of -OH linking groups.

【0008】これは、絶縁膜5の誘電率(ε)を増大さ
せる原因となることから、動作スピードを律速する配線
間容量や配線層間容量の増加を招くなど、特性を著しく
劣化させるという問題があった。
Since this causes the dielectric constant (ε) of the insulating film 5 to increase, there is a problem that characteristics are significantly deteriorated, such as an increase in inter-wiring capacitance and inter-wiring capacitance that control the operation speed. there were.

【0009】[0009]

【発明が解決しようとする課題】上記したように、従来
においては、Si−F結合基およびSi−OH結合基を
多く含有する絶縁膜は非常に吸湿しやすいため、その膜
を表面に露出させた状態で平坦化を行うと、膜中のSi
−OH結合基ならびにH−OH結合基の含有量が増加
し、結果として、誘電率の増大にともなって配線間容量
や配線層間容量が増加するなど、誘電率のばらつきによ
り特性が安定しないという欠点があった。
As described above, in the past, since an insulating film containing a large amount of Si-F bond groups and Si-OH bond groups is very likely to absorb moisture, the film is exposed to the surface. If flattening is performed in the
The content of the —OH bond group and the H—OH bond group increases, and as a result, the inter-wiring capacitance and the inter-wiring capacitance increase with an increase in the dielectric constant, resulting in unstable characteristics due to variations in the dielectric constant. was there.

【0010】そこで、この発明は、誘電率の増大にとも
なう配線間容量や配線層間容量の増加を防止でき、特性
を安定化させることが可能な半導体装置の製造方法を提
供することを目的としている。
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing an increase in inter-wiring capacitance and inter-wiring capacitance due to an increase in dielectric constant and stabilizing characteristics. .

【0011】[0011]

【課題を解決するための手段】上記の目的を達成するた
めに、この発明の半導体装置の製造方法にあっては、多
層構造とされた上下の配線層の相互間に誘電率の異なる
複数の絶縁膜を積層してなる場合において、前記下層側
の配線上に誘電率の低い第1の絶縁膜を形成する工程
と、この第1の絶縁膜の上面を外気にさらすことなく、
その上部に前記第1の絶縁膜よりも誘電率の高い第2の
絶縁膜を形成する工程と、この第2の絶縁膜を、前記第
1の絶縁膜を表面に露出させることなく平坦化する工程
とからなっている。
In order to achieve the above object, in the method of manufacturing a semiconductor device according to the present invention, a plurality of wiring layers having upper and lower wiring layers having different dielectric constants are formed. In the case of laminating insulating films, a step of forming a first insulating film having a low dielectric constant on the wiring on the lower layer side, and without exposing the upper surface of the first insulating film to the outside air,
A step of forming a second insulating film having a higher dielectric constant than the first insulating film on the upper part thereof, and planarizing the second insulating film without exposing the first insulating film to the surface. It consists of a process.

【0012】また、この発明の半導体装置の製造方法に
あっては、多層構造とされた上下の配線層の相互間に誘
電率の異なる複数の絶縁膜を積層してなる場合におい
て、前記下層側の配線上に、所定量のSi−F結合基お
よびSi−OH結合基を含有してなる第1の絶縁膜を形
成する工程と、この第1の絶縁膜の上面を外気にさらす
ことなく、その上部に前記第1の絶縁膜よりもSi−F
結合基およびSi−OH結合基の両方もしくは片方の含
有量が少ない第2の絶縁膜を形成する工程と、この第2
の絶縁膜を、前記第1の絶縁膜を表面に露出させること
なく平坦化する工程とからなっている。
Further, in the method for manufacturing a semiconductor device of the present invention, in the case where a plurality of insulating films having different dielectric constants are laminated between upper and lower wiring layers having a multilayer structure, the lower layer side Forming a first insulating film containing a predetermined amount of Si-F bonding group and Si-OH bonding group on the wiring of, and without exposing the upper surface of the first insulating film to the outside air, Si-F is formed on top of the first insulating film
Forming a second insulating film having a low content of both or one of the bonding group and the Si—OH bonding group; and
And the step of flattening the insulating film without exposing the first insulating film on the surface.

【0013】[0013]

【作用】この発明は、上記した手段により、Si−F結
合基およびSi−OH結合基を多く含有する第1の絶縁
膜の吸湿を阻止できるようになるため、配線層間の絶縁
膜の誘電率を安定に保つことが可能となるものである。
According to the present invention, since the first insulating film containing a large amount of Si-F bond groups and Si-OH bond groups can be prevented from absorbing moisture by the means described above, the dielectric constant of the insulating film between the wiring layers can be prevented. Can be kept stable.

【0014】[0014]

【実施例】以下、この発明の一実施例について図面を参
照して説明する。図1は、本発明にかかる半導体装置の
概略構成を示すものである。すなわち、この半導体装置
は、Si基板11上に形成されたSiO2 絶縁膜12、
このSiO2 膜12上に形成された第1の金属配線1
3、この第1の金属配線13を含む上記SiO2 膜12
上に形成された第1の絶縁膜14、この第1の絶縁膜1
4を表面に露出させることなく、その上面が平坦化され
てなる第2の絶縁膜15、この第2の絶縁膜15上に形
成された第2の金属配線16、この第2の金属配線16
と上記第1の金属配線13とを接続する接続孔(ヴィア
ホール)17、および上記第2の金属配線16を含む装
置主表面に形成されたパッシベーション膜18からなっ
ている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a semiconductor device according to the present invention. That is, this semiconductor device has the SiO2 insulating film 12 formed on the Si substrate 11,
First metal wiring 1 formed on this SiO2 film 12
3. The SiO2 film 12 including the first metal wiring 13
First insulating film 14 formed on the first insulating film 1
A second insulating film 15 whose upper surface is flattened without exposing 4 to the surface, a second metal wiring 16 formed on the second insulating film 15, and a second metal wiring 16
And a passivation film 18 formed on the main surface of the device including the second metal wiring 16 and a connection hole (via hole) 17 for connecting the first metal wiring 13 to each other.

【0015】上記SiO2 絶縁膜12は、たとえば熱酸
化法により約0.6μmの厚さで形成される。上記第1
の金属配線13は、たとえばAl−Cu−Si合金膜を
スパッタ法により約0.6μmの厚さで堆積し、その合
金膜をリソグラフィ技術と異方性エッチング技術とを用
いて加工することで形成される。
The SiO 2 insulating film 12 is formed to a thickness of about 0.6 μm by, for example, a thermal oxidation method. First above
The metal wiring 13 is formed, for example, by depositing an Al—Cu—Si alloy film with a thickness of about 0.6 μm by a sputtering method and processing the alloy film using a lithography technique and an anisotropic etching technique. To be done.

【0016】上記第1の絶縁膜14は、Si−F結合基
およびSi−OH結合基を多く含有してなり、たとえば
フロロカーボン系化合物ガス(500secm)とTE
OSガスとを用いて、約350℃の減圧プラズマ中に
て、約0.8μmの厚さで成膜される。
The first insulating film 14 contains a large amount of Si--F bond groups and Si--OH bond groups, and is composed of, for example, fluorocarbon compound gas (500 sec) and TE.
A film is formed with a thickness of about 0.8 μm in a low-pressure plasma at about 350 ° C. using OS gas.

【0017】上記第2の絶縁膜15は、上記第1の絶縁
膜14よりも少ない量のSi−F結合基を含有してな
り、たとえば上記減圧状態を破らないまま、フロロカー
ボン系化合物ガスの流量を低下させた状態で(または、
ゼロとした状態で)、約1.5μmの厚さで成膜され
る。
The second insulating film 15 contains a smaller amount of Si--F bond groups than the first insulating film 14, and for example, the flow rate of the fluorocarbon-based compound gas can be maintained without breaking the reduced pressure state. (Or with
A film having a thickness of about 1.5 μm is formed with the film thickness set to zero.

【0018】この場合、上記第1の絶縁膜14の誘電率
(ε1 )と上記第2の絶縁膜15の誘電率(ε2 )との
関係はε1 <ε2 となり、たとえばε1 =3.4,ε2
=4.1となっている。
In this case, the relationship between the dielectric constant (ε1) of the first insulating film 14 and the dielectric constant (ε2) of the second insulating film 15 is ε1 <ε2, for example ε1 = 3.4, ε2
= 4.1.

【0019】なお、第2の絶縁膜15としては、Si−
F結合基のみならず、たとえば上記第1の絶縁膜14よ
りも少ない量のSi−OH結合基を含有してなるもので
あっても良い。
As the second insulating film 15, Si-
Not only the F bond group but also a smaller amount of Si—OH bond groups than the first insulating film 14 may be contained.

【0020】また、上記第2の絶縁膜15は、たとえば
Chemical Mechanical Polis
hing(CMP)技術を用いてエッチングされ、その
表面が平坦化されるようになっている。
The second insulating film 15 is formed of, for example, Chemical Mechanical Polis.
Etching is performed by using the Hing (CMP) technique so that the surface is flattened.

【0021】この場合のエッチング量としては、上記第
1の絶縁膜14が表面に露出しない程度、たとえば上記
第1の絶縁膜14上に、0.1μm以上の厚さを有して
上記第2の絶縁膜15が残るようにエッチングが行われ
る。
In this case, the etching amount is such that the first insulating film 14 is not exposed on the surface, for example, the first insulating film 14 has a thickness of 0.1 μm or more and the second insulating film 14 has a thickness of 0.1 μm or more. Etching is performed so that the insulating film 15 of FIG.

【0022】このエッチングは、たとえばCMP装置の
荷重とモータ回転数とを制御することで、簡単に実現で
きる。上記第2の金属配線16は、たとえばAl−Cu
−Si合金膜をスパッタ法により約0.6μmの厚さで
堆積し、その合金膜をリソグラフィ技術と異方性エッチ
ング技術とを用いて加工することで形成される。
This etching can be easily realized by controlling the load of the CMP apparatus and the motor rotation speed, for example. The second metal wiring 16 is, for example, Al—Cu.
It is formed by depositing a -Si alloy film with a thickness of about 0.6 μm by a sputtering method and processing the alloy film using a lithography technique and an anisotropic etching technique.

【0023】上記接続孔17は、上記第2の金属配線1
6の形成前において、上記第1の金属配線13と上記第
2の金属配線16との接続部に対応して、上記第1,第
2の絶縁膜14,15に形成された開孔内に、たとえば
減圧CVD法により、約200℃にてWを選択的に成膜
することで形成される。
The connection hole 17 is provided with the second metal wiring 1
Prior to the formation of No. 6, in the openings formed in the first and second insulating films 14 and 15 corresponding to the connecting portions between the first metal wiring 13 and the second metal wiring 16. It is formed by selectively depositing W at about 200 ° C. by, for example, a low pressure CVD method.

【0024】上記パッシベーション膜18は、たとえば
TEOSガスを用いて、約350℃の減圧プラズマ中に
て、約0.3μmの厚さで成膜される。なお、このパッ
シベーション膜18の一部には、たとえばリソグラフィ
技術とNH4 F溶液とを用いて、外部電極接続用の開孔
部18aが選択的に形成されるようになっている。
The passivation film 18 is formed with a thickness of about 0.3 μm in a low pressure plasma at about 350 ° C. using, for example, TEOS gas. An opening 18a for connecting an external electrode is selectively formed in a part of the passivation film 18 by using, for example, a lithography technique and an NH4F solution.

【0025】このような構成によれば、第1の絶縁膜1
4が表面に露出することなく、第2の絶縁膜15を平坦
化することができるため、この後処理として、たとえば
H2Oによる表面洗浄処理またはH2 SO4 とH2 O2
との混合液を用いた表面洗浄処理を行っても、第1の絶
縁膜14の膜中への水分吸湿が生じることはない。
According to this structure, the first insulating film 1
Since the second insulating film 15 can be planarized without exposing 4 to the surface, the post-treatment is, for example, a surface cleaning treatment with H2O or H2SO4 and H2O2.
Even if the surface cleaning treatment is performed using a mixed liquid of the above, moisture absorption into the film of the first insulating film 14 does not occur.

【0026】したがって、第1の絶縁膜14のSi−O
H結合基ならびにH−OH結合基が増加し、これにとも
なって第1の絶縁膜14の誘電率ε1 が増大するといっ
た、従来装置における不具合を解決できる。
Therefore, the Si--O of the first insulating film 14 is
It is possible to solve the problem in the conventional device that the number of H-bonding groups and the number of H—OH bond groups increase, and the dielectric constant ε1 of the first insulating film 14 increases accordingly.

【0027】次に、図2を参照しつつ、図1に示した本
実施例装置の製造方法について説明する。まず、同図
(a)に示すように、Si基板11上に、たとえば熱酸
化法により、約0.6μmの厚さで上記SiO2 絶縁膜
12が形成される。
Next, with reference to FIG. 2, a method of manufacturing the apparatus of this embodiment shown in FIG. 1 will be described. First, as shown in FIG. 3A, the SiO2 insulating film 12 is formed on the Si substrate 11 by a thermal oxidation method to a thickness of about 0.6 .mu.m.

【0028】また、このSiO2 絶縁膜12の上に、た
とえばスパッタ法により、Al−Cu−Si合金膜が約
0.6μmの厚さで堆積された後、その合金膜がリソグ
ラフィ技術と異方性エッチング技術とを用いて加工され
ることで、上記第1の金属配線13が選択的に形成され
る。
An Al--Cu--Si alloy film having a thickness of about 0.6 .mu.m is deposited on the SiO2 insulating film 12 by, for example, a sputtering method. The first metal wiring 13 is selectively formed by being processed by using an etching technique.

【0029】次いで、同図(b)に示すように、上記第
1の金属配線13を含む上記SiO2 絶縁膜12の上
に、Si−F結合基およびSi−OH結合基を多く含有
してなる、誘電率ε1 が3.4とされた上記第1の絶縁
膜14が、たとえばフロロカーボン系化合物ガス(50
0secm)とTEOSガスとを用いて、約350℃の
減圧プラズマ中にて、約0.8μmの厚さで成膜され
る。
Then, as shown in FIG. 3B, a large amount of Si--F bond groups and Si--OH bond groups are contained on the SiO2 insulating film 12 including the first metal wiring 13. , The first insulating film 14 having a dielectric constant ε1 of 3.4 is formed of, for example, fluorocarbon compound gas (50
0 sec) and TEOS gas are used to form a film with a thickness of about 0.8 μm in a reduced pressure plasma at about 350 ° C.

【0030】また、上記第1の絶縁膜14を成膜した
後、この第1の絶縁膜14よりも少ない量のSi−F結
合基を含有してなる、誘電率ε2 が4.1とされた上記
第2の絶縁膜15が、たとえば上記減圧状態を破らない
まま、フロロカーボン系化合物ガスの流量を低下させた
状態で(または、ゼロとした状態で)、約1.5μmの
厚さで成膜される。
After the first insulating film 14 is formed, the dielectric constant ε 2 is 4.1, which contains a smaller amount of Si-F bond groups than the first insulating film 14. The second insulating film 15 is formed to have a thickness of about 1.5 μm, for example, in a state where the flow rate of the fluorocarbon-based compound gas is reduced (or in a state where it is zero) without breaking the reduced pressure state. Be filmed.

【0031】しかる後、同図(c)に示すように、上記
第2の絶縁膜15が、たとえばCMP技術を用いてエッ
チングされ、0.1μm以上の厚さを残して平坦化され
る。次いで、同図(d)に示すように、上記第1の金属
配線13と上記第2の金属配線16とを接続するための
開孔が形成され、この開孔に対して、たとえば減圧CV
D法により、約200℃にてWを選択的に成膜すること
で、上記接続孔17が形成される。
Thereafter, as shown in FIG. 3C, the second insulating film 15 is etched by using, for example, the CMP technique, and is flattened leaving a thickness of 0.1 μm or more. Next, as shown in FIG. 3D, an opening for connecting the first metal wiring 13 and the second metal wiring 16 is formed, and for example, a reduced pressure CV is formed in the opening.
The connection hole 17 is formed by selectively depositing W at about 200 ° C. by the D method.

【0032】さらに、上記接続孔17に対応する上記第
2の絶縁膜15の上に、たとえばスパッタ法により、A
l−Cu−Si合金膜が約0.6μmの厚さで堆積され
た後、その合金膜がリソグラフィ技術と異方性エッチン
グ技術とを用いて加工されることで、上記第2の金属配
線16が選択的に形成される。
Further, on the second insulating film 15 corresponding to the connection hole 17, A is formed by, for example, a sputtering method.
After the 1-Cu-Si alloy film is deposited to a thickness of about 0.6 μm, the alloy film is processed by using the lithography technique and the anisotropic etching technique, whereby the second metal wiring 16 is formed. Are selectively formed.

【0033】この後、上記第2の金属配線16を含む上
記第2の絶縁膜15の上に、たとえばTEOSガスを用
いて、約350℃の減圧プラズマ中にて、約0.3μm
の厚さで、上記パッシベーション膜18が成膜される。
Thereafter, on the second insulating film 15 including the second metal wiring 16, for example, TEOS gas is used, and the pressure is reduced to about 0.3 μm in a reduced pressure plasma at about 350 ° C.
The passivation film 18 is formed to a thickness of.

【0034】そして、このパッシベーション膜18の一
部に、たとえばリソグラフィ技術とNH4 F溶液とを用
いて、外部電極接続用の開孔部18aが選択的に形成さ
れることにより、上記した本実施例装置は製造される。
Then, an opening portion 18a for connecting an external electrode is selectively formed in a part of the passivation film 18 by using, for example, a lithographic technique and an NH4F solution, whereby the above-mentioned embodiment is carried out. The device is manufactured.

【0035】上記したように、Si−F結合基およびS
i−OH結合基を多く含有する第1の絶縁膜の吸湿を阻
止できるようにしている。すなわち、Si−F結合基お
よびSi−OH結合基を多く含有して成膜された第1の
絶縁膜を外気にさらすことなく、連続した処理にて、そ
れよりも少ない量のSi−F結合基を含有してなる第2
の絶縁膜を上記第1の絶縁膜の上に成膜するとともに、
その第1の絶縁膜が表面に露出しないようにして上記第
2の絶縁膜のみをエッチングするようにしている。これ
により、エッチング工程中および工程終了後において
も、第1の絶縁膜が大気中もしくは液層中にさらされる
のを第2の絶縁膜により保護できるようになるため、第
1の絶縁膜の誘電率を安定に保つことが可能となる。し
たがって、水分の吸湿により膜の誘電率が増大されて配
線間容量や配線層間容量が増加されるのを防止でき、よ
って誘電率のばらつきによって特性が不安定となるのを
阻止することができるものである。
As mentioned above, the Si--F linking group and the S
The first insulating film containing a large amount of i-OH bond groups is prevented from absorbing moisture. That is, the first insulating film containing a large amount of Si—F bond groups and Si—OH bond groups is exposed to the outside air without being exposed to the outside air, and a smaller amount of Si—F bond than that can be continuously processed. A second containing group
The insulating film of is formed on the first insulating film,
Only the second insulating film is etched so that the first insulating film is not exposed on the surface. As a result, the second insulating film can protect the first insulating film from being exposed to the atmosphere or the liquid layer during and after the etching process, so that the dielectric constant of the first insulating film can be improved. It is possible to keep the rate stable. Therefore, it is possible to prevent the inter-wiring capacitance and inter-wiring inter-layer capacitance from increasing due to the moisture absorption of the film, thereby preventing the characteristics from becoming unstable due to variations in the dielectric constant. Is.

【0036】しかも、第2の絶縁膜の平坦化をCMP技
術を用いて行うことで、製造工程の簡素化も図ることが
できるものである。なお、上記実施例においては、第1
の金属配線上に第1の絶縁膜を直に形成する場合につい
て説明したが、これに限らず、たとえば図3に示すよう
に、第1の金属配線13と第1の絶縁膜14との間にS
iO2 絶縁膜(第3の絶縁膜)21を形成するようにし
ても良い。
Moreover, by flattening the second insulating film by using the CMP technique, the manufacturing process can be simplified. In the above embodiment, the first
Although the case where the first insulating film is directly formed on the metal wiring has been described, the present invention is not limited to this, and as shown in FIG. 3, for example, between the first metal wiring 13 and the first insulating film 14, To S
An i02 insulating film (third insulating film) 21 may be formed.

【0037】このSiO2 絶縁膜21は、上記第1の金
属配線13を形成した後、たとえばTEOSガスを用い
て、約350℃の減圧プラズマ中にて、約0.05μm
の厚さで成膜される。
This SiO 2 insulating film 21 is formed to have a thickness of about 0.05 μm in a low pressure plasma at about 350 ° C. by using, for example, TEOS gas after forming the first metal wiring 13.
Is formed with a thickness of.

【0038】そして、これ以降は上記した各工程を順に
行うことで、図3に示す構造の半導体装置は製造でき
る。この場合、第1の金属配線13を第1の絶縁膜14
と分離できるようになるため、第1の金属配線13に、
たとえば第1の絶縁膜14と反応しやすいTiなどを用
いることが可能となる。
After that, the semiconductor device having the structure shown in FIG. 3 can be manufactured by sequentially performing the above steps. In this case, the first metal wiring 13 is connected to the first insulating film 14
Since it can be separated from the first metal wiring 13,
For example, Ti or the like that easily reacts with the first insulating film 14 can be used.

【0039】また、このSiO2 絶縁膜21を成膜後、
その減圧状態を維持したまま、上記第1の絶縁膜14お
よび第2の絶縁膜15を連続して形成するようにするこ
とも可能である。その他、この発明の要旨を変えない範
囲において、種々変形実施可能なことは勿論である。
After forming this SiO 2 insulating film 21,
It is also possible to continuously form the first insulating film 14 and the second insulating film 15 while maintaining the reduced pressure state. Of course, various modifications can be made without departing from the scope of the invention.

【0040】[0040]

【発明の効果】以上、詳述したようにこの発明によれ
ば、誘電率の増大にともなう配線間容量や配線層間容量
の増加を防止でき、特性を安定化させることが可能な半
導体装置の製造方法を提供できる。
As described above in detail, according to the present invention, it is possible to prevent the increase of the inter-wiring capacitance and the inter-wiring capacitance due to the increase of the dielectric constant, and to manufacture the semiconductor device capable of stabilizing the characteristics. A method can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例にかかる半導体装置の概略
構成を示す断面図。
FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.

【図2】同じく、半導体装置の製造工程を概略的に示す
断面図。
FIG. 2 is a sectional view schematically showing the manufacturing process of the semiconductor device.

【図3】この発明の他の実施例にかかる半導体装置の概
略構成を示す断面図。
FIG. 3 is a sectional view showing a schematic configuration of a semiconductor device according to another embodiment of the present invention.

【図4】従来技術とその問題点を説明するために示す半
導体装置の断面図。
FIG. 4 is a cross-sectional view of a semiconductor device shown for explaining a conventional technique and its problems.

【符号の説明】[Explanation of symbols]

11…Si基板、12…SiO2 絶縁膜、13…第1の
金属配線、14…第1の絶縁膜、15…第2の絶縁膜、
16…第2の金属配線、17…接続孔、18…パッシベ
ーション膜、21…SiO2 絶縁膜(第3の絶縁膜)。
11 ... Si substrate, 12 ... SiO2 insulating film, 13 ... First metal wiring, 14 ... First insulating film, 15 ... Second insulating film,
16 ... Second metal wiring, 17 ... Connection hole, 18 ... Passivation film, 21 ... SiO2 insulating film (third insulating film).

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 多層構造とされた上下の配線層の相互間
に誘電率の異なる複数の絶縁膜を積層してなる半導体装
置の製造方法において、 前記下層側の配線上に誘電率の低い第1の絶縁膜を形成
する工程と、 この第1の絶縁膜の上面を外気にさらすことなく、その
上部に前記第1の絶縁膜よりも誘電率の高い第2の絶縁
膜を形成する工程と、 この第2の絶縁膜を、前記第1の絶縁膜を表面に露出さ
せることなく平坦化する工程とからなることを特徴とす
る半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: laminating a plurality of insulating films having different dielectric constants between upper and lower wiring layers having a multi-layered structure; A step of forming a first insulating film, and a step of forming a second insulating film having a higher dielectric constant than the first insulating film above the first insulating film without exposing the upper surface of the first insulating film to the outside air. And a step of planarizing the second insulating film without exposing the first insulating film to the surface thereof.
【請求項2】 多層構造とされた上下の配線層の相互間
に誘電率の異なる複数の絶縁膜を積層してなる半導体装
置の製造方法において、 前記下層側の配線上に、所定量のSi−F結合基および
Si−OH結合基を含有してなる第1の絶縁膜を形成す
る工程と、 この第1の絶縁膜の上面を外気にさらすことなく、その
上部に前記第1の絶縁膜よりもSi−F結合基およびS
i−OH結合基の両方もしくは片方の含有量が少ない第
2の絶縁膜を形成する工程と、 この第2の絶縁膜を、前記第1の絶縁膜を表面に露出さ
せることなく平坦化する工程とからなることを特徴とす
る半導体装置の製造方法。
2. A method of manufacturing a semiconductor device, comprising: laminating a plurality of insulating films having different dielectric constants between upper and lower wiring layers having a multilayer structure, wherein a predetermined amount of Si is provided on the lower wiring. A step of forming a first insulating film containing a —F bond group and a Si—OH bond group, and a step of forming the first insulating film on the upper surface of the first insulating film without exposing the upper surface to the outside air. Than Si-F bonding group and S
a step of forming a second insulating film having a low content of both or one of the i-OH bond groups, and a step of planarizing the second insulating film without exposing the first insulating film to the surface. A method of manufacturing a semiconductor device, comprising:
【請求項3】 前記第2の絶縁膜を平坦化する工程は、
ChemicalMechanical Polish
ing(CMP)技術を用いることを特徴とする請求項
2に記載の半導体装置の製造方法。
3. The step of planarizing the second insulating film comprises:
Chemical Mechanical Polish
The method of manufacturing a semiconductor device according to claim 2, wherein an ing (CMP) technique is used.
【請求項4】 前記第2の絶縁膜を形成する工程は、前
記第1の絶縁膜を形成した減圧状態のまま連続して行わ
れることを特徴とする請求項2に記載の半導体装置の製
造方法。
4. The manufacturing of a semiconductor device according to claim 2, wherein the step of forming the second insulating film is continuously performed in a depressurized state where the first insulating film is formed. Method.
【請求項5】 前記下層側の配線と前記第1の絶縁膜と
の間に、前記第1,第2の絶縁膜とは異なる第3の絶縁
膜を形成する工程を含むことを特徴とする請求項2に記
載の半導体装置の製造方法。
5. A step of forming a third insulating film, which is different from the first and second insulating films, between the wiring on the lower layer side and the first insulating film. The method for manufacturing a semiconductor device according to claim 2.
JP33419093A 1993-12-28 1993-12-28 Method for manufacturing semiconductor device Expired - Fee Related JP3199942B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33419093A JP3199942B2 (en) 1993-12-28 1993-12-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33419093A JP3199942B2 (en) 1993-12-28 1993-12-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH07201985A true JPH07201985A (en) 1995-08-04
JP3199942B2 JP3199942B2 (en) 2001-08-20

Family

ID=18274552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33419093A Expired - Fee Related JP3199942B2 (en) 1993-12-28 1993-12-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3199942B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252280A (en) * 2001-02-26 2002-09-06 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252280A (en) * 2001-02-26 2002-09-06 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP3199942B2 (en) 2001-08-20

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