JP2000252286A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the parasitic capacity at groove wiring by discharging hydrogen on dry etching, by using a silicon oxide film for reducing the amount of etching active species of plasma excitation as the mask of the dry etching, and by selectively etching an insulating film material to be etched. SOLUTION: A first interlayer insulation film 2 is formed on a silicon substrate 1, and an etching mask layer 3 being composed by a silicon oxide film that contains a large amount of hydrogen and reduces the amount of etching active species of plasma excitation is formed on the interlayer insulation film 2. Then, on the etching mask layer 3, a second interlayer insulation film 4 is formed, and, on the second interlayer insulation film 4, a resist mask 5 for forming a wiring pattern is formed. The resist mask 5 is used as an etching mask, hydrogen is discharged from the etching mask layer 3, the second interlayer insulation 4 is subjected to dry etching for forming a wiring groove 6, and a barrier layer 7 and groove wiring 8 are buried to the wiring groove 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a low dielectric constant interlayer insulating film and wiring.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, fine multilayer wiring is indispensable for semiconductor devices. In addition, as the operation of the semiconductor device is reduced in voltage and speed, it is necessary to lower the dielectric constant of the interlayer insulating film. In particular, in a logic-based semiconductor device, an increase in resistance due to fine wiring and an increase in parasitic capacitance between wirings lead to a deterioration in operation speed of the semiconductor device. Therefore, a multilayer using a fine and low dielectric constant film as an interlayer insulating film. Wiring is required.

[0003] Miniaturization of the wiring width and the reduction of the wiring pitch not only increase the aspect ratio of the wiring itself, but also increase the aspect ratio of the wiring itself.
The aspect ratio of the space between the wirings is also increased, and as a result, a burden is imposed on the technology of forming fine and narrow wiring in the vertical direction and the technology of embedding the space between the fine wirings with an interlayer insulating film. And increase the number of processes at the same time.

Therefore, a wiring groove is formed in the interlayer insulating film,
A trench wiring technique of embedding a wiring material in this wiring groove by a chemical mechanical polishing (CMP) method has been receiving attention. However, in forming a wiring groove or a through hole in this technique, it is necessary to form an etching stopper film.

[0005] As such an etching stopper film, an insulating film having an etching rate different from that of an interlayer insulating film in which a wiring groove or a through hole is formed is used.

Hereinafter, the outline of the above-mentioned conventional technology will be briefly described by using the technology described in Japanese Patent Laid-Open Publication No. Hei 10-116904. Here, the technology described in the above publication is simplified for the sake of simplicity.

FIG. 9 is a schematic cross-sectional view for explaining the prior art, in the order of the manufacturing process of the trench wiring.

As shown in FIG. 9A, a first interlayer insulating film 102 is formed on a silicon substrate 101 on which elements (not shown) have been formed in advance. Here, the first interlayer insulating film 102 is a silicon oxide film, and the film is formed by a plasma-excited chemical vapor deposition (plasma CVD) method.

Next, a silicon nitride film 103 is formed on the first interlayer insulating film 102 as an etching stopper film. Further, a second interlayer insulating film 104 is formed on the silicon nitride film 103. This second interlayer insulating film 104
Is also a silicon oxide film deposited by the plasma CVD method.

Next, as shown in FIG. 9B, a resist pattern 105 for forming a wiring pattern is formed on the second interlayer insulating film 104 by a photolithography technique. Then, the second interlayer insulating film 1 is formed by reactive ion etching (RIE) using the resist pattern 105 as a mask.
04 is dry-etched to form a wiring groove 106.

Here, the silicon nitride film 103 functions as an etching stopper film in the dry etching of the second interlayer insulating film 104 for forming the wiring groove 106.

Next, the resist pattern 105 is removed by ashing in oxygen plasma. Then, with a general sputtering apparatus for forming a metal film, Al
An alloy film is formed as a wiring material. Next, the general C
In the MP apparatus, the Al alloy film is polished by the CMP method, and unnecessary portions of the Al alloy film on the second interlayer insulating film 104 are removed.

As described above, as shown in FIG. 9C, the wiring groove of the second interlayer insulating film 104 provided on the silicon substrate 101 and on the first interlayer insulating film 102 with the silicon nitride film 103 interposed therebetween. The trench wiring 107 is formed to be embedded in the groove 106.

[0014]

However, in the prior art as described above, the dielectric constant of the etching stopper film increases, and the parasitic capacitance between wirings increases. In the above example, the relative permittivity of the silicon nitride film is 7 to 8, which is about twice as large as ４4 of the silicon oxide film. Due to the increase in the parasitic capacitance between the wirings, the operation speed of the semiconductor device, particularly, the logic semiconductor device is reduced.

Alternatively, it is not possible to form a trench wiring using an organic low dielectric constant film as an interlayer insulating film, and there is a limit in reducing the dielectric constant of the interlayer insulating film.

A main object of the present invention is to make it possible to reduce the parasitic capacitance between trench wirings by a simple method. Still another object of the present invention is to make it possible to use an organic low dielectric constant film as an interlayer insulating film.

[0017]

For this reason, in the method of manufacturing a semiconductor device according to the present invention, a silicon oxide film containing hydrogen atoms, which releases the hydrogen at the time of dry etching to form a plasma-excited etching active species. The material of the insulating film to be etched is selectively etched using the silicon oxide film whose amount is to be reduced as a mask for dry etching.

Alternatively, the method of manufacturing a semiconductor device according to the present invention comprises the steps of laminating a first interlayer insulating film, a hydrogen-containing oxide film, and a second interlayer insulating film on a semiconductor substrate in this order; Forming a wiring groove in the second interlayer insulating film by dry-etching the second interlayer insulating film using the hydrogen-containing oxide film as an etching stopper film; and forming a groove wiring by embedding a metal material in the wiring groove. Forming.

Here, in the dry etching, a reaction gas which is an organic compound of halogen and does not contain hydrogen is used. The insulating material to be etched or the interlayer insulating film is made of a silicon oxide film containing no hydrogen.

The hydrogen-containing oxide film is composed of hydrogen silsequiosan.

Further, the method of manufacturing a semiconductor device according to the present invention
Laminating a hydrogen-containing oxide film and an organic insulating film on a semiconductor substrate, and laminating a first mask layer and a second mask layer in this order on the surface of the organic insulating film; Forming, etching and transferring a predetermined pattern of a resist mask formed on the second mask layer to the second mask layer, and removing the resist mask after the etching transfer; Dry etching the organic insulating film using the layer as an etching mask and the hydrogen-containing oxide film as an etching stopper film to form a wiring groove in the organic insulating film; and embedding a metal material in the wiring groove. And forming a grooved wiring.

Here, the first mask layer and the second mask layer are composed of a hydrogen-containing oxide film and a silicon oxynitride film, respectively. Alternatively, the hydrogen-containing oxide film is composed of hydrogen silsesquioxane.

Further, the organic insulating film is made of fluorinated amorphous carbon, benzylcyclobutene or organic polysilazane which is a low dielectric constant film.

As described above, in the present invention, a hydrogen-containing oxide film is used as an etching mask for dry etching. The relative permittivity of such an oxide film does not become larger than that of a silicon oxide film formed by an ordinary method.
When the hydrogen-containing oxide film is made of hydrogen silsesquioxane, its relative dielectric constant becomes 3 or less.

In the method of the present invention, in forming the trench wiring, the hydrogen-containing oxide film sufficiently functions as an etching stopper film, and the parasitic capacitance between the trench wirings is greatly reduced.

[0026]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present invention in the order of forming trench wirings.

As shown in FIG. 1A, a first interlayer insulating film 2 is formed on a silicon substrate 1 as described in the prior art. Here, the first interlayer insulating film 2 is a plasma CV
This is a silicon oxide film having a thickness of about 500 nm deposited by the method D.

Next, an etching mask layer 3 is formed on the first interlayer insulating film 2. This etching mask layer 3
Is composed of a silicon oxide film containing a large amount of hydrogen as described later in detail. Here, the thickness of the etching mask layer 3 is set to about 100 nm.

Then, a second interlayer insulating film 4 is formed on the etching mask layer 3. The second interlayer insulating film 4 is also deposited by a plasma CVD method and is a silicon oxide film having a thickness of about 500 nm.

Next, as shown in FIG. 1B, a resist mask 5 for forming a wiring pattern is formed on the second interlayer insulating film 4 by photolithography. And
In the RIE, the second interlayer insulating film 4 is dry-etched using the resist mask 5 as an etching mask to form a wiring groove 6. Here, the width of the wiring groove 6 is set to about 0.2 μm.

Here, the etching mask layer 3 functions as an etching stopper film in the dry etching of the second interlayer insulating film 4 for forming the wiring groove 6.
Note that, as a reaction gas in this dry etching, C ₄
A mixed gas of F ₈ gas, O ₂ gas and Ar gas is used. In addition, an organic compound of halogen containing no hydrogen is used as the reaction gas.

Next, the resist mask 5 is removed. Then, as described in the background art, the formation of the metal film and the formation of C
With the polishing by the MP method, the metal film is embedded in the wiring groove.

As described above, as shown in FIG. 1C, the second interlayer insulating film provided on the silicon substrate 1 and the first interlayer insulating film 2 via the silicon oxide film containing a large amount of hydrogen. The barrier layer 7 and the groove wiring 8 are buried and formed in the wiring groove 6 of the film 4. Here, the barrier layer 7 is made of titanium nitride (TiN), and the trench wiring 8 is made of copper (Cu).

Next, the etching mask layer 3 which is a feature of the present invention will be described with reference to FIGS.
2 and 3 are graphs showing characteristics of a silicon oxide film containing a large amount of hydrogen. Here, as a silicon oxide film containing a large amount of hydrogen, a hydrogen silsequiosane (HSQ) film, which is a coating insulating film, is used.

In FIG. 2, the horizontal axis represents the width of the wiring groove, and the vertical axis represents the groove.
Each etching rate in the ly etching is taken
I have. Here, C is used as a reactive etching gas.
_Four F ₈ Gas, O_Two Gas, a mixed gas of Ar gas is used.
ing. In addition, as a silicon oxide film (●)
Silicon oxide film (plasma Si) formed by plasma CVD
O_Two Membrane), (△) HSQ annealed in normal pressure of nitrogen
Film, (○) HSQ film annealed in vacuum is used
I have. Here, the annealing temperature of the HSQ film is 400 ° C.
You. In the case of annealing in a vacuum, the degree of vacuum is 10
^-9Torr-10 ^-3Set to Torr.

As can be seen from FIG. 2, when the wiring groove width is 1 μm or less, the etching rate of the HSQ film annealed in a vacuum is about １ ／ of that of the plasma SiO ₂ film.
The etching rate of the HSQ film annealed in normal pressure of nitrogen is 2 times that of the HSQ film annealed in vacuum.
It increases about twice. The above etching characteristics are for the case of etching into a predetermined pattern. On the other hand, in the case of etching over the entire surface, as shown in FIG. 2, there is no large difference in the etching rate among the above three types of silicon oxide films. This indicates that the microloading effect in dry etching differs depending on the material to be etched. Then, in dry etching of the silicon oxide film, a material belonging to the same silicon oxide film can be used as an etching mask.

FIG. 3 is an infrared (IR) absorption spectrum of the HSQ film. The spectrum in the upper part of FIG. 3 is obtained after a coating solution for forming an HSQ film is applied to the surface of a silicon substrate and baked at a temperature of about 150 ° C. As can be seen from the figure, the HSQ film before annealing has a Si—H bond and a Si—O bond. Thus, this HSQ
The film is based on a siloxane polymer (hereinafter referred to as a silicon oxide film) and is an insulating film having a large amount of Si-H bonds.

The spectrum in the middle of FIG. 3 is that of the HSQ film annealed in the vacuum. Also in this case, similarly to the HSQ film before annealing, the bonding of Si—H and Si—O
Is present in large amounts.

The spectrum in the lower part of FIG. 3 is that of the HSQ film annealed at normal pressure of nitrogen. In this case,
Although the bond of Si—O is the same as that described above,
Is reduced. Then, the bonding of Si—OH increases.

Taking into account the structure of the HSQ film understood from FIG. 3, the etching characteristics of FIG. 2 will be described as follows.

That is, in the HSQ film annealed in a vacuum, a large amount of Si—H bonds exist in the film, the microloading effect becomes remarkable, and the etching rate decreases. This is because a large amount of hydrogen is released from the HSQ film in the process of dry etching the HSQ film, and this hydrogen reacts with the plasma-excited reaction gas to reduce the amount of etching active species.

The inventor examined the etching characteristics described above by changing the dry etching reaction gas. As a result, it has been found that even when the reaction gas is an organic compound of halogen, the microloading effect as described above does not occur when the reaction gas contains hydrogen. It was also found that the decrease in the etching rate due to the microloading effect was unrelated to the hydrogen bonding state of the silicon oxide film.

As described above, when hydrogen is contained in the silicon oxide film and this hydrogen is released during dry etching and the amount of active species to be etched is reduced, the etching of the silicon oxide film containing hydrogen is reduced. I do. Then, as described in the first embodiment, the etching mask layer 3 functions as an etching stopper film for forming the wiring groove 6. When an HSQ film annealed in vacuum is used as the etching mask layer 3, its relative dielectric constant becomes 3 or less. And plasma C
The relative dielectric constant of the silicon nitride film formed by the VD method is greatly reduced from ８8.

Next, the second embodiment of the present invention will be described with reference to FIGS.
An embodiment will be described. The second embodiment is a case where an organic low dielectric constant insulating film is used as an interlayer insulating film. 4 and 5 are schematic cross-sectional views in this case in the order of the groove wiring forming process. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 4A, the silicon substrate 1
A first low dielectric constant insulating film 9 is formed thereon. Here, the first
The low dielectric constant insulating film 9 is an organic insulating film made of fluorinated amorphous carbon having a thickness of about 500 nm. The relative dielectric constant of the fluorinated amorphous carbon is about 2.4.

Next, an etching mask layer 3 having a thickness of 50 nm is formed on the first low dielectric constant insulating film 9. This etching mask layer 3 is made of HS annealed in the vacuum.
Q film.

Then, a second low dielectric constant insulating film 10 is formed on the etching mask layer 3. The second low dielectric constant insulating film 10 is also an organic insulating film made of fluorinated amorphous carbon having a thickness of 500 nm.

Further, the first low dielectric constant insulating film 10
The mask layer 11 and the second mask layer 12 are formed by lamination. Here, the first mask layer 11 is an HSQ film annealed in a vacuum having a thickness of about 50 nm. The second mask layer 12 has a thickness of 10 formed by a plasma CVD method.
It is a silicon oxynitride (SiON) film of about nm.

Next, as shown in FIG. 4B, a resist mask 5a for forming a wiring pattern is formed on the second mask layer 12 by photolithography, and the second mask is formed using the resist mask 5a as an etching mask. Layer 12
Is dry-etched. In the dry etching of the second mask layer 12, a mixed gas of CF ₄ and O ₂ is used as a reaction gas, and the first mask layer 11 is hardly etched.

Thereafter, the resist mask 5a is removed by a plasma ashing method using O ₂ gas. As a result, a first opening 13 having a wiring pattern shape is formed in a predetermined region of the second mask layer 12.

Usually, an organic low dielectric constant insulating film is easily etched by oxygen plasma. However, in the case of the present invention, the second low dielectric constant insulating film 10 is completely covered with the first mask layer 11 in the step of removing the resist mask 5a by the plasma ashing method. For this reason, the etching of the second low dielectric constant insulating film 10 in the plasma ashing process is completely prevented.

Next, as shown in FIG. 4C, the first mask layer 11 is dry-etched using the second mask layer 12 as a dry etching mask, and a second opening 14 is formed. In the dry etching of the first mask layer 11,
CHF ₃ gas is used as a reaction gas. In this dry etching, the second mask layer 11 or the second low dielectric constant insulating film 10 is hardly etched.

Next, as shown in FIG. 5A, the second low dielectric constant insulating film 10 is dry-etched using the second mask layer 12 as an etching mask to form a wiring groove 6. Here, in the dry etching of the second low dielectric constant insulating film 10, a mixed gas of Cl ₂ and O ₂ is used as a reaction gas, and anisotropic dry etching is performed. Thus, the wiring groove 6 without side etching is formed.

Next, as described in the first embodiment, the metal film is embedded in the wiring groove by the formation of the metal film and the polishing by the CMP method. In this way, as shown in FIG. 5B, the barrier layer 7 and the trench wiring 8 are formed by being buried in the wiring trench 6 of the second low dielectric constant insulating film 10. here,
The second mask layer 12 functions as a polishing stopper layer in the above polishing step by CMP.

Next, the second mask layer 12 is removed. Then, as shown in FIG. 5C, a third low dielectric constant insulating film 15 is formed on the entire surface. Here, the third low dielectric constant insulating film 1
5 is an organic coating film having a low dielectric constant and a film thickness of about 200 nm, such as BCB (benzylcyclobutene). The relative dielectric constant of such an organic coating film is 3 or less, which is considerably lower than the value 4 of the silicon oxide film.

As described above, as shown in FIG. 5 (c), on the silicon substrate 1 and on the organic first low dielectric constant insulating film 9 via the etching mask layer 3, 2 The barrier layer 7 and the groove wiring 8 are formed so as to be embedded in the wiring groove 6 in the low dielectric constant insulating film 10.

According to the method of the present invention, an organic low dielectric constant film can be easily used as an interlayer insulating film in forming a trench wiring. Since the trench wiring is completely covered with the low dielectric constant insulating film, the parasitic capacitance between the trench wirings is greatly reduced.

In the second embodiment, the case where fluorinated amorphous carbon is used as the organic low dielectric constant insulating film has been described. In addition, as such a low dielectric constant insulating film, an organic polysilazane having a relative dielectric constant of about 2.6, a BCB having a relative dielectric constant of about 2.7, and a relative dielectric constant of 2.
About 6 Parylene F (registered trademark), fluorinated polyimide, plasma CF polymer, plasma CH polymer, and fluorinated polyallyl ether may be used. Further, as the second mask layer 12, a silicon nitride film may be used instead of the SiON film.

Next, a third embodiment of the present invention will be described with reference to FIGS. 6 to 8 are cross-sectional views in the order of the manufacturing process for explaining the formation of the multilayer groove wiring. Here, the same components as those in the first embodiment are denoted by the same reference numerals.

As in the first embodiment, FIG.
As shown in FIG. 2A, a barrier buried in a wiring groove 6 provided in a second interlayer insulating film 4 formed on a first interlayer insulating film 2 of a silicon substrate 1 via an etching mask layer 3. The layer 7 and the trench wiring 8 are formed. This groove wiring 8 becomes a lower wiring of the multilayer wiring. Then, a hydrogen-containing oxide film 16 is formed on the entire surface. Here, the hydrogen-containing oxide film 16 is a silicon oxide film having a thickness of 500 nm and containing several at% of hydrogen atoms. Here, the relative dielectric constant of the hydrogen-containing oxide film 16 is about 4.

Next, as shown in FIG. 6A, a resist mask 5b for forming a through-hole pattern is formed by photolithography. Then, the third interlayer insulating film 17 is formed using the resist mask 5b as an etching mask.
Then, the oxide film 16 containing hydrogen is dry-etched, and a through hole 18 reaching the trench wiring 8 is formed.

After that, the resist mask 5b is removed by the plasma ashing method, and the buried resist 19 is filled in the through hole 18 as shown in FIG.

Next, as shown in FIG. 7B, a resist mask 5c for forming a wiring pattern is formed on the third interlayer insulating film 17 by a photolithography technique, and the third resist mask 5c is used as an etching mask. The interlayer insulating film 17 is dry-etched. Thus, the wiring groove 6a for the upper wiring is formed. This dry etching is performed in the same manner as in the first embodiment. Then, the hydrogen-containing oxide film 16 functions as an etching stopper film.

Thereafter, the resist mask 5c and the buried resist 19 are removed by the plasma ashing method. As a result, as shown in FIG. 8A, the wiring groove 6a for the upper wiring is formed in the third interlayer insulating film 17 by the hydrogen-containing oxide film 1.
6, through holes 18a are respectively formed.

Next, as shown in FIG. 8B, the upper layer wiring is formed by forming the barrier layer and the metal wiring film and polishing by the CMP method in the same manner as described in the first embodiment. Barrier layer 7 a and trench wiring 8 a are formed in third interlayer insulating film 17. In this manner, a groove wiring having a two-layer structure, that is, a lower layer wiring 8 and an upper layer groove wiring 8a connected to each other through the through hole 18a are formed.

In the third embodiment, the hydrogen-containing oxide film 16 functions as an etching stopper film,
It becomes an interlayer insulating film between the lower groove wiring 8 and the upper groove wiring 8a.

Also in this embodiment, wiring grooves for groove wiring can be formed with good control. Then, unlike the case of the conventional technique, the parasitic capacitance between the trench wirings is greatly reduced.

In the formation of the multi-layer trench wiring of the third embodiment, as described in the second embodiment, an organic low dielectric constant insulating film may be applied to the interlayer insulating film.

[0069]

As described above, according to the present invention, a silicon oxide film containing hydrogen atoms, which releases the hydrogen during dry etching and reduces the amount of plasma-excited etching active species. Using the film as a dry etching mask, the material of the insulating film to be etched is selectively etched. When a wiring groove is formed in an interlayer insulating film for forming a groove wiring, the above-described silicon oxide film containing hydrogen atoms is used as an etching stopper film. As the hydrogen-containing oxide film, an HSQ film having a small relative dielectric constant is used.

For this reason, in forming the groove wiring, the dimensional control of the wiring groove is greatly improved, and the formation of fine groove wiring is facilitated.

In addition, a wiring groove can be formed in an organic low dielectric constant film, and the parasitic capacitance between the groove wirings is greatly reduced. Further, it is possible to form a multilayer wiring structure using fine groove wiring.

In this way, it is easy to improve the performance and reliability of the fine multilayer wiring with the miniaturization or multifunctionalization of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention in the order of manufacturing steps of trench wiring.

FIG. 2 is a graph for explaining dry etching characteristics of an etching mask layer of the present invention.

FIG. 3 is an infrared absorption spectrum of a film for explaining the structural characteristics of the etching mask layer of the present invention.

FIG. 4 is a cross-sectional view for explaining a second embodiment of the present invention in the order of manufacturing steps of trench wiring.

FIG. 5 is a cross-sectional view for explaining a second embodiment of the present invention in the order of manufacturing steps of a trench wiring.

FIG. 6 is a cross-sectional view illustrating a groove wiring for explaining a third embodiment of the present invention in the order of manufacturing steps;

FIG. 7 is a cross-sectional view for explaining a third embodiment of the present invention in the order of manufacturing steps of a trench wiring.

FIG. 8 is a cross-sectional view for explaining a third embodiment of the present invention in the order of manufacturing steps of the groove wiring.

FIG. 9 is a cross-sectional view illustrating a related art in the order of manufacturing steps of trench wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 Silicon substrate 2,102 1st interlayer insulating film 3 Etching mask layer 4,104 2nd interlayer insulating film 5,5a, 5b, 5c Resist mask 6,6a, 106 Wiring groove 7,7a Barrier layer 8,8a, 107 trench wiring 9 first low dielectric constant insulating film 10 first low dielectric constant insulating film 11 first mask layer 12 second mask layer 13 first opening 14 second opening 15 third low dielectric constant insulating film 16 hydrogen-containing Oxide film 17 third interlayer insulating film 18, 18a through hole 19 buried resist 103 silicon nitride film 105 resist pattern

Continued on front page F-term (reference) 5F004 BA04 DA00 DA04 DA16 DA23 DA26 DB00 DB03 DB08 DB12 EA03 EA06 EA15 EA23 EB01 EB02 EB03 5F033 HH11 HH33 JJ11 JJ33 KK11 KK33 MM01 MM02 MM12 MM13 RR06 RRRR RR24 RR26 SS15 SS22 TT03 TT04 XX24 XX27

Claims (9)

[Claims] 1. A silicon oxide film containing a hydrogen atom, said silicon oxide film releasing hydrogen during dry etching to reduce the amount of plasma-excited etching active species (hereinafter referred to as a hydrogen-containing oxide film). A method of manufacturing a semiconductor device, wherein a material of an insulating film to be etched is selectively etched by using a dry etching mask as a mask. 2. A step of forming a first interlayer insulating film, a hydrogen-containing oxide film, and a second interlayer insulating film on a semiconductor substrate in this order, and using the hydrogen-containing oxide film as an etching stopper film. Dry etching the second interlayer insulating film to form a wiring groove in the second interlayer insulating film;
Forming a trench wiring by embedding a metal material in the wiring trench. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a reactive gas which is an organic compound of halogen and does not contain hydrogen is used in said dry etching. 4. The method according to claim 3, wherein the insulating material to be etched or the interlayer insulating film is a silicon oxide film containing no hydrogen. 5. The hydrogen-containing oxide film according to claim 1, wherein
2. The method according to claim 1, wherein the composition is composed of silsequiosan.
The method for manufacturing a semiconductor device according to claim 1. 6. A step of laminating and forming a hydrogen-containing oxide film and an organic insulating film on a semiconductor substrate, and laminating a first mask layer and a second mask layer in this order. Forming on the surface of the insulating film, etching and transferring a predetermined pattern of a resist mask formed on the second mask layer to the second mask layer, and removing the resist mask after the etching transfer. Dry etching the organic insulating film using the second mask layer as an etching mask and the hydrogen-containing oxide film as an etching stopper film to form a wiring groove in the organic insulating film; Forming a trench wiring by embedding a metal material in the semiconductor device. 7. The method according to claim 6, wherein the first mask layer and the second mask layer are a hydrogen-containing oxide film and a silicon oxynitride film, respectively. 8. The hydrogen-containing oxide film is formed of hydrogen
7. The composition according to claim 6, wherein the composition is composed of silsequiosan.
8. A method for manufacturing a semiconductor device according to claim 7. 9. The method according to claim 6, wherein the organic insulating film is made of fluorinated amorphous carbon, benzylcyclobutene or organic polysilazane, which is a low dielectric constant film. A method for manufacturing a semiconductor device according to claim 1.