JPH0719779B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a buried contact on a semiconductor region.

[Conventional technology]

Conventionally, as shown in FIG. 3 (a), a buried contact of this type has, for example, an element region and an n ⁺ diffusion layer 5 formed in a predetermined region of a P-type silicon substrate 1 and then an insulating film 6 formed on the entire surface of the substrate.
To form a contact hole on the n ⁺ diffusion layer 5. Next, for example, a phosphorus-doped polycrystalline silicon 13 having a thickness of 1 μm is grown by using a mixed gas of PH ₃ and SiH ₄ by the LPCVD method, and reactive ion etching is performed using a mixed gas of CF ₄ and oxygen. The phosphorus-doped polycrystalline silicon is removed to expose the insulating film 7 as shown in FIG. 3 (b). Finally, aluminum 11 containing, for example, 1% of silicon is deposited to a thickness of 1 μm by a sputtering method and patterned into a predetermined shape by a photo-etching technique to obtain a semiconductor device of FIG. 3 (c). It was

[Problems to be Solved by the Invention]

In the above-mentioned conventional technique, the material for obtaining contact with the n ⁺ diffusion layer 5 on the P-type silicon substrate 1 and the material for filling the contact hole are shared by the phosphorus-doped polycrystalline silicon 13, so that it is sufficient on the n ⁺ layer 5. Although low contact resistance can be obtained, it cannot be used as a rectifying contact on the P ⁺ layer. Further, if boron-doped polycrystalline silicon is used instead of the phosphorus-doped polycrystalline silicon described above, good contact can be obtained on the P ⁺ layer, but conversely, rectifying contact is obtained on the n ⁺ layer. Thus, if a low resistance contact is realized with polycrystalline silicon doped with one conductivity type impurity and a contact hole is to be buried, it is only applicable to a single conductivity type semiconductor device. was there.

If a buried contact is to be formed in a CMOS type semiconductor device by the conventional technique, it is necessary to form the n-channel element region and the P-channel element region in completely independent steps from the opening of the contact hole to the filling. The number of steps increases, and the manufacturing cost also increases. In this case, it is conceivable to fill the contact holes with non-doped polycrystalline silicon capable of obtaining a resistive contact for both conductivity type semiconductor regions. Resistance is formed,
The actual contact resistance is too high to be used.
As described above, the conventional technique is not practical for the CMOS type semiconductor device.

〔Purpose〕

An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method of manufacturing a semiconductor device capable of simultaneously realizing low resistance contacts and contact hole burying even in semiconductor regions of different conductivity types.

[Means for Solving the Problems]

The semiconductor device manufacturing method of the present invention includes a step of forming a refractory metal compound that makes electrical contact at openings on different conductivity type regions, and impurities of the same conductivity type in contact holes on each conductivity type region. A step of adding ions, a step of forming an oxide layer in the contact hole and heat treatment, a step of forming a contact hole burying layer on the substrate, and a step of exposing the refractory metal compound in a region other than the contact hole portion. And a step of forming a wiring metal film on the entire surface and then patterning the metal film and the refractory metal compound into a predetermined shape.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

As shown in FIG. 1 (a), after forming a field oxide film 3 on a P-type silicon substrate 1 to form element regions separately,
N well 2, n ⁺ diffusion layer 5 and P ⁺ diffusion layer 4 in predetermined positions
Are formed by using an ion implantation method. After forming the insulating film 6 on the surface of the substrate 1, openings are formed in the insulating film 6 on the n ⁺ diffusion layer 5 and the P ⁺ diffusion layer 4 by a photoetching method. Next, FIG. 1 (b)
After depositing a tungsten silicide 7 having a film thickness of 1000 Å by a sputtering method as described above, a photoresist 8 having an opening on the P ⁺ diffusion layer 4 is provided as shown in FIG. Dose amount 1 × 10 ¹⁵ c
Implant m ^-2 boron ions. After peeling off the photoresist 8, a photoresist 9 is formed on the entire surface again, and only the photoresist on the n ⁺ layer 5 is removed as shown in FIG. 1 (d), for example, energy 70 KeV, dose amount 1 × 10 ¹⁶ cm. ^-2
Implant phosphorus ions. After stripping the photoresist 9, a SiH ₄ gas is used by the CVD method, for example, a film thickness of 1000Å
Grow a silicon dioxide film. Here, the silicon dioxide film is a cap for preventing the impurities implanted from the tungsten silicide layer 7 from coming out during the heat treatment. Heat treatment is performed in nitrogen at 900 ° C. for 5 minutes to activate and diffuse the implanted boron ions and phosphorus ions.
After removing the silicon dioxide film with a buffered hydrofluoric acid solution, LPCV
1μ of polycrystalline silicon film 10 using SiH ₄ gas by D method
m is deposited. At this time, the thickness of the polycrystalline silicon film is
It is desirable that it is at least ½ or more of the length of the contact hole in the short side direction. Further, the conductivity type impurity concentration of polycrystalline silicon 10 may be arbitrary. The polycrystalline silicon film
10 is etched back by reactive ion etching using a mixed gas of CF ₄ and oxygen, and tungsten silicide 7 is formed in a region other than the contact hole as shown in FIG. 1 (e).
Expose. Thereafter, aluminum 11 containing 1% of silicon is deposited to a thickness of 1 μm by a sputtering method, and aluminum 11 and tungsten silicide 7 are patterned into a predetermined shape by a photo-etching technique as shown in FIG.

Next, a second embodiment of the present invention will be described with reference to FIG.
After obtaining FIG. 1 (d) by the same procedure as in the first embodiment, the photoresist 9 is peeled off and a silicon dioxide film having a film thickness of 1000 Å is grown by the CVD method using SiH ₄ gas.
By the LPCVD method, for example, a mixed gas of B ₂ H ₆ , PH ₃ and Si (OC ₂ H ₅ ) ₄ is used to deposit a BPSG film 12 having a thickness of 1 μm,
Reheat of the BPSG film 12 is performed in nitrogen at 10 ° C. for 10 minutes, and heat treatment is also performed to activate boron ions and phosphorus ions ion-implanted in the contact hole portion. The BPSG film 12 and the underlying silicon dioxide film are etched back by reactive ion etching using a mixed gas of CF ₄ and hydrogen,
As shown in FIG. 2A, the tungsten silicide is exposed in a region other than the contact hole. Aluminum 11 containing 1% of silicon is deposited to a thickness of 1 μm by a sputtering method, and aluminum 11 and tungsten silicide 7 are patterned into a predetermined shape by a photo-etching technique.
The semiconductor device shown in FIG.

〔The invention's effect〕

As described above, the present invention provides a CMOS semiconductor device in which a material for making a contact and a material for filling a contact hole are made of tungsten silicide and a separate material such as polycrystalline silicon or a BPSG film, respectively. There is an effect that a practical method of manufacturing a buried contact can be provided.

[Brief description of drawings]

1 (a) to 1 (f) are longitudinal sectional views of a semiconductor device showing a first embodiment of the present invention in the order of steps, and FIGS. 2 (a) to 2 (b).
Is a vertical sectional view of the semiconductor device showing the second embodiment in the order of steps, and FIGS. 3A to 3C are vertical sectional views of the semiconductor device showing the conventional technique in the order of the steps. 1 ... P-type silicon substrate, 2 ... n well layer, 3 ... field oxide film, 4 ... P ⁺ diffusion layer, 5 ... n ⁺ diffusion layer, 6
... Insulating film, 7 ... Tungsten silicide layer, 8, 9 ...
… Photoresist, 10 …… Polycrystalline silicon, 11 …… Aluminum wiring layer, 12 …… BPSG layer, 13 …… Phosphorus-doped polycrystalline silicon.

Claims (1)

[Claims] 1. A step of forming an opposite conductivity type region and a one conductivity type region on a one conductivity type semiconductor substrate, a step of forming an insulating film on the semiconductor substrate, the opposite conductivity type region and the one conductivity type region. A step of forming an opening in the insulating film above, a step of forming a refractory metal compound layer on the one conductivity type semiconductor substrate, a step of forming a buried layer filling the opening, and a region other than the opening A step of exposing the refractory metal compound layer, and a step of forming a wiring metal film on the semiconductor substrate,
A method of manufacturing a semiconductor device, comprising: patterning the metal film and the refractory metal compound layer into a predetermined shape.