JPS62298110A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a highly reliable electrode wiring having low contact resistance by a method wherein the polysilicon or the amorphous Si, which will be turned into the source of impurities to be used for a shallow diffused layer, is converted into a metal by reduction of the gas containing metal. CONSTITUTION:A contact hole 4 is provided on the insulating film 3 located on an Si substrate 1. A polycrystalline Si film 5 is formed in the hole 4 and on the insulating film 3, impurities are ion-implanted into the polycrystalline Si film, then a heat treatment is performed, and a shallow diffusion layer 2 is formed on the substrate 1. Subsequently, the polycrystalline Si film on the region other than the hole 4 is removed, and the polycrystalline Si film is converted into a w-film by a silicon reducing reaction using the gas formed by diluting WF6 with Ar. Besides, W is deposited in the hole 4 using the gas containing WF6 and t2, and then an Al wiring electrode 7 is formed. As a result, a highly reliable electrode wiring, having the low contact resistance for the microscopic contact with a shallow diffused layer 2, can be formed.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a method of manufacturing a high-density, large-scale integrated semiconductor integrated circuit having shallow junctions and fine contacts.

Conventional Technology A known method for forming shallow junctions in minute contact holes is to introduce impurities into polycrystalline silicon by ion implantation, etc., and then heat treat the polycrystalline silicon as a diffusion source to form a shallow diffusion layer. There is. This is shown in FIG. 8 is a semiconductor substrate, 9 is a shallow diffusion layer,
Polycrystalline silicon film 12 is formed as a source of impurities.

10 is an insulating film, and 13 is a wiring electrode.

With this method, a shallow junction of about 0.1 μm or less can be formed in a single crystal semiconductor substrate for p-type and n-type impurities such as boron and arsenic. However, it has the following drawbacks. When electrode wiring 13 such as A1 is formed in the contact hole of the diffusion layer, due to the presence of a natural oxide film on polycrystalline silicon 12 and the high resistance of polycrystalline silicon 12, the λg electrode wiring 13 and polycrystalline Contact resistance with silicon 12 increases. In a further fine contact hole, as shown in FIG. 13, when forming the J electrode wiring 13, a cavity 14 called a void is formed, and in severe cases, the Al electrode 13 may be disconnected. At present, most electrodes such as A1 are formed by sputtering, so this phenomenon cannot be prevented. Therefore, at present, there is no effective means for forming a highly reliable electrical wiring with low contact resistance in a fine contact hole having a shallow diffusion layer.

Problems to be Solved by the Invention The present invention has been made in view of the drawbacks of the conventional art, and its purpose is to form an electrode with low contact resistance and high reliability in a shallow diffusion layer by a simple method. .

Means for Solving the Problems In order to solve the above problems, the present invention forms polycrystalline silicon or amorphous silicon on a semiconductor substrate, then introduces impurities, and forms a shallow diffusion layer using this as a source. do.

Thereafter, the polycrystalline silicon or amorphous silicon is converted into the metal using a silicon reduction reaction of a gas containing metal.

Operation The present invention can form a highly reliable electrode with low contact resistance in a shallow diffusion layer by the above-described method.

Embodiment FIG. 1 is a sectional view of an extremely fine contact in which an electrode is formed on a shallow diffusion layer in an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a shallow diffusion layer, 3 is an insulating film, 4 is a contact hole, 6 is a polycrystalline silicon film, 6 is a tungsten film, and 7 is a wiring electrode. The manufacturing method will be explained based on FIGS. 2 to 9.

In FIG. 2, 1 is a semiconductor silicon substrate, 3 is an insulating film, and a contact hole 4 is formed therein.

In FIG. 3, a polycrystalline silicon (Sl) film 5 may be used over the entire surface, and an amorphous silicon film may be used instead of the thick silicon film 6.

In FIG. 4, impurities such as arsenic and boron are ion-implanted, and the energy of the implantation is adjusted so that the impurity peaks in the polycrystalline silicon film S.

This situation is shown in FIG. The horizontal axis shows polycrystalline silicon and single crystal semiconductor substrate, and the vertical axis shows arsenic concentration. Since the channeling effect is suppressed in the polycrystalline silicon 5, almost no arsenic as an impurity enters the single crystal semiconductor substrate 1. Naturally, the same applies when the impurity is boron. Polycrystalline material is formed by heat treatment in Figure 5.
Arsenic in 9-5 is diffused into semiconductor silicon substrate 1. This one can be formed. Polycrystalline silicon 5 becomes a diffusion source. This situation is shown in FIG. A shallow arsenic diffusion layer 2 (50
A thickness of 0 A) is formed in the single crystal semiconductor substrate 1.

In FIG. 6, after coating the entire surface with a coating film such as a resist, a resist 8 is selectively left only in the contact hole 4. Subsequently, in FIG. 7, the excess polycrystalline silicon film is removed using the resist film 8 as a mask, leaving only the contact hole 4 with the polycrystalline silicon film 5. After removing the resist film 8, as shown in FIG. 8, a gas prepared by diluting WF 6 (tungsten hexafluoride) with Ar (argon) is reacted with the polycrystalline silicon film 5 to deposit a tungsten film. That is, 2W
F6+3s1→2W+3S process Using the silicon reduction reaction of F4, tungsten or the like is selectively grown only on the side and bottom surfaces of the contact hole 4. This reaction converts polycrystalline silicon 5 into tungsten 6. Although this figure shows a portion of the polycrystalline silicon 5 still remaining, it goes without saying that all of the polycrystalline silicon 5 may be converted to tungsten 6. A detailed explanation using FIG. 12 shows that most of the polycrystalline silicon layer is converted into tungsten 6. In FIG. 12, a thin polycrystalline silicon film 5 remains at the interface between the diffusion layer 2 and the tungsten 6. Unfortunately, the arsenic contained in the polycrystalline silicon 5 piles up at the interface between the tungsten 6 and the single crystal semiconductor substrate. In FIG. 8, after tungsten is deposited by a silicon reduction reaction, WF6 and a gas containing H2 (hydrogen) are reacted. That is, tungsten 6 is further grown using the hydrogen reduction reaction of WF6+ 3H2-W+6HF. At this time, the contact hole 4 can be completely filled with tungsten 8 as shown in FIG. 8 because it grows from the bottom and side surfaces as well.

In FIG. 9, a mu E wiring electrode 7 is formed.

In the structure of Al electrode wiring 7/tungsten 6/polycrystalline silicon 5/shallow diffusion layer 2 formed by such a manufacturing method, the silicon layer underlying the tungsten reacts with WF6 and is converted to tungsten. Because
Contact characteristics between tungsten and the underlying silicon layer,
In particular, contact resistance is reduced. Furthermore, as shown in FIG. 12, since the highly concentrated impurity shrinks at the interface between the tungsten 6 and the shallow diffusion layer 2, this effect is even greater. In this structure, the contact resistance is less than 1 compared to when there is no tungsten 6. This tungsten 6 can also be used as an electrode to selectively fill contact holes.
It becomes possible to form highly reliable electrode wiring without disconnection for fine contacts having shallow diffusion layers. In this embodiment, an example is shown in which WF6 is used as the metal-containing gas in FIG. 8, but other gases include MoF6.
゜Similarly using Mo(Go)6 and W(Go)6
or W can be deposited.

Effects of the Invention As mentioned above, according to the present invention, it is possible to form a highly reliable electrode wiring with low contact resistance in a shallow diffusion layer by a simple method. Therefore, it becomes easy to realize a high-density, large-scale semiconductor integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a fine contact having a shallow diffusion layer according to an embodiment of the present invention, and FIGS. 2 to 9 are cross-sectional views showing the manufacturing process of the fine contact having a shallow diffusion layer. 12 are shallow diffusion impurity distribution diagrams according to an embodiment of the present invention, and FIG. 13 is a sectional view of a fine contact having a shallow diffusion layer formed by a conventional manufacturing method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Shallow diffusion layer, 3... First insulating film, 4... Contact hole, 5...・Polycrystalline silicon film, 6...
...Tungsten film, completed...Wiring electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person! −
--Handle body board 2-11 Shallow plate (Tongue 3--1 apricot bullet (Section 4- Contact hole layer 5--Polycrystalline silicon film b--Tungsten film 7--Wiring electrical supply Figure 1 wa Figure 10 Figure 8... - Sheep return rod slope 9 - - Shallow extraction 4 similar tongue 10... Zetsuya C Saki / 1 - Ko'J9 Gutohole 12... Taikoin silicon genus 13 -・-Sai #L Electric Winter Rabbit No 4-・-Sora-nq Figure 13

Claims (1)

[Claims] A step of depositing polycrystalline silicon or amorphous silicon on a semiconductor substrate, a step of introducing impurities into the polycrystalline silicon or amorphous silicon, and a step of depositing the polycrystalline silicon or amorphous silicon on the semiconductor substrate using the polycrystalline silicon or amorphous silicon as a source. A method for manufacturing a semiconductor integrated circuit, comprising the steps of diffusing the impurity and converting the polycrystalline silicon or amorphous silicon into the metal using a silicon reduction reaction of a metal-containing gas.