JPH03224221A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase an impurity concentration in the surface of an impurity diffused region and to contrive a reduction in a contact resistance by a method wherein impurity containing compound gas is introduced in the impurity diffused region exposed in a connection hole and an impurity adsorption layer is formed on the impurity diffused region. CONSTITUTION:An impurity diffused region 2 is formed in a silicon semiconductor substrate 1. Then, an insulating film 3 is formed, a photoresist 4 is applied, the film 3 is etched, a connection hole 5 is formed and part of the layer 2 is selectively exposed. Then, the resist 4 is removed and thereafter, compound gas containing an impurity, such as AsH3, AsCl3 or the like or B2H6, BCl3 or the like, is introduced in a wafer held at a prescribed temperature and an impurity adsorption layer 6 is formed on the region 2. After this, the hole 5 is filled with a high melting point silicide film or the like and a wiring 7 is formed. Thereby, an impurity concentration in the surface of a layer diffused from the layer 6 is increased and a contact resistance is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device having a connection hole between the eyebrows of a conductive band, and particularly relates to a method of embedding a connection hole with low contact resistance.

[Conventional technology]

A conventional method for manufacturing a semiconductor device will be explained using FIGS. 2(a) to (C1). As shown in FIG. b
After forming the connection hole 14 as shown in FIG. 2 (C1), aluminum (AI), silicide, or high melting point metal wiring 15 is formed as shown in FIG. 2 (C1).

[Problem to be solved by the invention]

In submicron devices and chairs, the depth of the impurity diffusion layer 12 shown in FIG. A phenomenon was observed in which the junction breakdown voltage of the diffusion layer 12 decreased. Further, when the wiring 15 is a silicide wiring or a high melting point metal wiring, the impurity concentration decreases at the interface of the silicon impurity diffusion layer 12 in the connection hole 14, and the contact resistance between the wiring 15 and the impurity diffusion layer 12 increases.

[Means to solve the problem]

In view of the above-mentioned problems of the conventional technology, the present invention increases the surface impurity concentration of the impurity diffusion region (first conductive band layer) formed in the substrate, and connects it to the wiring (second conductive band layer). An object of the present invention is to provide a conductor device that can lower the contact resistance of the semiconductor device.

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes forming a first conductive band layer and an insulating film thereon, exposing a part of the first conductive band layer, and opening a connection hole. a first step of forming an active surface on the surface of the connection hole; a third step of supplying a gas containing an impurity component to the active surface to form an impurity adsorption film; and a fourth step of filling the connection hole with a second conductive band layer.

Preferably, annealing is performed after the third step or after the fourth step to form an impurity diffusion layer in the first conductive band layer.

In addition, if the second conductive band layer is made of high melting point metal silicide such as tungsten silicide, by providing an impurity adsorption layer on this conductive band layer and annealing, impurities can be diffused into the high melting point metal silicide. The resistance of the conductive band layer can be lowered.

[Effect]

Although the impurity concentration on the surface of the layer diffused from the adsorption layer containing impurities is very high at 10''/cff1 or more, the diffusion layer can be made deep, so there is no need for alloy spikes or treatments that increase contact resistance due to a decrease in surface concentration.

〔Example〕

Embodiments of the present invention will be described based on FIGS. As shown in FIG. 1 (al), an impurity diffusion region 2 is formed in a silicon semiconductor substrate 1.
The impurities are, for example, N-type impurities such as arsenic (Aa), phosphorus (P), and antimony (Sb), or P-type impurities such as boron (B).

Next, as shown in FIG. 1 fbl, an insulating film 3 is formed.

This insulation WJ, 3 may be formed before forming the impurity diffusion region 2.

Next, as shown in FIG. selectively expose a portion of the

Next, as shown in Figure 1 (dl), the photoresist 4 is removed, and then an impurity adsorption layer 6 is laminated. The impurity diffusion layer 2 is formed by holding the wafer in a reaction device maintained at a temperature of
An impurity adsorption layer 6 is formed thereon. For example, in the case of an N-type adsorption layer, Arsone (ASH3), Arsenic trichloride (AsC
1*), phosphine (Pl+3): phosphorus chloride (PCJ3)
), arsenic trifluoride (AgF2) and phosphorus pentafluoride (PFS).
) is introduced. In addition, in the case of a P-type dyed layer, diborane (BAH,) boron dichloride < B
A gas containing a P-type element such as CI, ) or boron trifluoride (BFs) is introduced. The production pressure may be a high pressure of 1 atm or more, or a reduced pressure of latm or less. Furthermore, after forming an impurity adsorption layer, silane (Si84),
Disilane (SiJJ, dichlorosilane (SiHilJz)
) or trichlorosilane (SiHC:ii) can be introduced to grow a silicon thin film.

Before forming the impurity adsorption layer 6, 600 ml of natural oxide film existing on the surface of the impurity diffusion layer 20 of the contact hole
Gas phase etching can also be carried out by introducing a gas such as hydrogen (H2) or hydrogen chloride (HCf) into an atmosphere at a temperature of ~1000°C.

Further, after forming the impurity adsorption layer 6, the impurity can be diffused to a desired depth within the impurity diffusion layer by heat treatment.

Next, as shown in FIG. 1 (el), wiring 7 is formed.

The wiring 7 is made of aluminum (Aj), tungsten (14
), high melting point metals such as molybdenum (Mo), copper (Cu),
Gold (Au), silver (Ag) and tungsten silicide (
WSiz), molybdenum silicide (MoSiz), titanium silicide (TiSiz), and other metal silicides.

The thickness of the impurity adsorption layer 6 in FIG. 1 (dl, (e)) is less than 100 Å and can be made very thin.Furthermore, the impurity can be diffused very shallowly on the surface of the N2.Also, inside the silicon film It is also possible to stack this silicon film in a heavily doped state.

Although FIG. 1 (al to tel) describes a silicon substrate, the present invention can also be applied to a compound semiconductor such as gallium arsenide (GaAs).

FIG. 3 shows, for example, after an impurity adsorption layer 34 is provided in an opening defined by an impurity diffusion region 32 formed on the surface side of a semiconductor substrate 310 and a patterned insulating film 33, This is an example in which metal solicide 36 is deposited. FIG. 3 fal is a step of exposing a part of the impurity diffusion region 32 (this may be a well frequency region) as explained in FIG. 1, and is also shown in FIG.
is a step of providing an impurity adsorption layer 34 on the surface of the activated impurity diffusion region 32. FC+ in FIG. 3 is an annealing process, which is a step of forming an impurity diffusion layer 35 by performing solid phase diffusion using the impurity adsorption layer 34 as a diffusion source;
di is a step of depositing metal silicide 36 as a wiring material electrically conductive to impurity diffusion layer 35. Fourth
The methods shown in FIGS. 3A to 3D are essentially the same as those shown in FIGS. The difference is that annealing is performed after depositing. Figures 5 and 6
The figure shows an example in which a semiconductor film is provided as the wiring material. In the case of Fig. 5, Fig. 5 (al and +b+ are
This process is the same as that shown in Figures (al and bl). In Figure 5(C), semiconductor films 55 and 56 doped with impurities are formed on the impurity adsorption layer 54. In this case, the silane gas (Si)14) and diporane gas (B211
By supplying a gas mixed with 6) onto the substrate at a substrate temperature in the range of 800 to 1000°C, a P'-type epitaxial layer 55 is formed on the impurity diffusion region 52 and on the insulating film 53. A P° type polynolyric film is formed respectively to constitute the wiring material. After this, Figure 5 (
By performing the annealing process at d+, the contact resistance is further reduced. The process shown in FIG. 6 shows a case where an impurity adsorption layer 64 and semiconductor films 65 and 66 are laminated to provide wiring. In FIG. 6(a), a sixth [ff1
(In bl, for example, an adsorption layer 64 of poron as an impurity)
and semiconductor films 65 and 66 are sequentially stacked. 6th after this
In the figure (C1), an annealing process is performed to activate poron, and a wiring made of a silicon film is provided.

In this case, similarly to the process shown in FIG.
On top of this, there is a P′ type Evita Kinyal film and an insulating film 63.
A P''' type polysilicon film is formed on the top and serves as a wiring material. Figures 7 and 8 show a portion consisting of an impurity adsorption layer and a semiconductor film as a semiconductor substrate and a wiring material. This is an example in which the film is used as a buffer layer.

In this case, a high melting point metal silicide such as tungsten silicide is used as the wiring material. FIG. 7 shows that after activating the surface of a semiconductor layer whose surface is partially exposed, a semiconductor film is selectively formed only on this exposed semiconductor layer, and an impurity adsorption layer is further formed on the surface of this semiconductor layer. This figure shows the process of forming a Huffer layer by providing a Huffer layer. FIG. 7 (Al is a process for removing the native oxide film on the surface of the partially exposed impurity diffusion region 72. FIG. 74, dichlorosilane gas (SrH
zClz) and hydrogen gas (H2), and an impurity adsorption layer 75 is further provided on the semiconductor film 74. Note that the semiconductor film 74 can be made to have even lower resistance by adding, for example, diporane gas (Bal16) to the above gas. Next, in FIG. 7fd), an annealing process is performed to form a Huffer layer 76 in which impurities are uniformly distributed, and finally, in FIG. 7fd), metal silicide 77 is deposited on the buffer 1176 and the insulating film 73. and configure the wiring. The method shown in FIG. 8 is essentially the same as that shown in the method shown in FIG. 7, but differs from the method shown in FIG. 7 in that the semiconductor N85 is provided after forming the impurity adsorption layer 84. By using the methods shown in FIGS. 7 and 8, not only the contact resistance between the metal silicide and the semiconductor substrate is reduced, but also the level difference in the contact area becomes gentler, and the level difference in the latitude line near the edge of the insulating film is reduced. It is also effective in preventing cuts. In addition, in the examples shown in FIGS. 7 and 8, an impurity adsorption layer was formed,
It is also possible to omit the formation of an impurity adsorption layer by forming a semiconductor film while adding a high concentration of impurities into the semiconductor film.

Another embodiment of the present invention will be described with reference to FIG. That is, in FIG. 9, B (Poron) is applied to the surface of the 31 substrate 95.
After forming a P'5iil region 97 that forms a source or drain region by ion implantation, 5i (h) is provided as a field insulating film 93, and an impurity-doped single crystal thin film (P 'Si single crystal thin film) 92 and a metal electrode 94 are provided.The method for forming the P″St single crystal thin film 92 is to apply gaseous dichlorosilane (SiCfzlh) containing semiconductor component Si and impurities to the active surface of the semiconductor layer surface. After supplying gaseous diporane (BJ6) containing component B to form an adsorption layer containing semiconductor components and impurity components, the impurity components contained in the adsorption layer are solid-phase diffused into the semiconductor layer by heating to form a P''Si single crystal thin film. It is effective to form a 5i-H-C1-based normal pressure or reduced pressure CV
lar beam equitaxy). In this case, selective growth can be performed in the contact opening using the field insulating film 93 as a mask.

As described above, this embodiment has a structure in which the metal electrode 94 and the p'5i61 region 97 are in contact with each other through the P"ii single crystal thin film 92 formed at the contact portion on the P"Si region 97. ing.

[Effects of the Invention] As explained above, the present invention can increase the concentration of surface impurities in the pure diffusion pattern, and therefore can lower the contact resistance with wiring. When performing high-temperature heat treatment after forming the wiring, even if the impurity in the impurity diffusion layer diffuses into the wiring, a sufficiently low contact resistance can be maintained because the initial surface concentration is sufficiently high. Further, since the depth of the impurity diffusion layer in the region of the connection hole 5 can be controlled as desired, alloy spikes can be prevented by using aluminum wiring.

[Brief explanation of drawings]

Figure 1 (fat to tel) is a sectional view showing the process order of the semiconductor device manufacturing method of the present invention, Figure 2 (al~(C1 is a sectional view showing the process order of the conventional semiconductor device manufacturing method) (al ~ (dl, Figure 4 fa) ~ Id), Figure 5 f
al ~ Fdl, Figure 6 (al ~ (C), Figure 7 (a
1-(d) and 8 (al-tel are respectively process-order sectional views showing another embodiment of the present invention, and FIG. 9 is a structural sectional view showing still another embodiment. 12.32. 42, 52, 62, 72.82.97...
・Impurity diffusion region! 3, 33.43, 53.63, 73
．． 8393...Insulating film or higher

Claims (11)

[Claims] (1) A first step of forming a first conductive band layer and an insulating film thereon, exposing a part of the first conductive band layer to form a connection hole, and an active surface on the surface of the connection hole. a second step of forming an impurity adsorption film by supplying a gas containing an impurity component to the active surface; and a fourth step of filling the connection hole with a second conductive band layer. A method for manufacturing a semiconductor device comprising: (2) The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive band layer is an impurity diffusion layer region formed in the semiconductor substrate. (3) The method for manufacturing a semiconductor device according to claim 2, further comprising, before the fourth step, solid-phase diffusing impurity components contained in the impurity adsorption film into an impurity diffusion layer by heating. (4) The method for manufacturing a semiconductor device according to claim 2, further comprising, after the fourth step, solid-phase diffusing impurity components contained in the impurity adsorption film into an impurity diffusion layer by heating. (5) The semiconductor according to claim 2, wherein the third step is a step of supplying a gas containing a semiconductor component and a gas containing an impurity component to the active surface to form an adsorption film containing the semiconductor component and the impurity component. Method of manufacturing the device. (6) The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive band layer is a silicide of a high melting point metal. (7) Remove the inert coating present on the surface of the second conductive band layer and remove it to the active surface, supply a gas containing impurity components to the active surface to form an impurity adsorption film, and heat 7. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of diffusing impurities constituting the impurity adsorption film. (8) forming a first conductive band layer and an insulating film thereon;
a first step of exposing a part of the first conductive band layer to form a connection hole; a second step of forming an active surface on the surface of the connection hole; and a step of supplying a gas containing an impurity component to the active surface. a third step of supplying gas to form an impurity adsorption film, further supplying gas intermittently to form an epitaxial layer on the impurity adsorption film; and heating to remove impurities from the impurity adsorption film and the epitaxial layer. A method for manufacturing a semiconductor device, comprising a fourth step of forming a diffusion layer, and a fifth step of filling the connection hole with a second conductive band layer. (9) The third step is a step of intermittently supplying gas to the active surface to form an epitaxial growth layer, and further supplying a gas containing impurity components to form an impurity adsorption film on the epitaxial growth layer. The method for manufacturing a semiconductor device according to claim 8. (10) The semiconductor device according to claim 8, wherein the third step is a step of supplying a gas containing at least an impurity component and a gas containing a semiconductor component to the active surface to form an impurity-doped epitaxial growth layer. manufacturing method. (11) forming a first conductive band layer and an insulating film thereon;
a first step of exposing a part of the first conductive band layer to form a connection hole; a second step of forming an active surface on the surface of the connection hole; and a step of supplying a gas containing an impurity component to the active surface. a third step of supplying gas to form an impurity adsorption film, and further supplying gas intermittently to form an epitaxial layer on the impurity adsorption film; and repeating the third step to fill the connection hole and form the insulating film. A fourth step of providing this composite layer also on the film, and a fifth step of forming a layer that makes contact with the first conductive band layer by using the composite layer as an impurity diffusion layer by heating. Method.