JPH07193164A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPH07193164A
JPH07193164A JP33215893A JP33215893A JPH07193164A JP H07193164 A JPH07193164 A JP H07193164A JP 33215893 A JP33215893 A JP 33215893A JP 33215893 A JP33215893 A JP 33215893A JP H07193164 A JPH07193164 A JP H07193164A
Authority
JP
Japan
Prior art keywords
electrodes
semiconductor
carrier
container
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33215893A
Other languages
English (en)
Inventor
Toshio Morishige
季夫 森重
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33215893A priority Critical patent/JPH07193164A/ja
Priority to US08/361,970 priority patent/US5506448A/en
Priority to KR1019940036868A priority patent/KR0145641B1/ko
Publication of JPH07193164A publication Critical patent/JPH07193164A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/013—Alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/15165—Monolayer substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

(57)【要約】 【目的】本発明は多品種少量生産に対応して、容器の共
用化を図りパッケージ数を減らす方法を提供し、生産変
動に対応するものである。 【構成】半導体素子搭載用キャリアに半導体素子を搭載
し、素子の内部電極とキャリアの内部電極とを金属細線
によって接続し、その後キャリア裏面に形成された格子
状電極と容器本体に形成されている対応する内部電極と
を半田、又は導電性樹脂等により固着することにより、
電気的、機械的に接続を行う。その後、キャップにより
蓋をし封止を行う。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明はセラミックス材料を用い
た半導体集積回路に関し特に半導体素子を容器に搭載す
る祭の取り付け構造を改造した半導体集積回路装置。
【０００２】
【従来の技術】図４は従来のこの種の半導体集積回路容
器を示す断面図である半導体素子４１はセラミクス容器
基体４２に半田等の共晶ロー材又はエポキシ樹脂等によ
る接着剤によって固着され、その後半導体素子の内部電
極と金属細線４４によって電気的に接続するための内部
電極４３を有し、その内部電極４３と容器の外部端子４
５は容器内部金属配線によって電気的に接続されてい
る。上記内部電極４３の配置はこの容器に搭載される半
導体素子４１の内部電極の配置と金属細線４４によって
接続出来る長さによって決まっている。金属細線により
電極間接続後、半導体素子を保護するため抵抗溶接等の
手段によって金属蓋又は共晶ロー材により封止されてい
る。
【０００３】
【発明が解決しようとする課題】しかしながら、半導体
素子の品種数は毎年増える傾向にありその半導体素子の
内部電極の配置が変わると毎回新しく容器を作る必要が
ある。更には、電極の配置が同じでも素子の寸法が変わ
ると新たに容器を作りなおす必要がある。そのため容器
の開発件数は増え、開発費は嵩み容器の種類も多くなり
半導体装置原価は悪くなる一方である。さらに積層セラ
ミックスの容器の単価も高いため少しの生産の変動にた
いし、少量の在庫でも多額の金額の在庫を持つことにな
る。また半導体素子の寸法は毎年大きくなり、容器の外
形寸法が決まっているため、組み立て工程において半導
体素子内部電極と容器の電極とを金属細線でつなぐとき
接続の為に用いられているキャピラリーが容器の一部、
例えば封止用リングに接触する場合があり容器に搭載で
きる素子の大きさに制限が出来ることになる。そのため
には、容器の外形寸法を大きくする必要がでてきて、実
装密度の悪化を招いている。本発明はかかる問題点に鑑
みてなされたものであって半導体素子の寸法にかかわら
ず細線接続ができ生産の変動に対しても短納期で対応出
来しかも在庫額の削減が可能となる半導体装置を提供す
るものである。
【０００４】
【課題を解決するための手段】本発明に係る半導体集積
回路容器は半導体素子を搭載し半導体素子内部の電極と
電気的に接続するために金属細線をつなぐ電極を素子搭
載面に有し、それと対向する面に上記内部電極と電気的
に接続されてなる格子状に配置された電極を有するキャ
リアと、このキャリアの格子状電極と１：１に対応した
電極を有する容器本体よりなることを特徴とする。
【０００５】
【実施例】次に本発明の実施例について添付の図面を参
照して説明する。
【０００６】図１は本発明の第一の実施例に係わる半導
体集積回路容器を示す縦断面図である。半導体素子を半
導体素子の電極と接続される電極を有し半導体素子搭載
面と対向する裏面に格子状に配列された外部電極を有し
ている回路基盤に共晶ロー材または樹脂接着剤等により
接合し、その後金属細線によって素子の内部電極とキャ
リア電極を接続する。その後、素子の搭載されたキャリ
アを１２容器本体の格子状に配列された電極に半田又は
導電性樹脂等によって、電気的、機械的に接続を行う。
そして、キャップ１５を被せ抵抗溶接等によって、封止
を行う。
【０００７】図２は本発明の第２の実施例である。素子
の、発熱に伴い熱放散性の良い容器が要求された場合に
対応した例である。第１の実施例の如く半導体素子２１
をキャリア２２に搭載したあと半田または導電性樹脂に
よって電気的、機械的に容器本体２３に接続しキャップ
２５によって封止を行う。
【０００８】図３は第３の実施例である。本発明による
半導体装置は単一の素子に限るものでは無く、複数の素
子３１をキャリア３２にそれぞれ搭載し一つの容器３３
に搭載するＭＣＭの例である。
【０００９】
【発明の効果】本発明において半導体素子を上述したキ
ャリアに搭載しその素子が搭載されたキャリアを半田等
の共晶合金又は導電性樹脂によって容器に固着搭載す
る。したがって本キャリアの外部の格子状電極の配置を
共通にしておけばキャリアを搭載する容器は共通の容器
を用いることが出来る。その結果容器品種数を大幅に削
減出来、半導体素子が少量多品種になっても在庫量の低
減が可能となる。また、キャリアの品種数も組立時にキ
ャピラリー等の空間的制限も無いため従来の容器の種類
よりは減り、価格的には、キャリアの寸法が小さいこと
から従来の容器より安いため、在庫金額は非常に少ない
ものとなる。おおよそ従来の１／１０にまで在庫金額を
減少させる効果がある。製造工期的にはキャリアの層数
は従来の容器の層数に比べりはるかに少ないこととキャ
リアの構造が外部電極として従来の容器のようにリード
の形態を持たないので製造工期も短く従来に比べ約半分
で短納期対応に適している。即ち、以上をまとめると従
来容器の高価な部分は共通化して種類を少くし大量に作
ることにより安くし種類の多くなる部分は安いキャリア
構造を用いることにより低価格の容器ができ上がること
になる。
【図面の簡単な説明】
【図１】本発明の実施例を示す半導体装置の構造を示す
縦断面図。
【図２】本発明の第二の実施例を示す縦断面図。
【図３】第３の実施例を断面図。
【図４】従来の半導体装置の構造を示す縦断面図。
【符号の説明】
１１ 半導体素子 １２ 半導体素子キャリア １３ 容器 １４ 接続部

Claims (4)

    【特許請求の範囲】
  1. 【請求項１】 ＬＳＩ素子及びＬＳＩ素子に形成された
    内部電極と金属細線によって電気的に接合された電極を
    一面に有し相対する他方の面には格子状の電極を有する
    基板よりなり該素子が該基板に固着されている半導体集
    積回路装置。
  2. 【請求項２】 請求項１の半導体装置の素子面および金
    属細線を樹脂により覆われた半導体集積回路装置。
  3. 【請求項３】 請求項１又は２のそれぞれの格子状電極
    に半田球を具備する半導体集積回路装置。
  4. 【請求項４】 請求項１，２又は３の半導体装置が当該
    装置の格子状の電極と半田によって接続された格子状電
    極を内部に有し、該内部電極と配線により電気的に接続
    されている外部電極を有する半導体容器に収納されてい
    る半導体集積回路装置。
JP33215893A 1993-12-27 1993-12-27 半導体集積回路装置 Pending JPH07193164A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP33215893A JPH07193164A (ja) 1993-12-27 1993-12-27 半導体集積回路装置
US08/361,970 US5506448A (en) 1993-12-27 1994-12-22 Semiconductor integrated circuit device having an improved packaging structure
KR1019940036868A KR0145641B1 (ko) 1993-12-27 1994-12-26 반도체 집적 회로 장치

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JP33215893A JPH07193164A (ja) 1993-12-27 1993-12-27 半導体集積回路装置

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Publication number Priority date Publication date Assignee Title
US5744752A (en) * 1995-06-05 1998-04-28 International Business Machines Corporation Hermetic thin film metallized sealband for SCM and MCM-D modules
US5739584A (en) * 1995-06-07 1998-04-14 Lsi Logic Corporation Multiple pin die package
EP0774888B1 (en) * 1995-11-16 2003-03-19 Matsushita Electric Industrial Co., Ltd Printed wiring board and assembly of the same
US6433411B1 (en) * 2000-05-22 2002-08-13 Agere Systems Guardian Corp. Packaging micromechanical devices
JP2002204053A (ja) * 2001-01-04 2002-07-19 Mitsubishi Electric Corp 回路実装方法、回路実装基板及び半導体装置

Citations (1)

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Publication number Priority date Publication date Assignee Title
JPH04315456A (ja) * 1991-04-15 1992-11-06 Hitachi Ltd 半導体装置の製造方法

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US4417392A (en) * 1980-05-15 1983-11-29 Cts Corporation Process of making multi-layer ceramic package
JPH0756887B2 (ja) * 1988-04-04 1995-06-14 株式会社日立製作所 半導体パッケージ及びそれを用いたコンピュータ
JP2772001B2 (ja) * 1988-11-28 1998-07-02 株式会社日立製作所 半導体装置
JPH02165675A (ja) * 1988-12-20 1990-06-26 Konica Corp イメージセンサー

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315456A (ja) * 1991-04-15 1992-11-06 Hitachi Ltd 半導体装置の製造方法

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US5506448A (en) 1996-04-09
KR0145641B1 (ko) 1998-11-02
KR950021298A (ko) 1995-07-26

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