JPH07192459A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the time required for the reading and the writing of data and to attain the speeding up of data access in a system in which the memory cell unit of an NAND type is consituted by connecting plural memory cells in series. CONSTITUTION:This device is a DRAM provided with a memory cell array in which memory cell units consituted by connecting plural dynamic type memory cells in series are arranged in a matrix and register cells RC1, RC0 provided in the ratio of one pair to the prescribed number of memory cell units and storing temporarily data read out from respective memory cells C1, C0, etc., of a corresponding memory cell unit and storing temporarily data to be written in respective memory cells of the memory unit. Further, the device is provided with a row address comparing circuit 2 and a decoder selecting circuit 3 and the row address of one before is compared with the newest row address. In the case where row addresses express the same memory cell unit, data are not read out from memory cells but are directly read out from register cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a semiconductor memory device using a memory cell unit (NAND type cell) configured by connecting memory cells in series.

[0002]

2. Description of the Related Art Conventionally, a DRAM in which a plurality of memory cells are connected in series to form a NAND type memory cell unit, and a plurality of these memory cell units are connected to bit lines to form a memory cell array It has been known. In this NAND type cell array system, the number of bit line contacts is smaller than that in a system in which individual memory cells are connected to bit lines, respectively, so that the cell area can be reduced.

By the way, in the NAND type cell array system,
When reading the data of the memory cell farther from the bit line contact in the memory cell unit, the cell data passes through the transistor portion of the memory cell on the bit line side of the memory cell. In the portion where the cell data passes, the data in the memory cell in that portion is destroyed. Therefore, a register for temporarily holding the data in the memory cell unit and rewriting the cell is required.

Then, in order to read the data of the memory cell, after reading the data from the memory cell to the register,
Data will be read from the register, and normal DR
It takes longer time to read data than AM.
The read cell data can be restored simultaneously with the amplification of the read data in the DRAM in which each bit is connected to the bit line. However, in the NAND type cell array method, the register data is stored in the cell separately from the read cycle. A write cycle is required. This also lengthens the time required to read the data.

Also in the data writing, the data in the memory cell is once read into the register, the data to be written in the register is written, and then the data in the register is written in the memory cell, which is the time required for writing the data. Becomes longer. That is, the NAND type cell array system has a problem that it takes time to access data.

[0006]

As described above, the conventional NA
In the ND type cell array type DRAM, there is a problem in that data transfer between the memory cell and the register is required at the time of reading and writing data, and it takes time to access the data.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to read data from and read data by a method of connecting a plurality of memory cells in series to form a NAND type memory cell unit. It is an object of the present invention to provide a semiconductor memory device capable of shortening the time required for writing and speeding up data access.

[0008]

The essence of the present invention is to utilize the data stored in the register as it is when continuously reading or writing the same address (or a near address).

That is, according to the present invention, a memory cell array in which a plurality of memory cell units each composed of a plurality of dynamic memory cells connected in series are arranged, and a set of memory cell units is provided in a ratio of one set. A semiconductor provided with a register cell for temporarily storing data read from each memory cell of a corresponding memory cell unit and temporarily storing data to be written in each memory cell of the memory cell unit In the memory device, the previous row address is compared with the latest row address, and when these row addresses represent the same memory cell unit, the data of the register cell is read directly instead of the memory cell in reading. When reading and writing, write the data in the memory cell to the register cell without reading it. And writes the Data transfers to the register cell.

Preferred embodiments of the present invention are as follows. (1) Data writing is performed in the same manner as the normal NAND type cell array method, and only data reading is performed as described above.
When the previous row address and the latest row address represent the same memory cell unit, read the data in the register cell directly instead of the memory cell. (2) Data read is performed in the same manner as the normal NAND type cell array method, and only data write is performed as described above.
When the previous row address and the latest row address represent the same memory cell unit, write the data to be written into the register cell without once reading the data in the memory cell into the register cell. (3) In addition to register cells that temporarily store data when reading and writing data from memory cells,
Provide a refresh register cell and select this refresh register cell when refreshing. (4) A plurality of memory cell units form a memory cell group, and register cells are provided in a ratio of one set to a predetermined number of memory cell groups and read from each memory cell of the corresponding memory cell group. The stored data is temporarily stored, and the data to be written in each memory cell of the memory cell group is temporarily stored. In this case, if the previous row address and the latest row address represent the same memory cell group,
In reading, the data in the register cell is read directly instead of in the memory cell, and in writing, the data in the memory cell is directly written in the register cell without being read in the register cell.

[0011]

According to the present invention, when row addresses representing the same memory cell unit are continuously selected, data is read directly from or written to the register cell without accessing the memory cell. be able to. Therefore, it is possible to perform high-speed reading and writing while omitting the time required to transfer the cell data from the memory cell to the register cell and restore the cell data from the register cell to the memory cell. When row addresses representing the same memory cell unit are not continuously selected, data read and write are performed in the same manner as in the normal NAND type cell array system.

By providing a register cell for refreshing separately from the register cell (main register cell), data in the main register cell is not destroyed at the time of refreshing, so that refreshing can be performed without impairing the effect of speeding up. it can.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a D according to the first embodiment of the present invention.
It is a figure which shows the circuit structure of RAM. In this embodiment, an example in which two memory cells are connected in series to form a memory cell unit is shown, but the number of memory cells connected in series can be appropriately changed.

In FIG. 1, the word lines for the two memory cells C0 and C1 are WL0 and WL1, respectively, the register cells for storing cell data are RC0 and RC1, and the register word lines which are their selection lines are RWL0 and RWL
Set to 1. Further, a sense amplifier (S / A) 6 and an equalizer (EQL) 7 are connected to one end of the bit line BL connected to the memory cell unit including the memory cells C0 and C1. Further, a selection gate driven by φT is inserted in the middle of the bit line BL.

The sense system is an open bit line system, and the bit lines BL are arranged on both sides of the sense amplifier 6. Although not shown in the figure, the bit line BL
A plurality of memory cell units are connected to the
The one-line configuration shown in is arranged in a plurality of columns in the word line direction.

The configuration up to this point is the same as that of a normal NAND type cell array system, but this embodiment is characterized by the way of driving by the circuits 1 to 5 shown in blocks. That is, the row address is input to the row address latch circuit 1 and the row address comparison circuit 2, and the decoder selection circuit 3 selectively drives the row decoder 4 and the register cell decoder 5 based on the output of the row address comparison circuit 2. . And
The row decoder 4 drives WL0 and WL1, and the register cell decoder 5 drives RWL0 and RWL1.

The row address latch circuit 1 is a circuit for holding the row address of the previous time, and is constructed as schematically shown in FIG. Here, the row address is RA
Of the four bits of 0, RA1, RA2, RA3, the upper 3 bits RA3, RA2, RA1 represent the row address of the unit cell, and the least significant bit RA0 represents the row address of the cell in the unit cell. That is, the case where one unit cell has two cells is shown. However, the latch of RA0 is not always necessary. The row address comparison circuit 2 is a circuit for comparing the previous row address held in the row address latch circuit 1 with a new row address when a new row address is input in the next cycle, and is shown in FIG. Is configured. Here, when φ = “H” and all addresses (RA1 to RA3) match, cout = “H”
Becomes

The decoder selection circuit 3 is constructed as shown in FIG. 4, and if the new row address and the row address one time before are different, the signal S0 for driving the row decoder 4 and the register cell decoder 5 are provided. Signal S to drive
1 is selected, and if the same address is selected, only S1 is selected.
Here, only when cout is “L” and φ is “H”, S
0 becomes "H".

The row decoder 4 selectively drives the word lines WL of the memory cells, and is constructed as shown in FIG. The register cell decoder 5 selectively drives the register word line RWL, and is configured as shown in FIG.

In such a configuration, the row address comparison circuit 2 compares the input new row address with the row address one time before, and the decoder selection circuit 3 uses the same word line (WL0, WL1). If not selected, the row decoder 4 and the register cell decoder 5 operate normally.

That is, the row decoder 4 raises the word line corresponding to the address, and the data is read in order from the memory cell near the bit line contact. When the read data is amplified by the sense amplifier 6,
The register cell decoder 5 raises the register word line corresponding to each address and writes the data of the memory cell into the register cell. When the reading of all the memory cells connected in the NAND type and the storage in the register cells are completed, the restore from the register cells is performed, and the word lines far from the bit line contacts fall in order.

Similarly for writing, word lines rise in sequence to store data in register cells, write data in target cells, and restore from register cells.

Here, the same word line (WL0, WL
If a row address that continuously selects 1) is input, the decoder selection circuit 3 selects only S1. At this time, the row decoder 4 does nothing. On the other hand, the register cell decoder 5 directly selects the register word line of the register cell in which the data corresponding to the address is stored to read the data from the register cell.

At this time, the sense amplifier 6 operates to amplify the data in the register cell and restore the data in the register cell, as in reading and restoring the cell data. Restoration from the register cell to the memory cell is performed after reading from the register cell.

After transferring the data to the DQ line, the bit line pair is equalized. At this time, RWL is set to "L" and the data in the register cell is not equalized. By doing this, even if the same row address is input again,
Data can be read from the register cell.

In the case of writing, if the same word line WL as the data stored in the register cell is selected, the data may be directly written in the register and restored in the memory cell. In this way, the trouble of temporarily transferring the data from the memory cell to the register cell is saved.

Also in the case of writing, when equalizing the bit line pair, RWL is set to "L" and the data in the register cell is not equalized. By doing so, even if the same row address is input again, the data can be read from the register cell.

Waveform diagrams in the case of reading of the first embodiment are shown in FIGS. 7 and 8. FIG. 7 shows a case where different row addresses are read after the first read. In this case, the second read is performed in the same manner as the first read. Then, after the second read, the restore is performed in the same manner as the restore after the first read.

FIG. 8 shows a case where the same row address is read after the first read. In this case, at the time of the second read, it is not necessary to transfer the data of the memory cell to the register cell, and the data is read directly from the register cell. Therefore, the read time is shorter than that of the first read. Become. Therefore, the time required for reading can be significantly reduced.

The read method as shown in FIG. 8 can be adopted not only when the two addresses are completely the same, but also when the upper 3 bits are the same, that is, when the addresses represent the same memory cell unit. If

Although not shown in the figure, in writing, when the new address is the same as the address one time before, the data of the memory cell is already stored in the register cell. The transfer of data can be omitted, and the data to be written can be written directly to the register cell. As a result, the time required for writing can be shortened.

As described above, according to the present embodiment, when the row address representing the same memory cell unit is continuously selected, the data is read from the direct register cell or the direct register cell is accessed without accessing the memory cell. You can write data to. Therefore, it is possible to omit the time required to transfer the cell data from the memory cell to the register cell and to restore the cell data from the register cell to the memory cell, and it is possible to significantly reduce the data access time. (Second Embodiment) Next, the DR according to the second embodiment of the present invention.
The AM will be described.

In this embodiment, the restoration from the register cell to the memory cell in the first embodiment is not performed until the address of the next word line is indicated.

FIG. 9 shows a waveform diagram in the case of reading according to the present embodiment. Also in this embodiment, as in the first embodiment, the row address latch circuit 1 holds the previous row address, and the row address comparison circuit 2 compares them when a new row address is input in the next cycle. To do. If the new row address is different from the one previously selected, the register cell is restored to the memory cell, and the read cycle of the new address is started. Same word line (WL
If a row address that continuously selects (0, WL1) is input, restoration is not performed. The register cell decoder 5 selects not the word line but the register word line of the register cell in which the data corresponding to the address is stored, and the data is read from the register cell.

At this time, the sense amplifier operates to amplify the data in the register cell, and restores to the register cell in the same manner as when reading or restoring the cell data.

After the data is transferred to the DQ line, the bit line pair is equalized. At this time, RWL is set to "L" and the data in the register cell is not equalized. By doing this, even if the same row address is input again,
Data can be read from the register cell.

In the case of writing, if the same word line WL as the data stored in the register cell is selected, the data is directly written in the register cell. The data newly written in the register cell is restored to the memory cell when a different row address is input next. In this way, the trouble of temporarily transferring the data from the memory cell to the register cell is saved.

If a different word line WL is selected,
Similar to reading, the data currently stored in the register cell is restored to the memory cell, and then the write cycle is started.

At the time of equalizing the bit line pair after writing, RWL is set to "L" and the data in the register cell is not equalized. By doing so, even if the same row address is input again, the data can be read from the register cell.

Further, in the second embodiment, the contents of the register cell are restored to the corresponding memory cell before the refresh cycle is started. (Embodiment 3) FIGS. 10 and 11 are diagrams showing a circuit configuration of a DRAM according to a third embodiment of the present invention. Figure 10
In the first embodiment, a plurality of bit line pairs share a register cell and a sense amplifier. In this figure,
The register cell and the sense amplifier are shared by two bit lines, but any number may be used.

FIG. 11 shows a sense amplifier shared by a plurality of bit line pairs including register cells in the first embodiment. In this figure, two bit line pairs share the sense amplifier, but any number may be used.

Also in this embodiment, when row addresses representing the same memory cell unit are continuously selected, data transfer between the memory cell and the register cell can be omitted as in the first embodiment. The data access time can be greatly shortened. Here, in this embodiment, the memory cell unit composed of C0 and C2 and the memory cell unit composed of C1 and C3 are made into the same group, and the register cells RC0 to RC3 are made to correspond to this. Therefore, the above method can be adopted when row addresses representing the same memory cell group are continuously selected, not limited to row addresses representing the same memory cell unit.

The operation of FIG. 10 will be briefly described. (1) First, set WL0 to “H”, open φT0, and open cell C0.
Of the data is transferred to the S / A side. Then, φT0 is closed and amplified by S / A. Open RWL0 and write C0 to RC0. Close RWL0, end S / A, equalize bit line BL. (2) Open φT1 and transfer the data in cell C1 to the S / A side. Open RWL1 and write C1 to RC1. RWL
Close 1 S / A ends. Equalize the bit line BL. (3) Open both φT0 and φT1 to set BL0, BL1,
Equalize all BL. (4) Steps (1) to (3) are repeated once more to write the data of cell C2 to RWL2 and the data of cell C3 to RWL3. (Embodiment 4) FIG. 12 shows the D according to the fourth embodiment of the present invention.
It is a figure which shows the circuit structure of RAM. RC0 and RC1 are register cells for temporary storage, ReC0 and ReC1 are second register cells for refresh, RWL0 and RWL1 are register cell selection lines, and ReWL0 and ReWL1 are refresh register cell selection lines.

In this embodiment, at the time of refresh, the data in the memory cell is stored in the refresh register cell, amplified by the sense amplifier and restored in the memory cell. Therefore, the data in the register cell for temporary storage is not destroyed, and the register cell for temporary storage can be accessed even after refreshing. (Embodiment 5) FIGS. 13 and 14 are diagrams showing a circuit configuration of a DRAM according to a fifth embodiment of the present invention.

FIG. 13 shows that a plurality of bit line pairs share a register cell and a sense amplifier in the fourth embodiment. Although the register cell and the sense amplifier are shared by two bit lines in this figure, any number of bit lines may be shared.

FIG. 14 shows that in the fourth embodiment, a plurality of bit line pairs including register cells share a sense amplifier. In this figure, the sense amplifier is shared by two bit line pairs, but any number of bit lines may be shared.

This embodiment is a combination of the third and fourth embodiments, and the effects as described in each embodiment can be obtained.

[0048]

As described above, according to the present invention, when a row address representing the same memory cell unit is continuously input twice or more, the register cell is directly accessed to read or write data. This can be performed, and thus high-speed data access can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a NAND type DRAM according to a first embodiment.

FIG. 2 is a diagram schematically showing a configuration of a row address latch circuit used in the first embodiment.

FIG. 3 is a diagram showing a specific configuration of a row address comparison circuit used in the first embodiment.

FIG. 4 is a diagram showing a specific configuration of a decoder selection circuit used in the first embodiment.

FIG. 5 is a diagram showing a specific configuration of a row decoder used in the first embodiment.

FIG. 6 is a diagram showing a specific configuration of a register cell decoder used in the first embodiment.

FIG. 7 is a signal waveform diagram for explaining a read operation in the first embodiment.

FIG. 8 is a signal waveform diagram for explaining a read operation in the first embodiment.

FIG. 9 is a signal waveform diagram for explaining a read operation in the second embodiment.

FIG. 10 is a circuit configuration diagram showing a NAND type DRAM according to a third embodiment.

FIG. 11 is a circuit configuration diagram showing a NAND type DRAM according to a third embodiment.

FIG. 12 is a bit line configuration diagram of a NAND type DRAM according to a fourth embodiment.

FIG. 13 is a circuit configuration diagram showing a NAND type DRAM according to a fifth embodiment.

FIG. 14 is a circuit configuration diagram showing a NAND type DRAM according to a fifth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Row address latch circuit 2 ... Row address comparison circuit 3 ... Decoder selection circuit 4 ... Row decoder 5 ... Register cell decoder 6 ... Sense amplifier 7 ... Equalizer C0, C1, C2, C3 ... Memory cell RC1, RC2 ... Register cell

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cell units each composed of a plurality of dynamic memory cells connected in series are arranged, and one set is provided for a predetermined number of the memory cell units. , A register cell for temporarily storing data read from each memory cell of the corresponding memory cell unit and temporarily storing data to be written in each memory cell of the memory cell unit, and a previous row. A means for comparing the address with the latest row address to determine whether or not these row addresses represent the same memory cell unit, and each row address represents the same memory cell by the means. If it is determined that the data in the register cell is read directly instead of the memory cell in reading, the memory The semiconductor memory device characterized by having a means for writing data to be written without the register cell to read the data once to the register cell.