KR0150496B1 - A semiconductor memory device - Google Patents

Abstract

In a semiconductor memory device, a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided, and each memory cell unit is connected to a bit line, and in the semiconductor memory device, a previous row address is connected to a current row address. Control circuit for directly reading the register cell data during a read operation when designating the same memory cell, and data replacement control for replacing data of an arbitrary memory cell of the memory cell unit with data of the memory cell closest to the bit line contact. Rows for corresponding row addresses AR5 and AR7 for selecting the memory of the memory cell unit 33a for addresses higher than the portions of the row addresses AR0 to AR5 for selecting the memory units in the circuit and the memory cell unit 33a. It is configured with a decoder.

Description

Semiconductor memory device

1 is a circuit diagram showing a NAND DRAM of the first embodiment of the present invention.

2 is a diagram schematically showing the configuration of the rinse dress latch circuit used in the first embodiment of the present invention.

3 is a diagram showing a specific configuration of the row address comparison circuit used in the first embodiment of the present invention.

4 is a diagram showing a specific configuration of a decoder selection circuit used in the first embodiment of the present invention.

5 is a diagram showing a specific configuration of a row decoder used in the first embodiment of the present invention.

6 is a diagram showing a specific configuration of a register cell decoder used in the first embodiment of the present invention.

7 is a signal waveform diagram for explaining a read operation of the first embodiment of the present invention.

8 is a signal waveform diagram for explaining a read operation of the first embodiment of the present invention.

9 is a signal waveform diagram for explaining a read operation of the second embodiment of the present invention.

Fig. 10 is a circuit diagram showing a NAND type DRAM according to the third embodiment of the present invention.

FIG. 11 is a circuit diagram showing a NAND DRAM of a third embodiment of the present invention. FIG.

Fig. 12 is a circuit arrangement diagram showing a NAND DRAM of the fourth embodiment of the present invention.

Fig. 13 is a circuit arrangement drawing showing a NAND DRAM of the fifth embodiment of the present invention.

Fig. 14 is a circuit arrangement drawing showing a NAND DRAM of the fifth embodiment of the present invention.

Fig. 15 is a block diagram showing a schematic configuration of a semiconductor memory device of a sixth embodiment of the present invention.

FIG. 16 is a diagram showing a specific configuration of a memory cell unit used in the sixth embodiment of the present invention. FIG.

17 (a) to 17 (d) show a circuit for making a timing for controlling the sense amplifier of the sixth embodiment, the word line of the temporary memory cell, and the transfer gate between the cell array and the sense amplifier.

18 (a) and 18 (b) show the counter circuit and reset circuit using JK flip-flop, controlling the timing of WLj and the timing of RWL0 to 3 in the sixth embodiment of the present invention.

19 (a) and 19 (b) show a circuit for controlling the timing of the word line in the sixth embodiment of the present invention.

20 (a) and 20 (b) show a circuit for controlling the timings of RWL0 to 3 of the sixth embodiment.

21 shows operation timings of the circuits of FIGS. 17 (a) to 17 (d).

FIG. 22 is a diagram showing the operation timing of the circuits of FIGS. 18 (a) to 21. FIG.

FIG. 23 is a block diagram showing a specific configuration of a data replacement control circuit according to a sixth embodiment of the present invention. FIG.

FIG. 24 is a diagram showing a specific configuration of an address register used in a data replacement control circuit. FIG.

25 is a diagram showing a specific configuration of a sense amplifier, an equalization circuit, and an address temporary memory register used in a data replacement control circuit.

FIG. 26 is a diagram showing the specific configuration of the address comparison circuit used for the data replacement control circuit. FIG.

FIG. 27 is a diagram showing a specific configuration of the recording order change circuit used in the data replacement control circuit. FIG.

FIG. 28 is a diagram showing a specific configuration of a copy / replace selection circuit used in a data replace control circuit. FIG.

FIG. 29 is a diagram showing operation timing when data is refreshed. FIG.

30 is a diagram showing operation timing when data is replaced.

31 (a) to 31 (c) are diagrams showing a data movement state at the time of reading data when data is replaced.

32 (a) to 32 (c) are diagrams showing a data movement state in rewriting when data is replaced.

33 is a diagram showing operation timing when copying data.

34 (a) to 34 (c) are diagrams showing a data movement state during reading when data is copied.

35 (a) to 35 (c) are diagrams showing a data movement state in rewriting when data is copied.

36 is a diagram showing a specific configuration of a row decoder.

37 (a) and 37 (b) show specific configurations of the decoder for the address temporary memory register and the address register core control circuit.

38 (a) and 38 (b) show specific configurations of a register row decoder and a core control circuit.

39 (a) to 39 (c) show specific configurations of the address buffer.

40 (a) and 40 (b) show specific configurations of a decoder.

41 (a) and 41 (b) show specific configurations of an I / O control circuit.

42 is a diagram showing a specific configuration of an I / O buffer.

43 (a) and 43 (c) show a data movement state when data is replaced.

44 (a) to 44 (c) are diagrams showing a data movement state when data is replaced.

45 (a) to 45 (c) are diagrams showing a data movement state when data is copied.

46 (a) to 46 (c) are diagrams showing data movement states when data is copied.

FIG. 47 is a diagram showing a specific configuration of a CPU access start signal generation circuit. FIG.

Fig. 48 is a block diagram showing the schematic structure of the semiconductor memory device of the eighth embodiment of the present invention.

49 is a diagram showing the memory map of the eighth embodiment of the present invention.

50 is a circuit diagram showing the row address buffer used in the eighth embodiment of the present invention.

FIG. 51 is a diagram showing the relationship between the circuit configuration and the I / O signals of the predecode signal generating circuit used in the eighth embodiment of the present invention.

Fig. 52 is a circuit arrangement diagram showing a WDRV driving circuit used in the eighth embodiment of the present invention.

Fig. 53 is a circuit diagram showing the row decoder used in the eighth embodiment of the present invention.

54A and 54B are block diagrams showing a schematic configuration of a semiconductor memory device of a ninth embodiment of the present invention.

55 is a circuit arrangement drawing showing a specific example of the address replacement circuit.

* Description of the symbols for the main parts of the drawings *

1: Hang address latch circuit 2: Hang address comparison circuit

3: decoder selection circuit 4: row decoder

5: Decoder for register cell 6: Sense amplifier

7: Light circuit

[Industrial use]

The present invention relates to a dynamic semiconductor memory device (DRAM) of the present invention, and more particularly to a semiconductor memory device using a memory cell unit (NAND type cell) configured by connecting a plurality of memory cells in series.

[Prior art]

Recently, a semiconductor memory device having a memory cell unit in which a plurality of memory cells are connected in series has been proposed (IEEE ISSCC DIGEST OF TECHNICAL PAPERS vol. 34, p. 106 TAM6.2, 1993 IEEE ISSCC DIGEST OF). TECHNICAL PAPERS vol. 36, p. 46 wp3.3). This type of semiconductor memory device has an advantage that the cell area is reduced because the number of contacts with the bit lines is small compared with the case where the memory cells are not connected in series.

Background Art Conventionally, DRAMs in which a plurality of cells are connected in series to form a NAND type memory unit, and the plurality of memory units are connected to a bit line to form a memory cell array are known. According to this NAND type cell array system, since the number of contacts with the bit lines is small compared with the case where the memory cells are not connected in series, the cell area is reduced.

By the way, when reading the data of the memory cell far from the bit line contact of the memory cell unit in the NAND cell array, the cell data passes through the transistor portion of the memory cell on the bit line side from the memory cell. In the part where the cell data passes, the data of the memory cell in that part is destroyed. In order to prevent data destruction, a register for temporarily storing data in the memory cell unit and rewriting the cell is required.

In order to read the data of the memory cell, after reading the data from the memory cell into the register, the data is read from the register. As a result, the time required for reading data is longer than that of ordinary DRAM. Restoration of the read cell data can be performed simultaneously with amplification of the read data in a normal DRAM in which each bit is connected to a bit line. However, in the NAND type cell array system, a cycle for writing register data to a cell is required in addition to a read cycle. As a result, the time required for reading data becomes long.

In the data recording, after reading the data of the memory cell into the register once, the data to be recorded is recorded in the register section, and the data of the register is written into the memory cell. As a result, the time required for recording data becomes long. That is, according to the NAND type cell array system, there is a problem that it takes a long time to access data.

[Problem to Solve Invention]

As described above, in the DRAM of the conventional NAND cell array system, the data transfer between the memory cell and the register is required at the time of reading and writing the data, and therefore, it takes a long time to access the data. there was.

In other words, when reading the data farthest from the bit line contact of the memory cell unit, the data must be read in order from the data of the nearest one. As a result, there has been a problem that it takes a lot of time each time data is read.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor memory device capable of shortening an average access time and an average cycle time of a memory while using a memory cell unit in which a plurality of memory cells are connected in series. There is this.

In addition, the present invention has been made in view of the above problems, and in the method of configuring a NAND memory cell unit by connecting a plurality of memory cells in series, the time required for reading and writing data can be shortened, and the data An object of the present invention is to provide a semiconductor memory device capable of speeding up access.

[Means and Actions to Solve the Problem]

The main point of the first semiconductor memory device of the present invention is that data stored in a register is directly used when reading or writing the same address (or adjacent address) continuously.

That is, the first semiconductor memory device of the present invention is provided with a memory cell array having a plurality of memory cell units formed by connecting a plurality of dynamic memory cells in series, and provided at a ratio of one set to a predetermined number of memory cell units. And a register cell for temporarily storing data read out from each memory cell of the corresponding memory cell unit, and temporarily storing data to be written to each memory cell of the memory cell unit. In the first semiconductor memory device, the previous row address and the final row address are compared with each other. In the case where these row addresses indicate the same memory cell unit, the data of the register cell is read directly when reading, and the data to be written is written into the register cell without reading the data of the memory cell into the register cell once. do.

Preferred embodiments of the present invention include the following.

(1) Writing of data is performed in the same manner as in the normal NAND cell array method. If the previous row address and the last row address indicate the same memory cell unit only at the time of reading the data, the data of the register cell is read directly.

(2) Reading of data is performed in the same manner as in the normal NAND cell array method. When the previous row address and the last row address indicate the same memory cell unit only at the time of data writing, the data to be written is written into the register cell without reading the data of the memory cell into the register cell once.

(3) When reading and writing data from the memory cell, a refresh register cell is provided in addition to the register cell which temporarily stores data, and is selected at refresh time.

(4) A memory cell group is constituted by a plurality of memory cell units, and register cells are provided at a set ratio with respect to a predetermined number of memory cell groups to temporarily store data read from each memory cell of a corresponding memory cell group. And temporarily store data to be recorded in each memory cell of the memory cell group. In this case, in the case where the previous row address and the last row address indicate the same memory cell group, the read of the register cell data is directly read out during reading, and the data of the memory cell is not read out once to the register cell in writing. Write the data to be written to the register cell.

According to the present invention, when the row decoders R / D indicating the same memory cell unit are continuously selected, data can be directly read from or written to the memory cell without accessing the data in the memory cell. Can be. Therefore, the time required for transferring the cell data from the memory cell to the register cell or restoring from the register cell to the memory cell can be omitted, and data reading and writing can be performed at high speed. When the row addresses indicating the same memory cell unit are not continuously selected, reading and writing of data are performed in the same manner as in the normal NAND cell array method.

In addition, by providing a refresh register cell separately from the register cell (main register cell), data of the main register cell is not destroyed at the time of refresh. Therefore, the refresh can be performed without compromising the effect of the speedup.

According to the second semiconductor memory device of the present invention, the memory cell array includes a plurality of memory cell units constituted by connecting a plurality of memory cells in series, and each memory cell unit is connected to a bit line. In the second semiconductor memory device, a control circuit for controlling the position of data stored in the memory cell of the memory cell unit is provided. In particular, the position of the data is controlled to be stored in the memory cell closest to the bit line contact of the memory cell unit.

Preferred embodiments of the present invention include the following.

(1) The control circuit replaces data at an arbitrary position with data at another position.

(2) The control circuit copies data at any position in the memory cell unit to another position.

(3) In the above-mentioned (1) and (2), the other position is the position of the memory cell closest to the contact with the bit line.

(4) The control circuit for changing the position of the data in the above-mentioned (1) moves the data of any memory cell of the memory cell unit to the memory cell closest to the contact with the bit line, and also any memory cell. And a circuit for performing control so that data stored in a memory cell existing between the bit line contact and the bit line contact are sequentially shifted outward from the bit line contact to be stored in the memory cell.

(5) In the array of memory cell units, registers for data temporary storage of multiples of the number of memory cells of the memory cell unit are provided for each row.

(6) Arbitrary data is data which is accessed most recently from the outside of the chip.

(7) The control circuit is formed on the same engine as the memory cell.

(8) The control circuit is formed on an engine different from the memory cell and is shared by a plurality of memory chips.

(9) When data is read from the memory cell unit into the temporary memory register, data is transferred to the outside or data is received from the outside.

(10) When restoring data from the temporary memory register to the memory cell unit, data is transferred to the outside or data is received from the outside.

According to the present invention, by controlling the position of the data of the memory cell unit, in particular, the data predicted to be accessed next is controlled to be stored in the memory cell closest to the bit line contact of the memory cell unit so that the data is accessed next. Can be read in the shortest time. The data once read out from the memory cell unit is more likely to be read out again than other data. Therefore, by storing the lowest read data in the memory cell closest to the bit line contact, data highly likely to be read is stored in the memory cell closest to the bit line contact. As a result, the average access time and the average cycle time of the memory can be shortened as compared with the conventional case.

The gist of the third and fourth semiconductor memory devices is that the data of the memory cell closest to the bit line of the memory cell unit is likely to be accessed. Among the row addresses input from the outside, the row address portion for selecting memory cells in the memory cell unit is located above the address than the row address portion for selecting each memory cell unit.

That is, according to the third semiconductor memory device of the present invention, a plurality of memory cell units each configured by connecting a plurality of memory cells in series are arranged in an array form, and each memory cell unit is connected to a bit line. In this semiconductor memory device, a row decoder used to make the row address portion for selecting a memory cell in the memory cell unit among the row addresses input from the outside is located above the address than the row address portion for selecting the memory cell unit, respectively. Is installed.

According to the fourth semiconductor memory device of the present invention, a plurality of memory cell units each configured by connecting a plurality of memory cells in series are arranged in an array form, and each memory cell unit is connected to a bit line. In this semiconductor memory device, a control circuit for replacing data of an arbitrary memory cell of a memory cell unit with data of a memory cell closest to a bit line contact, and a row for selecting a memory cell in the memory cell unit from a row address input from the outside. A row decoder is used that is used so that the address portion is located above the address than other portions of the row address for selecting each memory cell unit.

Preferred embodiments of the present invention include the following.

(1) Circuits for replacing corresponding to the relationship between the external address and the internal address among a plurality of types by signals from the outside are provided.

(2) The data replacement circuit moves the data of any memory cell of the memory cell unit to the memory cell closest to the contact with the bit line, and moves to the memory cell existing between the arbitrary memory cell and the bit line contact. It is a circuit that performs control so that the stored data is sequentially shifted outward from the bit line contact to be stored in the memory cell.

(3) Arbitrary data is data which is accessed most recently from the outside of the chip.

According to the present invention, among the row addresses input from the outside, a row address portion for selecting a memory cell in the memory cell unit is located above another portion of the row address for selecting an arbitrary memory cell unit from the plurality of memory cell units. . Accordingly, it is possible to reduce the possibility that data of another memory cell in the same memory cell unit is next accessed, thereby reducing the average access time.

In the data access of the CPU, data close to the address once accessed may be accessed next. For this reason, when data of the memory cell closest to the bit line contact is normally accessed, data of another memory cell of the same memory cell unit is likely to be accessed next, which takes a long time to access the data. Therefore, as in the present invention, the access time can be shortened by reducing the possibility that data of the same memory cell unit is next accessed.

Further, a plurality of correspondences are set between the external address and the internal address, and any one of these correspondences can be selected by an external signal. Accordingly, the correspondence between the external address and the internal address can be selected in a very short time by the external signal.

Moreover, the present invention can be used more effectively by combining with a system that controls the position of the data so that the data most likely to be accessed next is stored in the memory cell closest to the bit line contact.

In particular, in accessing data, the upper address remains intact and the lower address changes continuously. Therefore, when the lower address selects each memory cell and the upper address selects a memory cell in the memory cell unit, the read data selects one memory cell from the plurality of memory cell units, thereby bringing all the data to the bit line contact. It is possible to store in a nearby memory cell. In contrast, when the lower address selects a memory cell in the memory cell unit and the upper address selects each memory cell unit as in the conventional case, the read data is stored in a plurality of memory cells or all memory cells from any memory cell unit. Will be selected. As a result, all read data cannot be stored in the memory cell closest to the bit line contact.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a diagram showing a circuit configuration of a DRAM according to the first embodiment of the present invention. In this embodiment, a memory cell unit is constructed by connecting two memory cells in series, but the number of memory cells connected in series can be appropriately changed.

In Fig. 1, the word lines for the two memory cells C0 and C1 are W0 and W1, respectively, and the register cells in which cell data are stored are RC0 and RC1, and register words serving as select lines of the register cells. The lines are referred to as RWL0 and RWL1. A sense amplifier S / A 6 and an equalization circuit EQL 7 are connected to one end of a bit line BL to which a memory cell unit consisting of memory cells C0 and C1 is connected. Further, a selection gate driven by ØT is inserted in the middle of the bit line BL.

Here, the sense method is an open bit line system, and bit lines BL and BL are disposed at both ends of the sense amplifier 6. Further, a plurality of memory cell units (not shown) are connected to the bit line BL, and a plurality of columns of the configuration shown in FIG. 1 are arranged in the word line direction.

The above-described configuration is the same as a conventional NAND cell array system, but in the present embodiment, the driving method by the circuits 1 to 5 shown in the block diagram is characteristic. That is, the row address is input to the row address latch circuit 1 and the row address comparison circuit 2, and the decoder selection circuit 3 supplies the row decoder 4 and the register based on the output of the row address comparison circuit 2; The cell decoder 5 is selectively driven. The word lines WL0 and WL1 are driven by the row decoder 4 and the register word lines RWL0 and RWL1 are driven by the register cell decoder 5.

The row address latch circuit 1 is a circuit for holding the previous row address and is configured as shown schematically in FIG. Here, the row address is 4 bits of RA0, RA1, RA2, RA3, and the upper three bits (RA3, RA2, RA1) represent the row address of the unit cell, and the least significant bit (RA0) represents the row address of the cell in the unit cell. Indicates. That is, this represents a case where two unit cells are installed in one unit cell. However, latch RA0 is not necessary. The row address comparison circuit 2 compares the previous row address held in the row address latch circuit 1 with the new row address when a new row address is input in the next cycle. As shown in FIG. Consists of. Here, Cout = H is obtained when all addresses RA1 to RA3 coincide under the condition of Ø = H.

The decoder selection circuit 3 is made as shown in FIG. If the new address is different from the previous address, the decoder selection circuit 3 selects the signal S0 for driving the row decoder 4, and selects the signal S1 for driving the decoder 5 for the register cell. do. The decoder selection circuit 3 then selects only the signal S1 if the new address is the same as the previous address. In this case, the signal SO is set to H only when Cout = L and Ø = H.

The row decoder 4 is configured as shown in FIG. The row decoder 4 is used to selectively drive the word line WL of the memory cell. The decoder 5 for the register cell is configured as shown in FIG. The decoder 5 for the register cell is used to selectively drive the register word line RWL.

According to the above structure, the new row address and the previous row address inputted are compared with each other by the row address comparator 2. If both addresses do not select selection of the same word lines WL0 and WL1 by the decoder selection circuit 3, the row decoders 4 and 5 for the register cells perform normal operation.

That is, the word line corresponding to the address is applied by the voltage by the decoder, and the data is read out from the memory cells close to the bit line contacts in order. If the read data is amplified by the sense amplifier 6, the register word line corresponding to each address is applied to the voltage by the decoder 5 for the register cell, and the data of the memory cell is written to the register cell. After reading data from all the memory cells connected to the NAND type unit, the data is stored from the register cell to the NAND cell after the storage of the data in the register cell is finished, and the word line is separated from the word line in the order away from the bit line contact .

Similarly, in the write operation, the word lines rise in order, data is stored in the register cell, data is written in the target cell, and data is stored from the register cell.

If an address for sequentially selecting the same word lines WL0 and WL1 is input, the decoder 3 selects only the signal S1. At this time, the row decoder 4 does not operate. On the contrary, the decoder 5 for the register cell directly selects the register line of the register cell in which the data corresponding to the address is stored, and thus the data is read out from the register cell.

In this case, similar to the case of cell data reading and rearranging, the sensing amplifier 6 operates to amplify the data of the register cell and stores the data in the register cell. Restoring of data from the register cell to the memory cell is performed sequentially after reading data from the register cell.

After data is transferred to the DQ line, the pair of bit lines are equalized. However, RWL is set to L at this time, and the data of the register cell is not equalized. Even by the same row address being input again, data can be read from the register cell.

In the case of writing, if the same word line WL as the data stored in the register cell is selected, the data may be written directly into the register, or the data may be re-stored in the memory cell. As a result, the time for data to move from the memory cell to the register cell can be omitted once.

In the case of writing, in equalizing a bit line pair, RWL is set to L and data of a register cell is not equalized. Even by the same row address being input again, data can be read from the register cell.

In the case of the first embodiment, the waveform diagram is shown in FIG. 7 and FIG. 7 shows a case in which another hang address is read after the first read. In this case, the second read is performed in the same way as the first read. The data storage after the second read is then performed in the same manner as the data storage after the first read.

8 shows a case where the same row address is read after the first read. In this case, data of the memory cell need not be transferred to the register cell. Data is read directly from the register cell. For this reason, the time for reading data becomes shorter than the first reading. Therefore, the time required for reading data can be greatly reduced.

The case in which the reading system of FIG. 8 is applicable is applicable not only when two addresses are completely the same but also when the three upper bits of each address are the same, and is an address indicating the same memory cell unit.

Moreover, although not shown in the figure, the data of the memory cell is already stored in the register cell when the new address in writing is the same as the previous address. For this reason, data transfer from a memory cell to a register cell can be omitted. Therefore, the data to be written can be written directly to the register cell, and the time required for writing the data can be reduced.

As described above, according to the present embodiment, when the row addresses indicating the same memory cell unit are selected continuously, data can be read directly from the register cell without accessing the data to the memory cell, or the data is written directly to the register cell. Can be. For this reason, the time required for transferring the cell data from the memory cell to the register cell and storing the data from the register cell to the memory cell can be reduced, and the data access time can be greatly reduced.

Example 2

The DRAM of the second embodiment of the present invention is described in detail below.

The second embodiment shows a case in which data is not restored from the register cell to the memory cell until the address of the next word line appears in the first embodiment.

9 shows a waveform diagram in the case of reading in the present embodiment. Similar to the first embodiment in the second embodiment, the row address latch circuit 1 retains the previous row address, and the row address comparator 2 stores the new address and the previous one when the new address is entered next cycle. Compare the row address. If the new row address is different from the previous address, resave from the register cell to the memory cell is performed, and a read cycle of the new address begins. If a row address in which the same word lines WL0 and WL1 are selected continuously is input, resave is not performed. The decoder 5 for a register cell selects a register word line of a register cell in which data corresponding to an address is stored, and reads data from the register cell.

Similarly to the case where the cell data is read out and the restoring is performed, the sensing amplifier 6 operates to amplify the data of the register cell and restores the data to the register cell.

After data is transferred to the DQ line, the bit line pairs are equalized. However, RWL is set to L at this time, and the data of the register cell is not equalized. Even when the same row address is not input again, data can be read from the register cell.

In the case of writing, if the same word line WL as the data stored in the register cell is selected, the data may be written directly to the register cell. When another row address is input, the data already written to the register cell can be restored to the memory cell. As a result, the time for moving data from the memory cell to the register cell can be omitted.

When another word line WL is selected, the data currently stored in the register cell is first restored into the NAND cell, and then data is read out from the selected WL and recorded.

In equalizing the bit line pairs after writing, RWL is set to L and the data in the register cells is not equalized. Even when the same row address is input again, data can be read from the register cell.

Further, according to the second embodiment, the contents of the register cell are stored in the corresponding memory cell before the refresh cycle starts.

Example 3

10 and 11 show a circuit structure of the DRAM of the third embodiment of the present invention. 10 shows a case where a register cell and a sense amplifier are shared by use of a plurality of bit line pairs of the first embodiment. In the figure, two bit lines share a register cell and a sense amplifier. However, quite a few bit lines can be used.

Figure 11 is shared by the use of a number of bit line pairs in which the sense amplifier comprises the register cell of the first embodiment. In the figure, two bit lines share a sense amplifier. However, quite a few bit lines may be used.

Even in this embodiment, it is possible to omit the data transfer between the memory cell and the register cell similarly to the first embodiment when the row addresses indicating the same memory cell unit are selected continuously. This can greatly reduce the data access time. In this embodiment, the memory cell units consisting of C0 and C2 and the memory cell units consisting of C1 and C2 are formed in the same group and the register cells RC0 to RC3 are made to correspond to the group. For this reason, the above system can be used not only when the row addresses indicating the same memory cell unit are selected continuously but also when the row addresses indicating the same memory cell group are continuously selected.

10, the operation is described next.

(1) First, WL0 is set to H, ØT0 is turned on, and thus data of the cell C0 is transmitted to the S / A side. ØT0 is then turned off and amplified by S / A. RWL0 is turned on, so cell C0 is written to RC0. RWL0 is turned off, the S / A operation is terminated, and the bit line is equalized.

(2) ØT0 is turned on, so the data of cell C1 is transmitted to the S / A side. As S / A is activated and amplified, and RWL is on, C1 is recorded as RC1. RWL1 is turned off. S / A operation is terminated. The bit line is equalized.

(3) Both Ø0 and Ø1 are on, and all BL0, BL1, BL are equalized.

(4) The operations 1 to 3 are repeated again, the data of the cell C2 is written to the RWL2, and the data of the cell C3 is written to the RWL3.

Example 4

12 is a diagram showing the circuit structure of a DRAM of a fourth embodiment of the present invention. RC0 and RC1 are register cells for interim storage, ReC0 and ReC1 are second register cells for refresh, RWL0 and RWL1 are select lines for register cells, and ReWL0 and ReWL1 are select lines for register cells for refresh. to be.

In this embodiment, the data of the memory cell is stored in the register cell for refresh upon refresh, amplified by the sense amplifier, and stored in the memory cell. Therefore, the data of a register cell for a provisional storage device can be accessed even after refresh without the data of the register cell for the provisional storage device being destroyed.

Example 5

13 and 14 show circuit structures of the DRAM of the fifth embodiment of the present invention. Figure 13 shows that a register cell and a sense amplifier are shared by the use of multiple bit line pairs in the fourth embodiment. In this figure, two bit lines share a register cell and a sense amplifier. However, some shared bit lines may be used.

14 is shared by the sense amplifier using a plurality of bit lines including register cells in the fourth embodiment. In the figure, two bit lines share a sense amplifier. However, some shared bit lines may be used.

The fifth embodiment is a combination of the third and fourth embodiments, and the benefits can be obtained as described in each embodiment.

As described above, according to the fifth embodiment, when a row address indicating the same memory cell unit is input two or more times in succession, data can be directly accessed to a register cell to be read and written, thus providing high-speed data access. Can be realized.

Example 6

This embodiment illustrates that the data expected to be accessed is considered as the latest accessed data. This is based on the possibility that the data once accessed is quite likely, and the data of the neighbor address of the accessed data will be accessed next. However, the concept of the present invention is not limited to this embodiment. If the CPU instructs the next access data, the data may be controlled to move to a position close to the bit line contact of the memory cell unit.

15 is a block diagram showing the structure of the semiconductor memory device according to the sixth embodiment of the present invention. In the drawing, reference numeral 1 denotes a NAND cell array in which memory cell units to be described later are arranged in an array form, and reference numeral 2 denotes a sense amplifier for writing and reading data and equalizing a circuit. Reference numeral 3 denotes a provisional storage cell, reference numeral 4 denotes a row address buffer, reference numeral 5 denotes a row decoder, reference numeral 6 denotes a core control circuit, and reference numeral 7 denotes a storage row. A decoder, reference numeral 8 is an open-dress buffer, reference numeral 9 is a column decoder, reference numeral 10 is an I / O buffer, reference numeral 11 is an I / O control circuit, and reference numerals. Denoted at 12 is a control pulse generating circuit, and reference numeral 13 is a data replacing control circuit. Individual circuits are arranged on the same engine as memory chips.

In this embodiment, the dynamic memory cell is used as the memory cell. As shown in FIG. 16, four memory cells are connected in series. As a result, the memory cell units represented by the NAND cell in this embodiment are formed and arranged in an array form. Although the memory cell capacity is assumed to be 64k bits in this embodiment, the present invention can be used for memory sizes of different sizes. In the sense amplifier section 2, four dynamixels are arranged as provisional storage cells required for the NAND cell in order to temporarily store read data.

In this embodiment, the change of the position of the data in the memory can be realized by changing the order in which the word lines RWL0 to RWL3 of the provisional storage cell 3 operate. That is, data rewriting is normally performed in the reverse order of reading order. However, according to this embodiment, the order of rewriting controls word lines RWL0 to RWL3 such that data externally accessed is last recorded.

Conventionally, the data of the memory cell furthest from the bit line is read out by the sense amplifier and rewritten directly into the original cell. For this reason, reading is realized even when the number of provisional storage cells is one less than the number of cells in the memory cell unit. However, according to the present embodiment, since cells for temporarily storing the last data are required, the number of temporarily storing the same cells as the number of cells of the memory cell unit is always required.

The data replacement control in this embodiment is performed by the control pulse generation circuit 12 and the data replacement control circuit 13. 17 (a) to 20 (b) show a special circuit structure of the control pulse generating circuit 13. VBRAS and VBXFCK are used as basic clocks from the outside. VBRAS is mainly used to reset internal circuits and fetch addresses. VBXFCK is a signal for obtaining time for reading and writing respective data of the memory cell unit.

17 (a) to 17 (d) show a circuit for obtaining time to control the sense amplifiers 2 from the VBXFCK and the word lines RWL0 to RWL3, the memory cell array 1 and the sense amplifiers 2 The transfer gate of the figure is shown. 21 shows a timing diagram of a typical signal. In this figure, WDOWN is used to obtain the time of bit line equalization, and PHAF and PHBF are times for controlling the provisional storage cell 3 between the memory cell array 1 and the sense amplifier 2 and the word line of the transfer gate. It is used to get SEN is used to get the time of the sense amplifier 2.

The timing of the word line WLj and the timing of RWL0 to RWL3 are controlled by a counter circuit using the JK flip flop shown in Fig. 18A. In this figure, QA and BQA represent the output of the slave stage, QA and BQC represent the output of the master stage, and R represents a reset terminal. The timing is shown in FIG. The circuit shown in FIG. 18 (b) is used as a reset. The identification between read and write can be done by 0 (read) and 1 (write), which are the most significant bits of the counter. When the current internal address matches the external address, the HIT signal of the counter is set to 1, and the most significant bit of the counter is set to 1. The next time VBXFCK is input, the HIT signal starts recording.

Fig. 19A shows a circuit for controlling the timing of word lines, and Fig. 19B is a truth table thereof. FIG. 20 (a) shows a circuit for controlling the timings of RWL0 to RWL3, and FIG. 20 (b) shows the truth table. 22 shows the operating time of these circuits.

23 is a block diagram showing a more detailed structure of the data replacement control circuit 13. The data replacement control circuit 13 includes an address register 21, a sense amplifier / equalization circuit 22, an address temporary storage register 23, an address comparator 24, a write order replacement circuit 25, and copy / replace selection. Circuit 26, a row decoder 27 for an address register, an address register core control circuit 28, and a decoder 29 for an address temporary storage register. The address register 21 stores the data address of the memory cell unit. Sense amplifier / equalization circuit 22 is used to read the address. The address tentative storage register 23 is used to tentatively store the read address. The address comparator 24 is used to compare the address from the outside with the address from the address register 21. The write order changing circuit 25 is used for control to change the order of writing the addresses from the provisional storage cells to the memory cells when the addresses are compatible with each other. The copy / replace selection circuit 26 is used to select when the data of the unit is changed in the unit and when the data of the unit is copied.

24 shows a special circuit of the address register 21. As shown in FIG. The number of bits in the register is determined by the number of cells in series in the memory cell unit. In this embodiment, since the number of cells in series is four, a register of 2 bits (2 x 2 = 4) per one cell unit is prepared, and the address of the cell of the memory cell unit is one unit based on four data. And 64 such units (corresponding to the number of memory cell units for independent control) are required. In this case, the RSET signal is a signal that sets the contents of the register to initial values (00, 01, 10, 11), and becomes H when power is turned on.

25 shows a special structure of the sense amplifier / equalization circuit 22 and the address temporary storage register 23. As shown in FIG. The signal lines RAWL0 to RAWL3 of the address tentative storage register 23 operate as if RWL0 to RWL3 correspond to the number. That is, when the data position of the cell is replaced, the position of the address is also controlled to be replaced.

26 shows a special structure of the address comparator 24. As shown in FIG. When the least significant two bits are input from the outside, the address from the outside is compared with the address stored in the address register to match the data read. When the address from the outside matches the address stored in the address register 21, the HIT signal becomes H, and it generates a control pulse and the write sequence changing circuit 25 in which the data mentioned with the CPU are currently read out to the sense amplifier from the outside. The circuit 12 is notified. This causes the CPU to start reading data. Further, the pulse control circuit 12 is set so that the write operation is performed from the clock of the VBXFCK. The HIT signal continues to output H until the write operation is completed.

FIG. 27 shows a special structure of the recording order change circuit 25, and FIG. 28 shows a special structure of the copy / replace selection circuit 26. As shown in FIG. The write order switching circuit 25 sets the REF signal to H when the refresh is performed, and transmits the respective signals XQ0 to XQ3 sent from the control pulse generating circuit 12 to XA0 to XA3, respectively. Also, when data is copied, the recording order switching circuit 25 sets the CP signal to H. Moreover, when data is replaced in the unit, the recording order switching circuit 25 sets the CP signal to L.

The following describes a case where data is replaced and a case where the third cell facing from the bit line contact is copied when accessed from the outside. First, the case where data is replaced is described. If XA2 is activated during normal access, and the HIT signal becomes H signal, XA2 is connected to XQ0, XA1 is connected to XQ @, 2, and XA0 is connected to XQ1 at the clock of the next VBXFCK. The timing chart is shown in FIG. 29 and FIG. 30, and the state of data movement is shown in FIG. 31 (a) and FIG. 32 (c). By this connection, data is written late from the outside and stored in the cell closest to the bit line contact of the memory cell unit. Moreover, by considering the order of the data of the memory cell unit by the use of the above control, the data related to a long time is inputted in chronological order from more cells from the bit line contact, and the newly referenced data is the cell closest to the bit line contact. Are entered in chronological order.

As an example, the following describes the case where the least significant bits of the external address are 1 and 0. First, as shown in Fig. 31 (a), the data A of the memory cell closest to the bit line contact is read out into the provisional storage cell, and the address corresponding to the memory cell is simultaneously read out into the provisional storage register.

Secondly, as shown in Fig. 31 (b), the data B and the address of the memory cell twice close to the bit line contacts are read out. Further, as shown in Fig. 31 (c), the data C and the address of the memory cell closest to the bit line contact are read out. Next, the data C of the memory cell read late is output to the outside.

Next, data and addresses which are temporarily stored are rewritten to memory cells and address registers. At this time, except for the data C of the late-read memory cell, other data and addresses are sequentially written.

More specifically, as shown in FIG. 32 (a), the data B of the second read memory cell and the address are rewritten to the third read memory, and the position of the address register is rewritten. As shown in Fig. 32 (b), the data A and the address of the first memory cell to be read out are rewritten to the memory cell to be read out second, and the position of the address register is rewritten.

Next, as shown in Fig. 32 (c), the data C of the memory cell read late and the memory cell read first are rewritten and the position of the address register is rewritten. This completes the rewrite operation. Under this condition, the data of the memory cell closest to the bit line contact becomes C, which is the recently read data.

On the contrary, when data is copied to the memory cell unit, the CP signal is set to H. The timing chart is shown in FIG. 33, and the data movement state is shown in FIGS. 34 (a) to 35 (c). If XA2 operates during normal access and the HIT signal becomes H, then XA2 is connected to XQ0 to XQ2, and XA1 is connected to XQ1 at the next clock signal of the next CBXFCK. If a write operation is started under this condition, the referenced data is copied from the outside closest to the bit line contact to the memory cell. At this time, since the copy / replace selection circuit 26 shown in Fig. 26 is connected to XB0, XB1, XB2, and XB3 from XQ0 to XQ3, the contents of the address register are not changed.

As an example, the following describes a case where the least significant bits of the external address are 1 and 0. First, as shown in FIG. 34 (a), the data A of the memory cell closest to the bit line contact is read out into the provisional storage cell, and the address corresponding to the memory cell is simultaneously read out into the provisional storage register.

Secondly, as shown in Fig. 34 (b), the data B and the address of the memory cell closest to the bit line contact are read out. Further, as shown in Fig. 34 (c), the data C and the address of the memory cell closest to the bit line contact are read out. Next, the data C of the memory cell read late is output to the outside. Up to this point, this case is the same as when data is replaced.

Next, the data and address temporarily stored are written to the memory cell and the address register. At this time, the data C of the (third) memory cell read out late is rewritten at the original position and rewritten to the memory cell closest to the bit line.

In particular, as shown in FIG. 35 (a), the data C and the address of the late read memory cell are rewritten to the positions of the late read memory cell and address register. Subsequently, as shown in FIG. 35 (b), the data B and the address of the second read memory cell are rewritten in the positions of the second read memory cell and the address register.

At this time, as shown in FIG. 35 (c), the data C and the address of the memory cell that are read late and the address of the memory cell and the address register where the address is first read are rewritten instead of the first read data A. do. Thus, the rewrite operation is terminated. Under this condition, the data of the memory cell closest to the bit line contact becomes C, i.e., recently read data.

The specific structure of each part is shown in FIGS. 36 to 42 for reference. FIG. 36 shows the row decoder of FIG. 23, FIG. 37 (a) shows the decoder for the address temporary storage register, and FIG. 37 (b) shows the specific structure of the address core control circuit. Fig. 38 (a) shows the core control circuit of Fig. 15, Fig. 38 (b) shows a register row decoder, and Figs. 39 (a) to 39 (c) show an address buffer, and Fig. 40 (a) Fig. 40 (b) shows the row and column decoders, Figs. 41 (a) and 41 (b) show the I / O control circuit, and Fig. 42 shows the specific structure of the I / O buffer.

As described above, according to the embodiment, the arbitrary data of the memory cell unit is replaced and copied, and the position where such data expected to be accessed next is stored in the closest memory cell of the bit line contact of the memory cell unit is controlled. A data replacement circuit control circuit 13 is provided. This allows the data to be read for the shortest time the next time the data is accessed, and the average access time and average cycle time of the memory can be reduced compared to the normal case.

Example 7

In the above embodiment, data reception / transmission to the outside is performed when data is read from a register for provisionally storing from the memory cell unit. Instead of this operation, data reception / transmission to the outside is performed when data is stored in a memory cell unit from a register. This embodiment is shown in FIGS. 43 (a) -47. The basic circuit structure and signal waveform of this embodiment are the same as in the previous embodiment. First, the case where the data is replaced. When XA2 is activated during normal access and the HIT signal becomes H, XA2 is connected to XQ0, XA1 is connected to XQ2, and XA0 is connected to XQ1 at the next VBXFCX clock. The timing diagrams are shown in Figs. 29 and 30, and the state of data movement is shown in Figs. 43 (a) to 44 (c). The data referred to by this connection is written late from the outside and written to the cell closest to the bit line contact of the memory cell unit. At this time, the CPU is notified that the access can be started by the CPU access start signal generation circuit shown in FIG. By the use of the above control, the order of the data of the memory cell unit is taken into consideration, so that data referred to as old is input continuously and continuously in time from the cell furthest from the bit line contact, and referred to as newly. The received data is continuously inputted continuously in time from the cell closest to the bit line contact.

As an example, the case where the least significant bit of the external address is: 1 or 0 will be described. As shown in FIG. 43 (a), first, data A of the memory cell closest to the bit line contact is read into the long term storage cell, and an address corresponding to the memory cell is simultaneously read into the tentative storage register.

Next, as shown in FIG. 43 (b), second, the data B and the address of the memory cell closest to the bit line contact are read out. Further, as shown in FIG. 43 (c), the third time, the data C of the memory cell closest to the bit line contact and the address are read out.

Next, the temporarily stored data and the address are rewritten into the address register. At this time, except for the data C (third) of the late-read memory cell, other data and addresses are sequentially written.

In particular, as shown in Fig. 44 (a), the data B and the address of the second read memory cell are rewritten to the positions of the third read memory cell and address register. Subsequently, as shown in FIG. 44 (b), the data A and the address of the first memory cell to be read out are rewritten to the memory cell to be read out second and to the address register.

At this time, as shown in FIG. 44 (c), the data C of the memory cell to be read late, the memory cell to which the address is first read, and the address register are rewritten. At this time, the data C of the memory cell is output to the outside. Thus, the rewrite operation is terminated. In this state, the data of the memory cell closest to the bit line contact becomes C, i.e., recently read data. On the other hand, when data is copied in the memory cell unit, the CP signal is set to H. The timing chart is shown in FIG. 33, and the state of data movement is shown in FIGS. 45 (a) to 46 (c). When XA2 is activated during normal access and the HIT signal goes to H, at the next clock of the next VBXFCX, XA2 is connected to XQ0 and XQ2, and XA1 is connected to XQ1. When the write operation is started under this condition, the mentioned data is copied from the outside to the memory cell closest to the bit line contact. At this time, the copy / replacement selection circuit 26 shown in FIG. 28 connects XQ0 to XQ3 to XB0, XB1, XB2, and XB3, so that the contents of the address register are not changed.

As an example, the case where the least significant bit of the external address is 1 or 0 will be described. As shown in FIG. 45 (a), first, data A of the memory cell closest to the bit line contact is read out into the provisional storage cell, and an address corresponding to the memory cell is simultaneously read out into the address provisional storage register. .

Next, as shown in FIG. 45 (b), second, the data B and the address of the memory cell closest to the bit line contact are read out. Further, as shown in FIG. 45 (c), thirdly, the data C of the memory cell closest to the bit line contact and the address are read out. At this time, the memory cell data C read late is output to the outside. So far, this case is the same as when data is replaced.

Next, the temporarily stored data and address are rewritten to the memory cell and address register. At this time, the data C of the late-read (third) memory cell is re-stored in its original position and rewritten in the memory cell closest to the bit line.

In particular, as shown in Fig. 46 (a), the data C and the address of the late read memory cell are rewritten to the positions of the late read memory cell and the address register. Subsequently, as shown in FIG. 46 (b), the data B of the second read memory cell and the address are rewritten to the second read memory cell and the address resist.

At this time, as shown in FIG. 46 (c), the data C of the memory cell read late, the memory cell whose address is read first, and the position of the address register are not the first data A read out. Is rewritten in. At this time, the data C of the memory cell is output to the outside. Thus, the rewrite operation is terminated. Under this condition, data of the memory cell closest to the bit line contact becomes C, i.e., recently read data.

Of course, this embodiment can obtain the same advantages as the previous embodiment. In this embodiment, the first data access is later than the previous embodiment. However, in this embodiment, there is an advantage that the next data access is fast.

The sixth and seventh embodiments described above are not limited to the above-described embodiments, respectively. The above embodiment has described that the data replacement control circuit is provided on the same substrate as the memory chip. However, the data replacement control circuit may be provided on another substrate. When the data replacement control circuit is commonly used for a plurality of memory chips, if another substrate is used, the required area may be small. Moreover, the above embodiment has described that data is copied or replaced for the position closest to the bit line contact of the unit. However, the location is not particularly limited. Different circuit structures can be designed to allow data to move to different locations in the same unit.

Moreover, the above embodiment described that the dynamic cell was used. However, nonvolatile memory cells such as EEPROM can be used. Moreover, it will be understood that various modifications can be made without departing from the spirit of the invention.

As described above, according to the sixth and seventh embodiments, the data is stored in the memory closest to the bit line contact of the memory cell unit by controlling the position of the data expected to be accessed next, and when the data is next accessed. It can be read for the shortest time. Therefore, the average access time and average cycle time of the memory can be reduced as compared with the conventional case.

Example 8

FIG. 48 is a block diagram showing the schematic structure of the semiconductor memory device of the eighth embodiment of the present invention, and FIG. 49 shows the memory map of the same embodiment. The addresses AR0 to AR11 input from the outside are stored in the row address buffer 31. The address buffer 31 transmits the decoder signals AR0 to AR11, / AR0 to AR11 to the row decoder 32. The row decoder 32 activates the word line of the memory cell 33 based on the decoder signals AR0 to AR11 and / AR0 to AR11.

It is assumed that the memory structure of this embodiment is a memory cell array formed by connecting a plurality of memory cell units 33a each having a plurality of memory cells connected in series to bit lines. At this time, the external addresses AR6 and AR7 corresponding to the inside of the memory cell unit are provided at an address higher than the portions AR0 to AR5 of the external addresses corresponding to the portions between the memory cell units. In this embodiment, assume a memory cell unit consisting of four memory cells. However, if many memory cells are used, there is no fundamental difference in the number of memory cells.

In FIG. 49, the left side shows the selection of each memory cell unit, and the right side shows the selection of memory cells in the memory cell unit. In addition, addresses AR8 to AR11 (not shown) are used to select a block having a plurality of units.

In accessing a program of a computer, there is a characteristic of a spatial location of data. That is, when data having a predetermined address is accessed, there is a high possibility that data having an address close to the predetermined address is accessed. The addresses are made to correspond to each other as described above, thus reducing the possibility of the next data being accessed in adjacent data of the same memory cell unit. Furthermore, by combining a system of stored data for storing recently accessed data in the memory cell closest to the bit line of the memory cell unit, the average time can be greatly reduced.

50 shows a circuit structure of the row address buffer 31, and FIG. 51 shows a pre-decode signal generation circuit 34 provided between the row address buffer 31 and the row decoder 32. FIG. The relationship between the input / output circuit configuration is shown. In the table shown in the lower part of Fig. 51, x of signals xARi and xARj indicates the presence of / (bar), 0 indicates the presence of a bar, and 1 indicates that a bar does not exist. In this embodiment, a decoding system using the pre-code signal shown in FIG. 51 can be considered. However, despite using a system in which the decode signal is used directly from the row address buffer 31, there is no fundamental difference.

Fig. 52 shows a circuit diagram of the WDRV driver 35 for generating a signal corresponding to an address for selecting a memory cell unit. In this example, the address signals for selecting the memory cells of the memory cell unit are D0 to D3 decoded from the addresses AR6 and AR7 that are higher than the portions AR0 to AR5 of the addresses for selecting each memory cell. FIG. 53 shows a circuit diagram of the row decoder operated by receiving the pre-decode signal of the pre-decode signal generating circuit 34 and the WDRV driver 35. As shown in FIG.

According to this embodiment, the external addresses AR6 and AR7 corresponding to the inside of the memory cell unit are made to correspond to higher addresses than the portions AR0 to AR5 of the external addresses corresponding to the portions between the memory cell units. Thus, it is possible to reduce the possibility that the data of the memory cell unit is next accessed. Furthermore, by combining a system of stored data for storing recently accessed data in the memory cell closest to the bit line of the memory cell unit, the average access time can be greatly reduced.

Example 9

54A and 54B are block diagrams showing the schematic structure of the semiconductor memory device of the ninth embodiment of the present invention. The addresses A0 to A11 input from the outside are stored in the address buffer 31. The address buffer 31 transmits the address decoder signals AR0 to AR11 and / AR0 to / AR11 to the address decoder 32. The address decoder 32 determines the cell for activating the word line of the memory cell 33 based on the decoder signals AR0 to AR11 and / AR0 to / AR11.

At this time, an address replacement circuit 36 is provided in front of the address buffer 31 as shown in FIG. 54 (a). Alternatively, as shown in FIG. 54 (b), an address replacement circuit 36 is provided between the address buffer 31 and the address decoder 32. As shown in FIG. The address replacement circuit 36 is a circuit that selects the correspondence between the external address and the internal address from a plurality of correspondences by signals from the outside or signals from the internal circuit.

55 shows a specific structure of the address replacement circuit 36. As shown in FIG. This example shows a case where the address replacement circuit 36 is provided as shown in FIG. 54 (a). Q04 to Q07 and Q14 to Q17 are n-channel MOS transistors. Ak (k = 4 to 7) is an address input from the outside. A'k (k = 4 to 7) is an address inside the memory cell. The signal ADC sent from the outside is connected to the gates of Q14 to Q17 and is connected to the gates of Q04 to Q07 through the inverter 11.

When the ADC is set to L, Q04 to Q07 are activated and Q14 to Q17 are deactivated. Ak (k = 4 to 7) is then connected to A'k (k = 4 to 7). When the ADC is set to H, Q04 to Q07 are deactivated and Q14 to Q17 are activated. At this time, the external addresses A4 and A5 are connected to the internal addresses A'6 and A'7, and the external addresses A6 and A7 are connected to the internal addresses A'4 and A'5.

As described above, the address replacement circuit 36 can replace the correspondence between the external address and the internal address based on the signal ADC sent from the outside. In this embodiment, one of the two correspondences between the external address and the internal address is selected based on the signal ADC sent from the outside. However, one correspondence between the external address and the internal address can be selected from two or more correspondences. In addition, when the address replacement circuit 36 is provided as shown in Fig. 54 (b), the decoder replacement signal and the addresses A4 to A7 and / A4 to / A7 are set to the 54th address (a). In the same manner as the case provided as shown in FIG.

The eighth and ninth embodiments are not limited to the above-described respective embodiments. The above embodiment has described a case where a dynamic memory cell is used. However, nonvolatile memory cells such as EEPROM can be used. Moreover, the number of memory cells forming the NAND cell is not limited to four, and the number of memory cells can be appropriately changed in accordance with specifications. Moreover, the structure for controlling the position of the data is not limited to FIGS. 15 to 55 degrees, and the structure can be appropriately changed according to specifications. Moreover, of course, it can be variously performed in the range which does not deviate from the summary of this invention.

As described above, according to the eighth and ninth embodiments, the row address for selecting the memory in the memory cell unit among the row addresses input from the outside is made to correspond to the higher address than the other selection of the row address for selecting the memory cell unit. Therefore, the possibility that the data of the same memory cell unit is next accessed is reduced as compared with the conventional case, so that the average access time is greatly reduced. Furthermore, a circuit can be provided which can select the correspondence between the external address and the internal address from a plurality of correspondences therebetween. Thus, the correspondence between external and internal addresses can be selected by external signals for shorter average access times.

On the other hand, the present invention can be carried out in various modifications within the scope not departing from the gist of course.

Claims (29)

A memory cell array having a plurality of memory cell units, each memory cell unit being formed of a plurality of memory cells, wherein a memory cell position within a memory cell array is designated by a row address, and each memory of the memory cell unit A plurality of register cells for provisionally storing data read out from the cell and provisionally storing data to be written to each memory cell of the memory cell unit, and for identifying whether these row addresses designate the same memory cell unit Identification means for comparing the row address of the current row address with the current row address, and data of the register cell during a read operation when the previous row address identifies that the same row cell stores the same memory cell as the current row address by the identification means. Characterized in that it comprises a reading means for reading directly Semiconductor memory. The data storage method according to claim 1, wherein data is written into a register cell during a write operation when the previous row address identifies that the same memory cell is designated as the current row address by the identification means. And a recording means for the semiconductor memory device. The semiconductor memory device according to claim 2, further comprising a register for refreshing to be selected during a refresh operation. A memory cell array having a plurality of memory cell units, formed of a plurality of memory cell units formed by connecting a plurality of memory cells in series, and in which the position of the memory cells in the memory cell array is designated by a row address; A plurality of register cells for temporarily storing data read out from each memory cell of the cell unit and for temporarily storing data to be written to each memory cell of the memory cell unit, whether these row addresses designate the same memory cell unit Identification means for comparing the previous row address with the current row address to identify whether or not, and during a write operation when the previous row address identifies by the identification means designating the same memory cell as the current row address; The memory cell can be read without reading the data of the memory cell once to the register cell. In addition to recording the data in the master cell, the semiconductor memory device, characterized in that configured by a recording means for storing the data in the memory cell. The semiconductor memory device according to claim 4, further comprising a register for refreshing to be selected during a refresh operation. In addition to having a plurality of memory cell units, each memory cell unit is formed by connecting a plurality of memory cells in series and connected to a bit line by bit line contacts, and a memory cell array of the data stored in the memory cell unit of the memory cell unit. And a control means for correcting the position. 7. The semiconductor memory device according to claim 6, wherein a register is provided for provisionally storing data, which is a total multiple of the number of memory cells of the memory cell unit, for the array of all rows of the memory cell units. In addition to having a plurality of memory cell units, each memory cell unit is formed by connecting a plurality of memory cells in series, and a memory cell array connected to a bit line by bit line contacts, and data of other memory cells of the memory cell unit. And control means for replacing data of an arbitrary memory cell of the memory cell unit with respect to the semiconductor memory device. 9. The semiconductor memory device according to claim 8, wherein a register is provided for provisionally storing data, which is a total multiple of the number of memory cells of the memory cell unit, for the array of all rows of the memory cell units. 9. The semiconductor memory device according to claim 8, wherein said control circuit replaces data of any memory cell of said memory cell unit with data of a memory cell closest to a bit line contact of said memory cell unit. 9. The apparatus of claim 8, wherein the control circuit for changing the position of the data moves data of any memory cell of the memory cell unit to the memory cell closest to the bit line contact, wherein the control circuit is further from the bit line contact. And a bit line contact to be stored in a visible continuously shifted memory cell and data stored in a memory cell existing between the arbitrary memory cell. The semiconductor memory device according to claim 8, wherein the control circuit is formed on the same substrate as the memory cell. 9. The semiconductor memory device according to claim 8, wherein the control circuit is formed on a substrate different from that of the memory cell and is commonly used for a plurality of memory chips. 9. The semiconductor memory device according to claim 8, wherein data is received / transmitted to the outside when data is read from the memory cell unit to the memory cell for temporarily storing. 9. The semiconductor memory device according to claim 8, wherein when data is stored in the memory cell unit from a register for provisional storage, data is received / transmitted to the outside. 12. The semiconductor memory device according to claim 11, wherein the data of the arbitrary memory cell is data accessed later from the outside of the chip. In addition to having a plurality of memory cell units, each memory cell unit is formed by connecting a plurality of memory cells in series, and a memory cell array connected to a bit line by bit line contacts, and data of other memory cells of the memory cell unit. And control means for copying data of an arbitrary memory cell of the memory cell unit with respect to the semiconductor memory device. 18. The semiconductor memory device according to claim 17, wherein a register is provided for temporarily storing data, which is a total multiple of the number of memory cells of the memory cell unit, for the array of all rows of the memory cell units. 18. The semiconductor memory device according to claim 17, wherein said control circuit copies data of any memory cell of said memory cell unit into data of a memory cell closest to a bit line contact. 18. The semiconductor memory device according to claim 17, wherein the control circuit is formed on the same substrate as the memory cell. 18. The semiconductor memory device according to claim 17, wherein the control circuit is formed on a substrate different from that of the memory cell, and is commonly used for a plurality of memory chips. 18. The semiconductor memory device according to claim 17, wherein data is received / transmitted to the outside when the data is read from the memory cell unit to the memory cell for provisional storage. 18. The semiconductor memory device according to claim 17, wherein data is received / transmitted to the outside when data is stored in a memory cell unit from a register for provisional storage. 20. The semiconductor memory device according to claim 19, wherein the data of said arbitrary memory cell is data accessed late from the outside of the chip. In addition to having a plurality of memory cell units, each memory cell unit is formed by connecting a plurality of memory cells in series, the memory cell array connected to the bit line by bit line contacts, an address bit for designating the memory cell unit, A memory cell corresponding to a bit position higher than a portion of an address bit of a row address for specifying a memory cell unit among the row addresses to be input from the outside, and a row address including address bits for designating a memory cell in the memory cell unit And a row decoder having a function of replacing another address bit of a row address for designating a memory cell in a unit. 26. The semiconductor memory device according to claim 25, further comprising a control circuit for replacing data of an arbitrary memory cell of said memory cell unit with data of a memory cell closest to said bit line contact. 26. The semiconductor memory device according to claim 25, further comprising a circuit for replacing the arrangement of the row addresses input from the outside due to the plurality of types of column decoders by the signals from the outside. 27. The semiconductor memory device according to claim 26, further comprising a circuit for replacing an arrangement of the row addresses input from the outside due to a plurality of types of said column decoders by signals from the outside. 27. The semiconductor memory device according to claim 26, wherein the data of said arbitrary memory cell is data accessed late from the outside of the chip.