JPH04291088A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable integrated writing operation selecting a bit line. CONSTITUTION:In a semiconductor storage device which selects a prescribed storage cell C and performs the writing operation to an applicable storage cell by means of a writing amplifier WA provided for each applicable data bus DB and bar DB via a bit line BL, bar BL, data bus DB and bar DB by selecting the bit line BL, bar BL and word line WL, a control circuit CNT outputting a control signal simultaneously actuating plural writing amplifier from among the applicable writing amplifier WA is connected to the respective writing amplifiers WA.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write circuit for writing cell information into memory cells constituting a semiconductor memory device. One type of DRAM is a dual-port memory with built-in serial access memory, which is particularly used as an image memory. Such DRAMs are required to operate at high speed, and in particular, in the case of image data, it is necessary to perform a write operation all at once to some of the memory cells arranged in a rectangular shape from among the large number of memory cells that make up the cell array. is needed.

0002

2. Description of the Related Art Some conventional DRAMs are equipped with a flash write function for high-speed writing. This flash write function writes the same cell information all at once to the memory cells connected to the selected word line, and is designed to be faster than the previous writing speed.

0003

[Problems to be Solved by the Invention] However, with the above-mentioned flash write function, it is possible to write in bulk only to memory cells connected to the same word line.
Since it is impossible to select a bit line and write data all at once, it is not possible to write the same data all at once to a large number of memory cells located in a rectangular shape within the cell array, or to write different data at random. Therefore, in such a case, there is a problem in that it is not possible to speed up the write operation.

[0004] An object of the present invention is to provide a semiconductor memory device that enables batch write operation by selecting bit lines.

[0005]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, a predetermined memory cell C is selected by selecting the bit lines BL, /BL and the word line WL, and the data is transmitted to the memory cell C via the bit lines BL, /BL and the data buses DB, /DB. A semiconductor memory device that performs a write operation with a write amplifier WA provided for each bus DB and bar DB, and a control signal that outputs a control signal to each write amplifier WA to simultaneously operate multiple write amplifiers from among the write amplifiers WA. A circuit CNT is connected.

[0006]

[Operation] The write amplifier WA selected by the control circuit CNT simultaneously performs a write operation for a plurality of bits.

[0007]

[Embodiment] A first embodiment embodying the present invention will be described below with reference to FIG. In this DRAM, one block is composed of 4 bits, and 4 pairs of bit lines BL0, /BL0
A predetermined memory cell C is selected from among a large number of memory cells C by selecting either one of -BL3 and /BL3 and one of a large number of word lines. Each bit line BL0,
Bars BL0 to BL3 and bar BL3 are connected to data buses DB3 and bar DB3 to DB0 via transfer gates Tr1, respectively.
, DB0, bit lines BL0, BL0
~Transfer gate T connected to each pair of BL3 and BL3
Column selection signals CL3 to CL0 are respectively input from the column decoder 1 to the gate of r1, and when the column selection signals CL3 to CL0 go to H level, each bit line BL0
, bar BL0 to BL3, bar BL3 are each data bus DB.
3, are connected to DB3 to DB0 and DB0, respectively. A column address signal AD is input to the column decoder 1, and the column selection signals CL0 to CL3 are outputted based on the column address signal AD.

Data bus DB0, DB0 to DB3,
Each pair of bar DB3 has a light amplifier WA0 to W.
A3 is connected, and write data WD is input to each. Each write amplifier WA0 to WA3 has a control circuit CN.
T0 to CNT3 are connected, and each control circuit CNT
0 to CNT3 are a write amplifier activation signal WL for activating write amplifiers WA0 to WA3, and a column mask signal for prohibiting activation of write amplifiers WA0 to WA3 even when the write amplifier activation signal WL is input. C
2-bit column address signals A0 and A1 for selecting M and control circuits CNT0 to CNT3 are input.

Such control circuits CNT0 to CNT3 activate the corresponding write amplifiers WA0 to WA with priority over the write amplifier activation signal WL based on the input of the column mask signal CM.
3 is prohibited, and the column address signal A0 is input while the write amplifier activation signal WL is input.
, A1, the corresponding light amplifier W
It is designed to activate A0 to WA3. and,
Data input/output is performed from this one block of cell array via one I/O device, and in a DRAM with a ×4 configuration (each block has bit lines for 4 bits), such a block has 4 bit lines. Consists of individuals.

Now, to explain the write operation in the DRAM configured as described above, in a normal write operation, when one of the word lines, for example, the word line WL1, is selected, each of the control circuits CNT0 to CNT3 is The write amplifier activation signal WL is input, and the column selection signals CL0 to CL3 go to H level based on the address signal input to the column decoder 1, and the bit lines BL0, BL0 to BL3, and BL3 are selected, and the control circuit C
Column address signal A0 input to NT0 to CNT3
, A1, the write amplifier activation signal WL is inputted only to the write amplifier WA0, and the write amplifier WA3 is activated. And that light amplifier WA
Based on the write data WD inputted to 0, write data WD is written from the same write amplifier WA3 to the memory cell C1 via the bit lines BL0 and /BL0.

On the other hand, when performing block writing, first, as with normal writing, a write amplifier activation signal WL is applied to each control circuit CNT0 to CNT3 with one of the word lines, for example, word line WL1, being selected.
is input, column selection signals CL0 to CL3 go to H level based on the address signal input to column decoder 1, and bit lines BL0, BL0 to BL3, and B
L3 is selected. In this state, each control circuit CNT0~C
Column address signals A0 and A1 input to NT3 select all write amplifiers WA0 to WA3, and at the same time column mask signal CM input to each control circuit CNT0 to CNT3 selects any write amplifier WA0 to WA3.
Write operation of WA3 is prohibited. As a result, write data W input to each write amplifier WA0 to WA3
Based on D, a write operation is simultaneously performed on the memory cell C selected by each bit in all or some of the write amplifiers WA0 to WA3 for which the write operation is not prohibited. Therefore, random data is written all at once into the memory cells C selected by each bit.

[0012] Furthermore, by utilizing the above-described configuration, a redundant circuit as shown in FIG. 3 can be constructed. That is, each data bus DB0, /DB0 to DB3, /DB
A common redundant data bus DB4, /DB4 is connected to each of the redundant data buses DB4, /DB4 through a transfer gate Tr2, and a bit line having the same configuration as each bit is connected to the redundant data bus DB4, /DB4. In addition, each data bus DB
A transfer gate Tr3 is interposed between bit lines 0, DB0 to DB3, and DB3. Each transfer gate Tr2, Tr3 has a transfer gate Tr corresponding to each data bus DB0, /DB0 to DB3, /DB3.
Redundant signals Φ0 to Φ3 are inputted from the redundant address decoder to the redundant address decoder 2, and redundant signals Φ0 to Φ3 are inputted to the transfer gate Tr3 via the inverter 2.

With this configuration, if a defect occurs in any bit, for example, a bit connected to the data bus DB0, /DB0, and the column address of the defective bit is set in the redundant address decoder, When the column address signal is input to the column decoder 1 and the redundant address decoder, the redundant signal Φ0 of H level is sent from the redundant address decoder to the transfer gate Tr.
2 and turns on the transfer gate Tr2, and the redundant signal Φ0 is inverted and input to the transfer gate Tr3 to turn off the transfer gate Tr3. Therefore, the data buses DB0 and /DB0 become redundant data buses. It is connected to the redundant bit via DB4 and /DB4.

Therefore, the bit in which a defective cell exists can be automatically switched to a redundant bit, and instead of replacing one entire block, only the bit in which a defective cell exists is switched to a redundant bit. Therefore, the area expansion of the cell array due to redundant bits can be reduced. This effect becomes more pronounced as the number of bits within one block increases.

[0015] In the above embodiment, the control circuits CNT0 to
Although the column mask signal CM is input to CNT3, each data bus DB0, DB0 to DB3,
A similar effect can be obtained by interposing a transfer gate Tr4 in each bar DB3 and inputting the column mask signal CM to the transfer gate Tr4.

[0016]

As described in detail above, the present invention exhibits the excellent effect of providing a semiconductor memory device that enables a batch write operation by selecting bit lines.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a redundant circuit of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment.

[Explanation of symbols]

BL, bar BL bit line WL word line C Memory cell DB, bar DB data bus WA light amplifier CNT control circuit

Claims (1)

[Claims] [Claim 1] A predetermined memory cell (C) is selected by selecting a bit line (BL, bar BL) and a word line (WL).
is selected and connected to the bit line (BL, BL,
A semiconductor memory device that performs a write operation with a write amplifier (WA) provided for each data bus (DB, bar DB) via a data bus (DB, bar DB), and a write operation for each write amplifier (WA). WA) is equipped with the light amplifier (
A semiconductor memory device characterized in that a control circuit (CNT) is connected to output a control signal for simultaneously operating a plurality of write amplifiers from WA.