JPH09139070A - Semiconductor storage system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the replacement of data by omitting the time for rewriting to a memory cell which has not been capable of being accessed from the outside of the chip. SOLUTION: The system uses plural memory cells selected by plural word lines and bit lines which mutually intersect in their arrangement, a register which stores temporarily the data of these memory cells, and a NAND type DRAM 20 provided with a control circuit which judges whether or not a signal AL1 that an instruction for replacement of data with the outside of the chip is delivered to the memory cell. When the control circuit 10 judges to be the replacement of data, both an output-enable signal (/OE) and write-enable signal (/WE) are generated during one cycle for data replacement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory system, and more particularly to a semiconductor memory system having a register for temporarily storing data in a memory cell.

[0002]

2. Description of the Related Art Conventionally, as a method of reducing the cost of a dynamic semiconductor memory device (DRAM), a technique of connecting a plurality of memories in series (NAND connection) to form a memory cell unit and reducing the cell area Has been known (JP-A-6-203552, etc.). This method is
Compared to the method of connecting each memory cell to the bit line, the number of bit line contacts is reduced, which is advantageous in that the cell area can be reduced.

In such a NAND type cell array system, when the data in the memory cell farther from the bit line in the memory cell unit is read, the data in the memory cell on the bit line side of the memory cell is destroyed. There must be. Therefore, a register for temporarily holding the data in the memory cell unit and performing rewriting is required. Therefore, in the DRAM having the NAND type cell array system, in addition to the time for reading the data from the memory cell to the outside of the chip, as shown in FIGS. 7 to 10, it is necessary to restore the data from the temporary storage register to the memory cell. It took time, and during this time, the memory cell could not be accessed. Therefore, even when data is replaced, the read data must be rewritten, and then new data must be written.

FIG. 11 is a timing chart when the read-modify-write operation of a general-purpose DRAM having a conventional NOR type memory cell is directly applied to the block serial mode of a NAND type DRAM.
As shown in FIG. 11, during one CAS cycle,
OE and / WE were sequentially set to "L" to rewrite the data. However, in the NAND type DRAM, since the data is serially read at high speed, / CAS needs to be toggled at high speed. Read operation cannot be realized. Further, in this case, the restore cycle cannot be omitted.

[0005]

As described above, the conventional NA
In a semiconductor memory device having a temporary storage register such as an ND type DRAM, even when data is replaced, time is required for restoration after data reading. Since the memory cells cannot be accessed during this time, it is difficult to perform high-speed data replacement.

The present invention has been made in view of the above circumstances, and an object thereof is to omit the time for rewriting to a memory cell that cannot be accessed from the outside of the conventional chip, thereby saving data. It is an object of the present invention to provide a semiconductor memory system capable of accelerating replacement.

[0007]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure. That is, according to the present invention, a plurality of memory cells selected by a plurality of word lines and bit lines arranged to intersect each other, a register for temporarily storing data of these memory cells, and an external device for the memory cells are provided. For a semiconductor memory device having a determination circuit for determining whether or not a signal for instructing data replacement has been input, if it is determined by the determination circuit that data replacement is performed,
A signal (output-enable) that enables data to be output to the outside during a cycle of reading data from the memory cell and storing the data in the temporary storage register during one cycle for data replacement; A semiconductor memory system having a memory control circuit, wherein both of a signal (write-enable) that enables writing of data to the memory cell from the outside are generated during a restore cycle from the temporary memory register to the memory cell. .

Here, preferred embodiments of the present invention include the following. (1) A circuit that determines whether or not a signal for instructing to replace all the data in the memory cells connected to the selected word line with the outside of the chip is included, and if it is determined that the replacement signal for all the data is included, Control to turn off all registers. (2) By omitting the time to control ON / OFF of the temporary storage register, a clock shorter than a normal read / write cycle optimized for data replacement is generated. (3) A circuit for determining whether or not a signal for instructing to replace all the data of the memory cells connected to the selected one word line with the outside of the chip is provided, and when it is determined that this signal is input, Control so as to selectively turn off only the registers corresponding to the memory cells connected to one word line. (4) The memory cell must be a dynamic memory cell consisting of 1 transistor / 1 capacitor. (5) A plurality of memory cell arrays configured by connecting a plurality of dynamic memory cells connected in series to each other and a plurality of memory cell units connected to a first bit line, and a plurality of memory cell units connected to the first bit line A first data node and a second data node arranged between the first transfer gate and the adjacent memory cell array and selectively connected to the first bit line via the first transfer gate. Is disposed between the sense amplifier and the memory cell, and is connected to at least one of the first data node and the second data node directly or via the second transfer gate. , At least one register for temporarily storing the data of the memory cell read from the memory cell unit and the data read to the first bit line. A gate control circuit for controlling the first transfer gate so as to disconnect the first data node of the sense amplifier and the first bit line when writing the data from the sense amplifier to the register. (6) In addition to the configuration of (5), the third transfer gate connected to each of the first data node and the second data node of the plurality of sense amplifiers, and connected via the third transfer gate. And a second register for storing the data of the memory cell via the second bit line pair. (7) In addition to the configuration of (6), a data transfer circuit provided between the second register and the second bit line is provided. (8) The DRAM and the memory control circuit are formed on one chip. (Operation) According to the present invention, when the data is replaced, the rewriting time of the read data from the temporary storage register to the memory cell is omitted, and the data is continuously written into the memory cell from outside the chip. By doing so, the time for replacing the data can be significantly shortened.
In addition, by controlling so that only the registers corresponding to the memory cells connected to the selected word line are selectively turned off, there is no need to recharge the register word line, and the power consumption can be reduced accordingly. it can. Further, by arranging the DRAM and the control circuit on one chip, there is no need to lay out the bus line for connecting them, so that the occupied area can be reduced and the speed can be increased.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. (First Embodiment) FIG. 1 is a block diagram showing a basic configuration of a NAND type DRAM and a memory control circuit according to the first embodiment of the present invention. FIG. 2 shows the NAND in FIG.
It is a block diagram showing a schematic structure of a type DRAM. 3 to 5 are circuit diagrams specifically showing the serial connection portion of the memory cells in FIG. 2, the temporary storage register and the sense amplifier.

First, the structure of the peripheral portion of the memory cell array will be described with reference to FIGS. Memory cell arrays 1 ₁ and 1 ₂ in which a plurality of memory cell units are arranged
Are arranged with the sense amplifier 7 in between. Dummy cell arrays 2 ₁ and 2 ₂ are provided at the ends of the memory cell arrays 1 ₁ and 1 ₂ , respectively. The memory cell MC and the dummy cell DC are cells of 1 transistor / 1 capacitor used in a normal DRAM.

The sense amplifier 7 is a CMOS flip-flop composed of nMOS transistors Q41 and Q42 and pMOS transistors Q43 and Q44. The equalizer circuit 6 is provided adjacent to the sense amplifier 7. The equalizing circuit 6 includes an nMOS transistor Q3 for precharge.
1, Q32 and an equalizing nMOS transistor Q33.

Rewriting registers 4 ₁ and 4 ₂ are arranged between the sense amplifier 7 and the equalizing circuit 6 and the memory cell arrays 1 ₁ and 1 ₂ . In this example register 4
₁ and 4 ₂ are configured by using the same memory cells MC used in the memory cell arrays 1 ₁ and 1 ₂ . Word line WL0 ～WL3, corresponding to 32 memory cell selected by / WL0 ~ / WL3, register 4 _1, 4 ₂
Register word lines RWL0 to RWL7 for each bit line
, RWL8 to RWL15 are arranged in 16 memory cells.

Each of the four bit lines BL0 to BL3 (first bit line) of _one memory cell array 11 is n
Are combined into one via a transfer gate 3 ₁ consisting of MOS transistors Q11 to Q14, the sense amplifier 7
Is connected to one of the data nodes N1. Each other four bit lines / BL0 ~ / BL3 of the memory cell 1 ₂ are combined into one via a transfer gate 3 ₂ consisting of nMOS transistors Q51～Q54, the other data nodes of the sense amplifier 7 N2 It is connected to the.

Data nodes N1 and N2 of the sense amplifier 7
Are respectively connected to the global bit line GB via a transfer gate 5 composed of nMOS transistors Q21 and Q22.
It is connected to L and / GBL (2nd bit line). The global bit lines GBL and / GBL are arranged over the memory cell arrays 1 ₁ and 1 ₂ , and are connected to a data input / output line (not shown).

The read / write gate control circuit 8 is for controlling each of the transfer gates 3 ₁ , 3 ₂ , 5 according to an address. The gate control circuit 8 basically transfers only the data of the bit line of interest among the data read from the memory cell to the bit line to the data node of the sense amplifier 7 and stores it in the registers 4 ₁ , 4 ₂ . The transfer gates 3 ₁ and 3 ₂ are controlled so as to rewrite the data node of interest with the bit line disconnected.

FIG. 6 shows a schematic structure of a general-purpose DRAM and a memory control circuit in the prior art corresponding to FIG. Conventionally, a memory control circuit corresponding to a NAND type DRAM has not been proposed.

The operation of the conventional memory control circuit will be described with reference to FIG. The control circuit 10 shown in the figure is a chip select signal / CS that is active during external access, read / write control signals R and / W that are "H" when the external access request is read, and "L" when the external access request is write, and an interval timer signal. φI is input to DRAM, / RAS, / CAS, / WE, / O
It outputs E and outputs a ready signal / RDY that is activated when preparation for an external access request is completed, and
Output enable signal / to various buffers 11-13
It outputs OE1 to / OE3.

The counter 14 in the figure is for generating a row address at the time of refreshing, and the count value is incremented by 1 at the rising edge of / OE1.
It has the same number of bits as the bit line of the M row address. The refresh address buffer 11 is / O
When E1 is activated, the count value of the counter 14 is output to the address bus as a row address. Row address buffer 12 outputs a row address signal to the address bus when / OE2 is activated. The column address buffer 13 has a COLU function when / OE3 is activated.
The MN address signal is output to the address bus. The interval timer 15 generates φI at regular intervals to generate refresh timing.

Reference numeral 16 in the drawing is an address buffer, 1
Reference numeral 7 is a buffer such as / RAS or / CAS, 20 is a memory cell array, 21 is a row decoder, 22 is a column decoder, 23 is a sense amplifier, and 24 is a data input buffer.

In the memory control circuit 10 for the NAND type DRAM of the present embodiment, in addition to this, a signal indicating whether or not the data is to be replaced with data outside the chip, particularly in the hard disk or disk cache, is input. As shown in FIG. 1, in the present embodiment, a signal of / AL1 is received, and this signal becomes "L" when replacing the data outside the chip, especially in the hard disk or disk cache. As will be described later, when this signal is input, / CAS, / W
E and / OE are controlled as shown in FIGS.

Next, the operation when an external access is requested will be described. First, when / CS becomes active, the control circuit 10 starts an access operation. The control circuit 10 checks the conflict with the refresh operation, and if there is no conflict, activates / OE2 to the row address buffer 12, outputs the row address through this address buffer 12, and activates / RAS. After a certain time,
/ OE2 is made inactive, / OE3 is made active, the column address is output, and then / CAS is made active. Further, according to the R and / W signals, / OE is activated in the read cycle and / OE in the write cycle.
Activate WE.

7 to 10 show read and write cycles in the prior art. 7 shows block-serial-mode-read, FIG. 8 shows block-serial-mode-write, and FIG. 9 shows first-page-
Mode-read, and FIG. 10 shows first-page-mode-write.

As shown in these figures, in the conventional memory control circuit, only / OE or / WE is activated during one cycle. Usually, data exchange between the main memory and the disk cache or the hard disk is data replacement in block units. Here, when the NAND type DRAM in the prior art is used as a main memory, data is exchanged with a hard disk or the like by first setting a read cycle and then temporarily storing the data by receiving a / OE signal generated in a memory control circuit. At the same time as the data is stored in the register, it is read out to a hard disk or the like, and then the memory cell is rewritten from this temporary storage register. Next, after setting the write cycle, the / WE signal generated in the memory control circuit is received, and the data sent from the hard disk or the like is first written in the temporary storage register and then written in the memory cell. When the data is replaced with a hard disk or the like in block units, the read data need not be rewritten.

Here, in the read-modify-write operation which has been conventionally used in the general-purpose DRAM, FIGS.
, / OE and / W during one CAS cycle
There is a problem that it is necessary to insert E, / CA cannot be toggled at high speed, and the restore cycle cannot be omitted. Therefore, as shown in FIGS. 13 and 14, at the time of rewriting from the temporary storage register to the memory cell during the read cycle and the write cycle, / WE and / CAS are toggled to write the memory from the outside. With control, time should be cut in half.

Incidentally, FIG. 11 shows a conventional read-modify-write cycle in a block of a NAND type DRAM.
FIG. 12 shows the first half of the time chart in which data is replaced by applying it to the serial mode as it is, and FIG. 12 shows the second half for the subsequent restoration. 13 is a time chart of data replacement in the block-serial mode in this embodiment, and FIG. 14 is a time chart of data replacement in the first-page mode in this embodiment.

Focusing on the above points, in the present embodiment, as shown in FIG. 1, first, it is determined whether or not the signal AL1 is inputted by the memory control circuit 10 as to whether or not the data is transferred in block units with the hard disk or the like. to decide. And this signal AL
When 1 is input, the restore cycle for originally rewriting from the temporary storage register to the memory cell as shown in FIGS. 7 and 8 is omitted, and the memory control circuit 10 toggles / WE and / CAS to set a hard disk or the like. To DRAM
Write data to Therefore, the memory control circuit 10 outputs both the / OE signal and the / WE signal during one cycle of data replacement.

Comparing FIGS. 13 and 14 with FIGS. 7 to 10, it is apparent that the time for replacing the data in units of blocks is significantly shortened in this embodiment as compared with the prior art. Further, when reading all the data of the memory cells connected to one word line, it is possible to reduce the power consumption by keeping the RWL OFF, and by optimizing the timing, it is possible to further increase the speed. Can be achieved. (Second Embodiment) FIGS. 15 to 18 are shown in FIGS.
2 shows an overall structure of a NAND type DRAM 1 chip including the basic structure shown in FIG. FIG. 15A is a diagram showing an overall schematic configuration of the NAND type DRAM of the present embodiment, in which four 64 Mbit memory cell arrays are arranged. 15 (b) and 15 (c) are partially enlarged views.

FIG. 16 shows a second sense amplifier for transferring data from the second bit line to the second register and a write buffer for writing data from the second register to the second bit line. FIG. 17 shows a specific configuration (a) of the second register and a data transfer control circuit (b). 18 shows a specific structure of the write buffer in FIG.

In this example, an I / O register for exchanging data with the outside of the chip, a write circuit for writing data from the I / O register to the second bit line, and a data write circuit for writing data from the second bit line to the I / O register. The control method of the read circuit for reading is changed according to a normal read / write cycle or replacement of data with a hard disk or the like.

Conventionally, at the time of rewriting from the temporary storage register to the memory cell, this I / O register and I / O register
The write circuit for writing data from the O register to the second bit line and the read circuit for reading data from the second bit line to the I / O register were turned off by the control circuit of FIG. 17B. Here, the memory control circuit 10 of FIG. 1 first determines whether or not data is to be replaced with a hard disk or the like, and if it is determined that the data is to be replaced, it is time to rewrite from the temporary storage register to the memory cell. 17B by issuing the / WE signal to
The NAND type DRAM is controlled so as to turn on the I / O register and the write buffer circuit for writing data from the I / O register to the second bit line through the control circuit.

FIG. 19 shows a timing chart corresponding to the data replacement mode according to this embodiment.
FIG. 19 (a) is block-serial-mode, (b)
Is the first-page-mode. For comparison, FIGS. 20 and 21 show timing charts at the time of reading and writing of the conventional type. FIG. 20 shows a block-serial mode, in which (a) is a read cycle and (b) is a write cycle. FIG. 21 shows the first-page mode, in which (a) is a read cycle and (b) is a write cycle.

Comparing FIG. 19 with FIGS. 20 and 21,
It can be seen that the data replacement time can be significantly reduced. (Third Embodiment) FIG. 22 is a block diagram showing a basic configuration of a memory control circuit and a NAND type DRAM according to a third embodiment of the present invention. The memory control circuit 10 in this embodiment generates two types of clocks, CK1 and CK2. CK1 gives a cycle for normal reading and writing of this DRAM. CK2 is a clock for using the DRAM as a main memory and for replacing all the cell data that appears on the bit line with the rise of the word line and the hard disk.

In this case, the signal AL2 indicating that all the data in the memory cells connected to the selected word line is replaced.
When is input, CK2 is output, and / WE and / CAS are output at the time of rewriting from the register to the memory cell to control all RWLs to be turned off. Therefore, not only the time for rewriting can be omitted, but also the clock cycle can be shortened, so that a higher speed can be achieved.

The present invention is not limited to the above embodiments. In the embodiment, the NAND type DRA
Although M has been described as an example, the present invention is not limited to this type of DRAM and can be applied to any semiconductor memory device having a temporary storage register. In addition, various modifications can be made without departing from the scope of the present invention.

[0035]

As described above, according to the present invention, by generating both the output-enable signal and the write-enable signal during one cycle for data replacement, the data of the external The time required for replacement can be significantly reduced. Further, when reading all the data of the memory cells connected to one word line, the power consumption can be reduced by controlling the register word line to be turned off.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a NAND DRAM and a memory control circuit according to a first embodiment.

FIG. 2 is a block diagram showing a schematic configuration of a NAND type DRAM in FIG.

3 is a circuit configuration diagram showing a part of a series connection portion of memory cells in the NAND type DRAM shown in FIG. 2;

4 is a circuit configuration diagram showing a temporary storage register and a sense amplifier in the NAND type DRAM shown in FIG.

5 is a circuit configuration diagram showing the remaining part of the serial connection of memory cells in the NAND type DRAM shown in FIG. 2;

FIG. 6 is a block diagram showing a basic configuration of a NAND DRAM and a memory control circuit according to a conventional technique.

FIG. 7 shows a timing of reading data in the block-serial mode according to the related art, which corresponds to the first embodiment of the present invention.

FIG. 8 is a diagram showing a timing of writing data in a block-serial mode according to a conventional technique corresponding to the first embodiment.

FIG. 9 is a diagram showing a timing of reading data in a fast-mode according to a conventional technique corresponding to the first embodiment.

FIG. 10 is a diagram showing a timing of writing data in a fast-mode according to a conventional technique corresponding to the first embodiment.

FIG. 11 shows a read-modify-write operation in a general-purpose DRAM having a NOR type cell,
FIG. 6 is a diagram showing the first half of a timing chart when applied to a block-serial mode in M of the related art.

FIG. 12 is a diagram showing a second half portion following FIG. 11.

FIG. 13 is a diagram showing the timing of data replacement in the block-serial mode according to the first embodiment.

FIG. 14 is a diagram showing a timing of data replacement in the first-page mode according to the first embodiment.

FIG. 15 is a NAND DRAM according to a second embodiment.
The figure which expands and shows the whole structure and a part of this chip.

FIG. 16 is a diagram showing a specific circuit configuration of a write buffer according to the second embodiment.

FIG. 17 is a diagram showing a specific configuration of a second register and a data transfer control circuit according to the second embodiment.

FIG. 18 is a diagram showing a specific circuit configuration of a write buffer according to the second embodiment.

FIG. 19 is a diagram showing a timing of data replacement in the block-serial mode and the first-page mode in the second embodiment.

FIG. 20 is a diagram showing the timing of reading and writing data in the block-serial mode according to the conventional technique, which corresponds to the second embodiment.

FIG. 21 is a diagram corresponding to the second embodiment and showing the timing of data reading and writing in the first-page-mode in the conventional technique.

FIG. 22 is a NAND DRAM according to a third embodiment.
3 is a block diagram showing the basic configuration of a memory control circuit. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Dummy cell array 3 ... Transfer gate 4 ... Rewriting register 5 ... Transfer gate 6 ... Equalize circuit 7 ... Sense amplifier 8 ... Gate control circuit 10 ... Control circuit 11 ... Refresh address buffer 12 ... Row address Buffer 13 ... Column address buffer 14 ... Refresh counter 15 ... Interval timer 16 ... Address buffer 20 ... Memory cell array 21 ... Row decoder 22 ... Column decoder 23 ... Sense amplifier 24 ... Data input buffer

Claims (1)

[Claims] 1. A plurality of memory cells selected by a plurality of word lines and bit lines arranged to cross each other, and a register for temporarily storing data of these memory cells.
For a semiconductor memory device having a determination circuit that determines whether or not a signal for instructing the replacement of data with the outside has been input to the memory cell, if the determination circuit determines that the data is to be replaced, A signal (output-enable) that enables data to be output to the outside during a cycle of reading data from the memory cell and storing to a temporary storage register during one cycle for replacement; A semiconductor memory system having a memory control circuit, wherein both of a signal (write-enable) that enables writing of data to the memory cell from the outside are generated during a restore cycle from a memory register to the memory cell.