JPH06251580A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform a write-in and a read-out at a same time by connecting each bit line to plural sense-amplifiers and equalizers to form a port and by making a column decoder to operate a write-in/read-out independently with the combination of bit lines consisting of a port. CONSTITUTION:A bit line connected to a cell shown by hatched lines is BL3, bit pair lines consisting of bit pair lines with BL3 are bit lines BL2, BL4, Bit lines consisting of BL2 and BL3 are connected to equalizers A and a sense- amplifier A and accessible with a port, A via the column decoder A and a data bus A. Thus, at the time of the write-in from the side of the port A, a write-in data is applied to a memory cell by selecting a word line WL3,1ines BL2, BL3. At the time of the read-out. the data in a desired memory cell is read-out via the column decoder A and the data bus A by changing electric charge on bit lines while applying a pre-charge voltage Vpc potential on lines from the equalizer A and by amplifying the changed part of the electric potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory.

[0002]

2. Description of the Related Art The problems that semiconductor memory circuits have are miniaturization, higher integration, higher speed, and improved utilization efficiency.
Conventionally, as a technique for improving the utilization efficiency of this semiconductor memory circuit, for example, a dual port RAM (Random) is used.
Access Memory) is known, and a plurality of MPUs are used in processing such as controlling a plurality of systems.
By interposing the common memory of the dual port RAM with respect to (Micro Processing Unit), the delivery time of data between MPUs and the software are simplified.

FIG. 6 is a circuit diagram of a dual-port RAM composed of a static type memory cell of the first conventional example. Word lines W and bit lines are Wr and W, respectively.
It consists of r *, Ww and BLw, BLw *, BLr, BLr *, and one memory cell is connected to the intersection of the word line W and the bit line BL pair. At the time of writing to this memory cell, the word line Ww, the bit lines BLw, BLw
* Is selected, write data Dw and Dw * are given,
At the time of reading, the word line Wr and the bit line BLr are selected and the read data Dr is obtained. Then, if there is an access from another route at the same time, the word line Wr * and the bit line BLr * are selected and the inverted read data Dr * can be obtained, and the double read access becomes possible.

FIG. 7 shows a dual port RAM composed of a dynamic memory cell of the second conventional example.
FIG. 9 is a circuit diagram of the present invention and can be applied to the cell array including the general dynamic memory cell shown in FIG. This memory cell is composed of two bit lines, each bit line pair (for example, BL1 and BL2, BL3 and BL in FIG. 8).
4, BL (n-1) and BLn) are provided with one sense amplifier and one equalizer, and each bit line uses the first column decoder CD1 and the first gate G1 to read / write the first port. It is commonly connected to the write bus BS1 and is connected to the read bus BS2 which is the second port by using the second column decoder CD2 and the first gate G2. As a dual port RAM using this dynamic type memory cell, for example, there is one disclosed in Japanese Patent Publication No. 4-59713.

[0005]

However, the conventional dual port RAM has the following problems. (1) It is difficult to achieve high integration with a conventional dual port RAM using static memory cells. (2) In the conventional dual-port RAM using dynamic memory cells, one port cannot perform a write operation, and both write and read operations cannot be performed from two ports.

Therefore, an object of the present invention is to eliminate the above-mentioned problems and to provide a highly integrated semiconductor memory capable of simultaneously performing both write and read operations from a plurality of ports without increasing the chip area. To do.

[0007]

In order to achieve the above-mentioned object, the present invention provides a plurality of word lines, a plurality of bit lines, and a dynamic memory cell provided near the intersection of the word lines and the bit lines. In a semiconductor memory including a sense amplifier connected to a bit line for refreshing data held in each of the dynamic memory cells, an equalizer for equalizing potentials of bit line pairs, and a column decoder for selecting each bit line, The bit line is connected to a plurality of sense amplifiers and a plurality of equalizers to form a plurality of ports, and the column decoder can independently control the write / read operation for the combination of bit lines that compose this port. To choose.

[0008]

According to the present invention, a plurality of sense amplifiers and a plurality of equalizers are connected to a bit line connected to a dynamic memory cell of a semiconductor memory, and two of these bit lines are selected to select a bit line pair. By configuring
It is possible to configure a plurality of ports to which the sense amplifier and the equalizer are respectively connected. Then, the combination of the bit lines forming this port is selected so that the column decoder can independently control the write / read operation.

In the case of a dual port, for example, this combination of bit lines can be realized by connecting adjacent bit lines with a sense amplifier and an equalizer without fail. With this configuration, the equalizer A for the port A, The data A is read and written by the sense amplifier A, the column decoder A, and the data bus A, and the data B is read and written by the equalizer B, the sense amplifier B, the column decoder B, and the data bus B for the port B. A dual-port RAM that can be written to so that the two ports can perform both write and read operations equivalently
Can be realized while suppressing an increase in chip area.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings. [Configuration of Semiconductor Memory According to First Embodiment of the Present Invention] FIG. 1 is a circuit configuration diagram of a semiconductor memory according to a first embodiment of the present invention. This figure shows the case of a dual port RAM having two ports, port A and port B, and the sense amplifier, equalizer, column decoder, and data bus of each port are represented by the symbols A and B.

A pair of two adjacent bit lines is provided between the pair of bit lines, and a sense amplifier for refreshing the data held in the dynamic memory cell and an equalizer for equalizing the potentials of the pair of bit lines are installed. Bit lines are always connected by a sense amplifier and an equalizer. That is, two sense amplifiers and an equalizer connected to different bit lines are connected to a certain bit line. A block unit diagram of the dynamic memory cell of FIG. 2 shows one structural unit for connecting the sense amplifier and the equalizer to the bit line. The memory cell in the figure is a dynamic memory cell having one transistor and one capacitor, and at the time of writing, the word line WL and the bit line BL are selected and write data is given to the memory cell. On the other hand, at the time of reading, first, the precharge voltage Vpc potential is applied from the equalizer, the bit line potential is changed, the potential change amount is amplified by the sense amplifier, and the data of the desired memory cell is read through the column decoder and the data bus. .

With respect to the connection state of the sense amplifier and the equalizer, for example, focusing on the bit line BL2 in FIG. 1, the bit lines adjacent to the bit line BL2 are the bit line BL1 and the bit line BL3, and the bit line BL2 and the bit line BL2. A sense amplifier B and an equalizer B are connected between the lines BL1, and a sense amplifier A and an equalizer A are connected between the bit lines BL2 and BL3.

Comparing this configuration with the general dynamic memory cell of FIG. 8, the semiconductor memory of the present invention shows that
The number of ports is increased by connecting a sense amplifier and an equalizer between bit lines that have not been connected in the past. For example, in FIG. 8, the bit line BL2 is connected to the bit line BL1 via the sense amplifier and the equalizer, but is not connected to the bit line BL3, whereas in the cell array of the present invention, the bit line BL2 in FIG. 3, the bit line BL2 is connected to the bit line BL1 via the sense amplifier B and the equalizer B, and is connected to the bit line BL3 via the sense amplifier A and the equalizer A. [Operation of Semiconductor Memory of Present Invention] Next, an access operation to the cell array of the semiconductor memory of the present invention will be described with reference to FIGS. FIG. 3 is a diagram for explaining the access operation to the cell array from the port A to which the data bus A is connected, and FIG. 4 is a diagram to explain the access operation to the cell array from the port B to which the data bus B is connected. It is a figure. Here, a cell (indicated by diagonal lines) at an intersection of a word line WL3 (indicated by a thick vertical solid line in the figure) and a bit line BL3 (indicated above a horizontal thick solid line in the figure). The access operation will be described.

First, the access operation from the port A will be described. In FIG. 3, the bit line connected to the cell of interest indicated by the diagonal lines is BL3, and it is the bit line BL2 and the bit line BL4 that form a bit line pair with this bit line BL3. Of these two bit line pairs, the bit line pair consisting of the bit line BL3 and the bit line BL2 is connected to the equalizer A and the sense amplifier A, and the port A can be accessed via the column decoder A and the data bus A. Although it is possible, the bit line pair consisting of the bit line BL3 and the bit line BL4 is connected to the equalizer B and the sense amplifier B and cannot access the port A.

As a result, at the time of writing from the port A side, the word line WL3 and the bit lines BL2, BL3 are selected and write data is given to the memory cell, and at the time of reading, the precharge voltage Vpc potential is supplied from the equalizer A. The bit line potential is applied, the potential change is amplified by the sense amplifier A, and the data of the desired memory cell is read out through the column decoder A and the data bus A.

Next, the access operation from the port B will be described. In FIG. 4, when the cell of interest is shown as the same cell as that of FIG. 3 by hatching, the bit line connected to this cell is BL3.
A bit line BL2 and a bit line BL4 form a bit line pair with 3. Of these two bit line pairs, the bit line pair consisting of the bit line BL3 and the bit line BL4 is connected to the equalizer B and the sense amplifier B, and the port B can be accessed via the column decoder B and the data bus B. Although it is possible, the bit line pair consisting of the bit line BL3 and the bit line BL2 is connected to the equalizer A and the sense amplifier A and cannot access the port B.

As a result, at the time of writing from the port B side, the word line WL3 and the bit lines BL3 and BL4 are selected and write data is given to the memory cell, and at the time of reading, the precharge voltage Vpc potential is supplied from the equalizer B. The bit line is changed, the potential change is amplified by the sense amplifier B, and the column decoder B and the data bus B are supplied.
Through, the data of the desired memory cell is read.

Therefore, it is possible to construct a dual port RAM capable of performing both read and write operations from either port with the same chip area as the conventional DRAM without increasing the chip area. [Configuration Example Using Semiconductor Memory of the Present Invention] Next, using the semiconductor memory of the present invention, a 1-megabit dual port R
An example of the structure of the AM is shown in the diagram of FIG.

Two cell arrays each having a capacity of 512 kilobits are used.
A single 1-megabit dual-port RAM is constructed by using them. The two 512 kbit cell arrays each have a column decoder A and a column decoder B connected to port A and port B respectively. Each column decoder A has a column address A, and each column decoder B has a column address A. The addresses of address B are input independently.
The addresses of the row address A and the row address B are input to the row decoder of each 512 kbit cell array via the row address arbitration unit. Each port A, B
Writes or reads data to or from the cell selected by the address via the data buses A and B.

Further, a refresh controller for controlling a refresh operation for preventing loss of stored information in the dynamic memory cell is provided, and a refresh signal is sent out through the row address arbitration unit. The row address arbitration unit controls the transmission of the refresh signal from the refresh control unit and the input address of the row addresses A and B to the row decoder. If necessary for access during the refresh cycle, each row address arbitration unit Sends a BUSY signal back to the external device.

In the above embodiment, two 51
Although a 2-megabit cell array constitutes a 1-megabit dual-port RAM, it is possible to increase the capacity of the dual-port RAM by increasing the number of cell arrays used. [Structure of Semiconductor Memory of Second Embodiment of Present Invention] FIG.
FIG. 11 is a diagram showing a bit line combination state of the semiconductor memory configuration of the first embodiment, and FIG. 10 is a diagram showing a bit line combination state of the semiconductor memory configuration of the second embodiment.

FIG. 9 is a rewrite of the configuration of the semiconductor memory shown in FIG. 1 in which the bit line pairs to which the sense amplifier A and the equalizer A are connected are A1-A1, A2-A2 ...
, And the bit line pair to which the sense amplifier B and the equalizer B are connected is represented by a pair of B1-B1, B2-B2 ... Note that the sense amplifier, equalizer, column decoder, data bus, etc. are omitted.

FIG. 10 shows the configuration of the semiconductor memory of the second embodiment of the present invention in the notation of FIG. The bit line pairs A1, A2, ... Connected to the port A and to which the sense amplifier A and the equalizer A are connected are the same as the combination of the first embodiment, but are connected to the port B.
The bit line pair B1, B2, ... To which the sense amplifier B and the equalizer B are connected is a combination in which the other two bit lines are sandwiched between the bit line pair. For example, the bit line pair B3 is a combination in which the bit line B2 and the bit line B4 are sandwiched between two bit lines B3, and the bit line pair B3.
4 is a combination in which the bit line B3 and the bit line B5 are sandwiched between two bit lines B4. The combination of the bit line pair for the port B is different from the bit line pair for the port A and the port B of the first embodiment, and one of the two bit lines is not connected to the memory cell. Is set by following the principle of the read operation of the dynamic memory cell. [Structure of Semiconductor Memory of Third Embodiment of the Present Invention] FIG.
FIG. 9 is a diagram showing a combination state of bit lines according to a third embodiment of the present invention.

The third embodiment constitutes a multiport semiconductor memory, and FIG. 11 shows a combination state of bit line pairs from port A to port F. The principle of the read operation of the dynamic memory cell in which the combination of bit lines for each port is different from the combination of bit lines for other ports, and one of the two bit lines is not connected to the memory cell. Set by following.

For example, bit line pair B for port B
1, B2 ... Are bit line pairs A1, A2 for port A
The port C is a combination that is shifted by 1 bit line with respect to ...
The bit line pair C1, C2 ... Is a combination in which two other bit lines are sandwiched between the bit line pairs as in the second embodiment, and the bit line pair D for the port D is
1, 2 are sandwiched between the bit line pairs C1 and C2, like the other two bit lines, and are a combination different from the bit line pairs C1 and C2. E1, E2 ... Are combinations of the other four bit lines sandwiched between the bit line pairs, and the bit line pair F1, F2 ... Bit line pair E and bit line pair E
1 and E2 are different combinations.

In the figure, the combination of bit line pairs for the six ports A to F is shown, but it is also possible to construct a multiport in which the number of ports is further increased. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0027]

As described above, according to the present invention,
Using a dynamic memory cell that can be easily highly integrated,
It is possible to realize a highly integrated semiconductor memory capable of performing both write and read operations simultaneously from a plurality of ports in an area similar to that of a DRAM without increasing the chip area.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a dynamic memory cell.

FIG. 3 is a diagram illustrating an access operation to a cell array from port A of the semiconductor memory of the present invention.

FIG. 4 is a diagram explaining an access operation to a cell array from a port B of the semiconductor memory of the present invention.

FIG. 5: 1 megabit using the semiconductor memory of the present invention
2 is a diagram of a dual port RAM.

FIG. 6 is a circuit diagram of a dual port RAM composed of static memory cells of a first conventional example.

FIG. 7 is a circuit diagram of a dual port RAM composed of a dynamic memory cell of a second conventional example.

FIG. 8 is a configuration diagram of a general dynamic memory cell.

FIG. 9 is a diagram showing a combination state of bit lines in the configuration of the semiconductor memory of the first embodiment.

FIG. 10 is a diagram showing a combination state of bit lines in the configuration of the semiconductor memory of the second embodiment.

FIG. 11 is a diagram showing a combination state of bit lines in the configuration of the semiconductor memory according to the third exemplary embodiment of the present invention.

[Explanation of symbols]

 BL1 to BLn Bit line WL1 to WLm Word line

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit lines,
A dynamic memory cell provided near the intersection of the word line and the bit line, a sense amplifier connected to the bit line for refreshing the data held in each dynamic memory cell, an equalizer for equalizing the potentials of the bit line pairs, In a semiconductor memory provided with a column decoder for selecting the bit line, each bit line is connected to a plurality of sense amplifiers and a plurality of equalizers to form a plurality of ports, and the bit lines forming the ports In the semiconductor memory, the column decoder enables independent control of write / read operations.