JPH04222986A - Semiconductor memory device and data writing method of semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten the writing time by successively selecting each word line without resetting each sense amplifier and each bit line and writing-in respectively the same data into many numbers of cells connecting to the same bit line. CONSTITUTION:Based on an address signal, the word line WL is selected by a row decoder 2 and also the bit lines BL, -BL is selected by a column decorder 3. Hence the prescribed storage cell is selected from among many numbers of storage cells 4. The writing and reading of the data are performed by a sense amplifier 5 provided on every each bit line BL, -BL with respect to the selected storage cell 4. When the same data is written in many numbers of storage cells 4 connecting to the same bit line, each sense amplifier 5 is activated to write-in and house the data. In this state, the address signal successively selecting each word line WL is outputted from a control device 1. Thus, in the semiconductor memory device, the time required to write-in and read-out is shortened and the power consumption is suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. Semiconductor memory devices are required to operate faster and consume less power. Therefore, there is a need to shorten the time required to rewrite data stored in a storage device into uniform data and to reduce power consumption.

0002

2. Description of the Related Art A data write operation in a conventional DRAM will be explained with reference to FIG. A word line based on the address is selected and raised by a word line driver built in the row decoder (step 2). Then, in this state, data is input to the sense amplifier selected by the column decoder, and data is written from the sense amplifier to the memory cell via the corresponding bit line (step 3). Then,
The word line selected by the word line driver is brought down (step 4), the output level of the sense amplifier is reset to an intermediate level between H level and L level, and the potential of the bit line is also brought to that intermediate level. It is reset (step 5). When a write operation is performed on a large number of memory cells, such an operation is repeated.

0003

[Problem to be solved by the invention] DRAM as described above
In this case, the above operation is repeated even when writing the same data to a large number of memory cells, so when writing data to each sense amplifier and resetting it, charging the bit line corresponding to the written data and the same bit line. Each time a discharge is performed to reset the bit line to an intermediate level, a current flows through the sense amplifier and the bit line, consuming power. Further, since the operations of steps 1 to 5 are performed when writing the same data to each memory cell, there is a problem that the time required for the writing becomes long.

An object of the present invention is to provide a semiconductor memory device that can shorten the time required for writing the same data into a large number of memory cells and reduce power consumption.

[0005]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, in the semiconductor memory device shown in FIG. 1, the row decoder 2 selects the word line WL based on the address signal, and the column decoder 3 selects the bit lines BL, B.
By selecting the L bar, a predetermined memory cell is selected from a large number of memory cells 4, and data is transmitted to the selected memory cell 4 via the sense amplifier 5 provided for each bit line BL and BL bar. Writing and reading are performed. When writing the same data to a large number of memory cells 4 connected to the same bit line, the control device activates each sense amplifier 5 at the same time and outputs an address signal that sequentially selects each word line WL while storing the write data. 1 is provided.

Furthermore, when writing the same data to a large number of memory cells, a column decoder simultaneously activates a plurality of sense amplifiers to store the write data and simultaneously selects the bit line corresponding to each sense amplifier. The row decoder now selects word lines sequentially.

[0007]

[Operation] Each word line WL is sequentially selected without resetting each sense amplifier 5 and bit lines BL, BL bar, and the same data is written into each of a large number of memory cells 4 connected to the same bit line.

[0008]

[Example] An example embodying this invention is shown below in Figure 2.
- Explanation will be made according to FIG. 5. FIG. 2 schematically shows a DRAM, and an address signal generation circuit 1 receives an address selection signal AD from an external circuit, and based on the address selection signal AD, a row address signal is inputted to a row decoder 2, and a column decoder 2 receives a row address signal. A column address signal is input to 3.

The row decoder 2 has a large number of word lines WL1.
-WLn are connected, and the row decoder 2 selects one of the word lines based on the row address signal and raises the potential of the word line to H level. Each word line WL1
A plurality of memory cells 4 are connected to each of ~WLn, and the memory cells 4 connected to the word line selected by the row decoder 2 are activated and data can be written or stored data can be read. Become.

A large number of sense amplifiers 5 are connected to the column decoder 3, and each sense amplifier 5 is connected to a pair of bit lines BL1, BL1 bar to BLn, BLn bar, as well as a data bus (not shown). The data bus is connected to a data input/output device (not shown).
is connected. Then, the column decoder 3 selects a sense amplifier 5 based on the column address signal, and the selected sense amplifier 5 is connected to a data input/output device and becomes capable of inputting and outputting data, and also uses the selected word line to The bit line BL is connected to the activated memory cell 4.
Data can be written or read via bars 1 to BLn.

Then, the address generation circuit 1 outputs a row address signal to the row decoder 2 to sequentially select any one word line based on the address selection signal AD,
A column address signal for sequentially selecting any one sense amplifier 5 or a column address signal for simultaneously selecting a plurality of sense amplifiers 5 is output to the column decoder.

Next, the operation of the DRAM configured as described above will be explained with reference to FIGS. 3 to 5. Now, this DRA
To explain the operation when writing the same cell information to the memory cells 4 connected to each bit line BL1 to BLn bar in M, first, as shown in FIG. A row address signal corresponding to WL is input, a row address based on the row address signal is decoded (step 11), and then a word line WL is input based on the decoded row address.
1 is selected and raised by the word line driver built into the row decoder 2 (step 12). In this state, each sense amplifier 5 is simultaneously selected by the column decoder 3 based on the column address signal output from the address signal generation circuit 1 to the column decoder 3, and sense amplifier data as shown in FIG. 5 is input, for example. Data is input from the output device and written from the sense amplifier to each memory cell 4 via the corresponding bit lines BL1 to BLn (step 13). As a result, as shown in FIG. 5, the sense amplifier data stored in each sense amplifier 5 is written into each memory cell 4 connected to word line WL1.

Next, the word line WL1 selected by the word line driver is brought down (step 1).
4) Next, the row address signal corresponding to the word line WL2 is input to the row decoder 2, and the row address based on the row address signal is decoded (step 15).
Then, word line WL2 is selected based on the decoded row address and is started up by the word line driver built in row decoder 2 (step 16). Then, sense amplifier data is written from each activated sense amplifier 5 to each memory cell 4 via the corresponding bit lines BL1 to BLn, and the selected word line WL2 is brought down (step 17).

Then, the operations of steps 15 to 17 are repeated for the other word lines WL3 to WLn, and then the output level of each sense amplifier 5 becomes H level and L level.
The potential of each bit line BL1 to BLn is also reset to the intermediate level (step 18), and the write operation is completed. In addition, when reading cell information written as described above, each sense amplifier 5
are individually selected, and cell information is read from the memory cells activated by the selected word lines.

As described above, in this DRAM, when writing the same cell information to the memory cells 4 connected to each bit line BL1 to BLn, the sense amplifiers 5 are activated simultaneously as shown in FIG. Each word line WL1 to W is output with write data output to the lines BL1 to BLn.
Since Ln is sequentially selected and raised, the data input to the sense amplifier 5 is sequentially written into the memory cells 4 connected to the respective bit lines BL1 to BLn. Therefore, as each word line WL1 to WLn rises and falls, the sense amplifier 5 and the bit lines BL1 to BL1 to
Since BLn is not reset, power consumption can be reduced and the time required for writing can be shortened.

In the above embodiment, the word lines WL1 to WLn are sequentially selected to write the same data into each memory cell 4, but if one of the word lines WL1 to WLn is not selected, the connection is made to the unselected word line. No data is written to the memory cells that have been updated, and the previous cell information is maintained. Further, if several word lines WL1 to WLn are selected at the same time, the writing time can be further shortened.

[0017]

As described in detail above, the present invention exhibits the excellent effect of shortening the time required for writing when writing the same data into a large number of memory cells, and reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram of a semiconductor memory device showing one embodiment of the present invention.

FIG. 3 is a flowchart diagram showing the operation of one embodiment.

FIG. 4 is a waveform diagram showing the operation of one embodiment.

FIG. 5 is a storage cell content diagram showing the operation of one embodiment.

FIG. 6 is a flowchart showing the operation of a conventional example.

[Explanation of symbols]

1 Control device 2 Row decoder 3 Column decoder 4. Memory cell 5 Sense amplifier BL, BL bar bit line WL word line

Claims (2)

[Claims] 1. A large number of memory cells (4 ) is selected, and a sense amplifier (5) provided for each bit line (BL, BL bar) is selected for the selected memory cell (4).
) is a semiconductor memory device that writes and reads data through a memory cell (4) connected to the same bit line, and when writing the same data to a large number of memory cells (4) connected to the same bit line, each sense amplifier (5) is simultaneously activated and the write data is read. 1. A semiconductor memory device comprising a control device (1) that outputs an address signal that sequentially selects each word line (WL) in a state in which a word line (WL) is stored. [Claim 2] When writing the same data to a large number of memory cells, a column decoder simultaneously activates a plurality of sense amplifiers to store the write data, simultaneously selects a bit line corresponding to each sense amplifier, and in this state. A data writing method for a semiconductor memory device, characterized in that word lines are sequentially selected by a row decoder.