JPH05250869A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an electric power consumption and to shorten a cycle time by providing an empty memory cell unit on each bit line of a memory cell array and writing into the empty unit at the same time when data is read out time-sequentially. CONSTITUTION:Besides a NAND type memory cell unit an empty memory cell unit is provided on a memory cell array 11 and cell data is written into the empty memory cell unit at the same time when it is read out time- sequentially. Also, an internal address is transformed and stored between a unit where specified data is stored before it is read out and a unit where the data read out of this written by an address translation circuit 14 and when an address from the outside is inputted, the translated internal address is outputted. Thus, the previous rewriting for the electric charging/discharging of a large capacity global bit line is made unnecessary and the electric power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) having a memory cell of one transistor / one capacitor, and more particularly to a DRAM in which a plurality of memory cells are connected in series to form a memory cell unit. Regarding

[0002]

2. Description of the Related Art Among DRAMs, a memory cell unit (hereinafter referred to as a NAND type memory cell unit) in which a plurality of memory cells are connected in series is known. This cell array method has an advantage that the cell area is reduced because the number of contacts between the bit line and the memory cell is reduced.

In this cell array type DRAM, in order to rewrite at the time of data reading, a register for reading data of a plurality of memory cells in the memory cell unit in time series and temporarily holding the data is required. .. As a layout method of this temporary register, a method of sharing a register among a plurality of bit line sense amplifiers has been proposed (19
1991 IEEE ISSCC DIGEST OF TECHNICAL PAPERS VOL.34
p106 TAM6.2). This is a method in which a bit line sense amplifier provided in the bit lines of a plurality of memory cell blocks is connected to a global bit line via a transfer gate, and a temporary register is connected to this global bit line.

However, according to this method, the global bit line having a capacity larger than that of the bit line must be charged / discharged in order to rewrite data, resulting in a large power consumption. In addition, since it is necessary to store all the data of a plurality of memory cells connected in series in a temporary register and then re-write the data, the re-writing is required as compared with the conventional DRAM in which the data read to the bit line is re-written at the same time. There has been a problem that the time required for the process is long, and therefore the cycle time is long.

[0005]

As described above, the conventional N
In the DRAM forming the AND type memory cell unit, a temporary register for rewriting is shared by a plurality of bit line sense amplifiers, and after reading data, the data is read again to the memory cell unit via a large-capacity global bit line. Since writing is performed, there are problems that the power consumption is large and the cycle time is long.

The present invention has been made in consideration of such circumstances, and an object of the present invention is to provide a DRAM having a NAND type memory cell unit capable of reducing power consumption and cycle time.

[0007]

A DRAM according to the present invention
Is a matrix arrangement of memory cell units in which a plurality of 1-transistor / 1-capacitor memory cells are connected in series, and an empty memory cell unit is connected to each bit line in addition to a memory cell unit having a predetermined data storage capacity. Has a memory cell array. The empty memory cell unit is different from the dummy cells and spare cells normally provided in the DRAM. Further, there is provided a means for writing data read from a certain memory cell unit to a bit line at the time of reading and writing to a memory cell unit which is empty at that time connected to the bit line through a bit line sense amplifier, and at the time of reading and writing, The address is converted between the memory cell unit in which the predetermined data is stored before reading and writing and the memory cell unit in which the data read from this is written, and this is stored in the address register. Address translation means is provided for outputting the translated internal address when the address is input from.

[0008]

In the NAND type DRAM according to the present invention, as a conventional temporary register for rewriting, apart from a memory cell unit having a predetermined storage capacity in the memory cell array, an empty structure similar to these is used. A memory cell unit is provided. Data of a plurality of memory cells in the memory cell unit is read in time series, and at the same time, data is written to an empty memory cell unit via the bit line sense amplifier. Therefore, there is no need to perform rewriting with charge / discharge of a large-capacity global bit line after reading data, as in the conventional case.
The power consumption of M and the cycle time can be shortened.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAND according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a main part of a type DRAM. Reference numeral 11 is a memory cell array, 12 is a row decoder, 13 is a column decoder, 14 is an address conversion circuit, and 15 is an input / output buffer.

FIG. 2 shows the structure of the memory cell array. In this embodiment, a plurality of memory cell units MU _ij (i = 0, 1, ..., J = 0, 1, ...) Are used in the open bit line system.
Are arranged in a matrix. In this example, each memory cell unit is configured by connecting four memory cells MC _{0 to} MC ₃ of one transistor / one capacitor in series, as shown in FIG. 2B, and one end of the memory cell unit. The storage node on the side is connected to the bit line BL via a transistor. Although not shown in detail, the bit line sense amplifiers 21 ₀ , 21 ₁ , ... Connected to the bit line BL are composed of CMOS dynamic flip-flops used in a normal DRAM.
Here, the bit line sense amplifier 21 is shown as including an equalize circuit EQL and an input / output gate (DQ gate).

Unit numbers 0, 1, ..., M, m + 1 are shown along the bit lines of the memory cell array. However, m memory cell units have a predetermined storage amount (the number of data per bit line is 4). Xm) is an indispensable memory cell unit. The remaining one memory cell unit is
It is a spare memory cell unit for writing the read data each time it is read and written. The spare memory cell unit mentioned here is different from a dummy cell that normally stores a reference potential required for a DRAM and a spare cell that is provided for repairing a defective bit. Although dummy cells and spare cells are omitted in the figure, they are added in units. FIGS. 3 (a) and 3 (b) show a case where the memory cell array is configured by the folded bit line system in correspondence with FIG.

The address conversion circuit 14 of FIG. 1 is provided because the memory cell unit to be read is different from the memory cell unit to which the read data is rewritten. That is, the address conversion circuit 14 converts the internal address between the memory cell unit in which the predetermined data is stored before the reading and writing and the memory cell unit in which the data read from this is written at the time of reading and writing, In addition, this is stored in the address register, and when the address is input from the outside, the converted internal address is output. The details will be described later.

Reading and writing in the DRAM of this embodiment are performed randomly in memory cell unit units. The operation will be described with reference to the timing chart of FIG. In the figure, t _SA shows the operation timing of the bit line sense amplifier, and t _EQ shows the equalizing operation timing.
Here, the (m + 1) th memory cell unit is empty first, and the i-th memory cell unit (word lines WL _io , WL _i1 , WL _i3 , WL _i4 ) is accessed. First, when the word line WL _i0 rises, the word lines WL _{(m + 1) 0} , WL _{(m + 1) 1} , WL _{(m + 1) 2} , WL of the (m + 1) th memory cell unit have already been written.
_{(m + 1) 3} are all up.

The word line WL _io rises, the data of the memory cell MC ₀ from the bit line in the i-th memory cell unit is read out to the bit line, and the bit line sense amplifier operates (m + 1). The word line WL _{(m + 1) 3} corresponding to the memory cell farthest from the bit line of the th empty memory cell unit falls. As a result, the first data of the i-th memory cell unit is stored in the innermost memory cell of the (m + 1) th memory cell unit.

Next, after the word line WL _i1 rises, the data of the second memory cell MC ₁ on the bit line side in the i-th memory cell unit is read to the bit line, and the bit line sense amplifier operates. , The word line WL _{(m + 1) 2} corresponding to the second memory cell from the back of the (m + 1) th empty memory cell unit falls. As a result, the second data in the i-th memory cell unit becomes (m +
The data is stored in the second memory cell from the back of the 1) th memory cell unit.

Similarly, the word lines WL _i2 and WL _i3 sequentially rise, and the word lines WL _{(m + 1) 1} and WL are delayed after this.
_{(m + 1) 0} sequentially falls, and the data read from the i-th memory cell unit is stored in the (m + 1) -th memory cell unit.

As described above, the data of the i-th memory cell unit is written to the (m + 1) th memory cell unit at the same time as the reading, and the i-th memory cell unit becomes empty. Next, when the third memory cell unit is accessed, four data that are sequentially read in the same manner are sequentially stored in the i-th memory cell unit that has been emptied by the previous read. And so on
The data of the memory cell unit read at each access is written to the memory cell unit which is empty at that time, and the operation of emptying the read memory cell unit is repeated.

The configuration and operation of the word line driving circuit portion for performing the word line driving as described with reference to FIG. 4 will be described in detail with reference to FIG. FIG. 5 shows word lines WL _i0 , WL _i1 , WL _i2 , WL corresponding to the i-th memory cell unit.
_The drive circuit part which drives _i3 is shown. Since the read address and the address for writing the read data as they are are different, there are two types of word line drive timing signals WL.
There is _{CKA0 ~WL CKA3} and WL _CKB0 ~WL _CKB3. Further, there are address latches A and B (details will be described later) corresponding to two types of address signals (decode signals), and two types of address signals and two types of word lines are provided by the NAND gate groups G ₁ , G ₂ and G _3. The word line drive signal is obtained by taking the logic of the drive timing signal.

FIG. 6 is an operation waveform diagram of FIG. The row address strobe signal / RAS is input to the timing signal CNT, the timing signal WL of the word line up and down as shown _{CKA0 ~WL CKA3} and WL _CKB0 to W-
_Try to create L _CKB3 .

FIGS. 7 to 9 _show a circuit for generating such word line drive timing signals WL _{CKA0 to} WL _CKA3 , WL _{CKB0 to} WL _CKB3 . As shown in FIG. 7, three JK flip-flops FF ₁ , FF ₂ , FF ₃ and an OR gate G _{11 are provided.}
Accordingly, to obtain a clock 1/2 frequency output Q ₀ of CK, 1/4 divided output Q _1, 1/8 frequency-divided output Q _2, using these output and the inverted output, EXOR gate G ₂₁ , G
_22. G ₂₃ and G ₂₄ provide two types of basic signals QA ₀ , QA ₁ and QB ₀ , QB ₁ for timing signals.

Then, as shown in FIG. 8, QA ₀ , QA
By ₁ a timing signal CNT and logic of these inverted signals sequentially rise, for generating a timing signal WL _CKA0 ~WL _CKA3 falling sequentially. In 9 Similarly, the logic of the QB _0, QB ₁ and timing signals CNT and their inverted signals sequentially rise, for generating a timing signal WL _CKB0 ~WL _CKB3 falling sequentially. FIG. 10 shows operation waveforms of this timing signal generation circuit.

As is clear from the above description, every time data is read and written, the read data of the memory cell unit is written to the memory cell unit at another position (address). Therefore, in order to read the data read at a certain external address to the next same external address, address conversion is necessary. This is done in Figure 1.
Address conversion circuit 12. The address conversion circuit 12 is provided in the DRAM chip in this embodiment, but may be provided outside the chip. The detailed configuration and operation will be described below.

FIG. 11 shows the configuration of the address conversion circuit. The address conversion circuit stores an internal address corresponding to each memory cell unit number 0, 1, ..., M + 1 along the bit line in an address register 112 (112).
₀ , 112 ₁ , ..., 112 _{m + 1} ), an address conversion decoder 111 for selecting them, and two types of latch circuits 113 _A , 113 for holding the converted addresses.
_It is composed mainly of _B. Address register 11
Although 2 is shown for each address number by 1 bit in the figure, actually, only the number of bits corresponding to the number of memory cell units along the 1 bit line (for example, 7 bits in the case of 128 memory cell units) is provided. .. Latch circuit 113
_The same applies to _A 113 _B.

The decode signal output from the conversion decoder 111 is the gates G _1A , G _1B , ..., G _{(m + 1) A} , G _{(m + 1) B} controlled by the latch circuit selection signals RWA and RWB. is selected by, thereby the data between the address register 112 and latch circuit 113 _a or 113 _B transfers are controlled.

Further, the address conversion circuit of this embodiment includes
Corresponding to each address register 112, an identification register 114 (114 ₀ , 114) for identifying the reverse of the data.
₁ , ..., 114 _{(m + 1)} are provided. This is because, as described above, every time the memory cell unit is accessed, the arrangement order of the data in the memory cell unit is reversed, and this must be recognized. The identification register 114 has only one bit in which "0" and "1" are alternately stored every access. Inversion circuit 115
_A and 115 _B are provided for data control of the identification register 114 and output of an identification signal.

FIG. 12 is a block diagram of the address conversion circuit of FIG.
(a) identification register 114, (b) address register 11
2, (c) Inversion circuit 115 and (d) Latch circuit 113. The (a) identification register and (b) address register are well-known ones composed of CMOS flip-flops and transfer gates. Further, when the SET signal becomes "H" to determine the initial address, the address register Each has a terminal to which a predetermined address is set.
(c) The inverting circuit is mainly composed of the latch circuit LA, a transistor for resetting it by the write signal WRITE, a transfer gate for transferring the data of the identification register 114 to the latch circuit LA, and the data of the latch circuit LA for the identification register 114. Clocked CMO for transfer
It is composed of an S inverter. (d) The latch circuit is also composed mainly of CMOS flip-flops.

FIG. 13 shows an example of the configuration of the control signal generation circuit of each part of FIG. A read address control signal ADREAD and a write address control signal ADWRITE synchronized with the / RAS clock are obtained, and various control signals are generated by using this and an output obtained by dividing / RAS clock by 1/2.

The operation of the address conversion circuit thus constructed will be described below. 14 to 17 show how the contents of the address register 112 are converted each time access is made. FIG. 18 shows operation waveforms. The state of address conversion according to the operation described above with reference to FIG. 4 will be described with reference to FIGS.

First, each address register 112 stores the internal address of the memory cell unit in a 1: 1 correspondence. This may be achieved by providing each address register 112 with a set terminal so that the address register 112 can be initialized. Assuming that the initial state is the state shown in FIG. 14, when it is desired to access the data Di from the outside, the i-th address register 112 _i is accessed. Then, the content (i) of the address register 112 _i is decoded and the memory cell unit corresponding to this is selected.

At this time, the data Di of the selected memory cell unit is stored in the (m + 1) th empty memory cell unit as described above. (M + of this read data
1) Corresponding to the writing to the memory cell unit, the contents of the i-th address register 112 _i and (m +
1) The contents of the _1st address register 112 _{(m + 1)} are exchanged. This is shown in FIG.

The next time that externally accessing data D3 is the third address register 112 ₃ in the same manner is accessed. Then, the content (3) is decoded to select the memory cell unit. As in the previous case, the data D3 read from the memory cell unit at this time
Is written in the empty memory cell unit at this time, that is, in the i-th memory cell unit which has been emptied by the previous reading. In response to this read / write, the contents (3) of the address register 112 ₃ and the address (i) of the empty memory cell unit are exchanged. FIG. 16 shows this state.

Next, when the data Di is accessed from the outside again, the i-th address register 112 _i is accessed. Then, the contents (m + 1) are decoded and the (m + 1) th memory cell unit is selected. At this time, since the data Di of the memory cell units are stored in the third empty memory cell unit, the address register 112 (m _{+ 1)} Contents (m + 1) and an empty memory cell unit of the address (3) And are exchanged. FIG. 17 shows this state.

FIG. 18 shows operation waveforms of the circuit of FIG. 11 which performs the above address conversion. As an initial state, one of the two latch circuits 113 _A, 113 _B, the internal address of an empty memory cell unit to a latch circuit 113 _A (m
+1) is latched. From this state, first data D
When accessing i, the address conversion decoder 11
1 decode signal and latch circuit selection signal R
By WB, G of i-th select gates G _iA and G _iB
The output of _iB goes to "H" level and the address register 11
2 _i is selected and its internal address (i) is latched in the latch circuit 113 _B.

The address data latched by the latch circuit 113 _B is sent to the row decoder, and the selected memory cell unit is read / written. At this time, as described above, the data of the i-th memory cell unit is read and the same data is written as it is to the (m + 1) -th memory cell unit.

Then, the latch circuit selection signal RWB is deactivated ("L" level), and the latch circuit line selection signal RWA is activated ("H" level) instead. This allows
Initially set have the address in the latch circuit 113 _A (m
+1) is written to the address register 112 _i . Address (i) corresponding to an empty memory cell unit
Is latched in the latch circuit 113 _B at this time.

Next, when the data D3 is accessed, the address register 112 is supplied by the decode signal from the address conversion decoder 111 and the latch circuit selection signal RWA.
₃ is selected and its internal address (3) is latch circuit 1
Latched to 13 _A. The address data of the latch circuit 113 _A is sent to the row decoder to access the memory cell unit. Then, next, the latch circuit selection signal RWA is deactivated, the latch circuit selection signal RWB is activated, and the address (i) latched by the latch circuit 113 _B is written in the address register 112 ₃ . The space-time since the address corresponding to the memory cell units (3) is latched in the latch circuit 112 _A.

Similarly, the data read at each access is written in the empty memory cell unit at that time, and the internal address is automatically converted in response to this.

Next, in the memory cell array structure of this embodiment, as described above, the data array written in the empty memory cell unit at each access is reversed from that of the read memory cell unit. Therefore, it is necessary to determine the read data in the reverse order. To do this, FIG.
As shown in FIG. 1, the identification register 114 and the inverting circuit 1 provided by adding 1 bit to each address register 112.
There are 15. The identification register 114 is selected at the same time as the corresponding address register 112, and every time writing is performed to an empty memory cell unit, the contents of the identification register of the address corresponding to the memory cell unit are inverted by the inverting circuit 115 _A or 115 _B. Is reversed by.

If the identification register is provided in this way, by checking the content thereof, it is possible to determine whether the read data of the selected memory cell unit is the reverse of the original data array order.

FIG. 19 shows a memory cell array structure according to another embodiment of the present invention. Unlike the configuration of the previous embodiment shown in FIG. 2, in this embodiment, the storage nodes at both ends of four memory cells connected in series are both connected to a bit line via a transistor. Therefore, unlike the previous embodiment, in this embodiment there are five word lines per memory cell unit. 19 shows a memory cell array corresponding to the open bit line system shown in FIG. 2 of the previous embodiment.
A folded bit line type layout corresponding to (a) and (b) is also possible.

FIG. 20 shows operation waveforms in such a memory cell array configuration. A case where access is performed in the same memory cell unit access order as that described with reference to FIG. 4 of the previous embodiment is shown in association with FIG. When the (m + 1) th memory cell unit is empty first, it starts from the point where the ith memory cell unit is accessed. When the i-th first word line WL _i0 rises, the word lines WL _{(m + 1) 0 to} WL _{(m + 1) 4} of the empty memory cell unit (m + 1) th memory cell unit become WL _(m All are up except for _{+1) 0} .

After the word line WL _i0 rises and the sense amplifier operates, the word line W of the empty memory cell unit
L _{(m + 1) 1} falls, and the first data of the i-th memory cell unit is the first memory cell of the (m + 1) -th memory cell unit (that is, the first memory cell viewed from the bit line contact used for reading). Stored in. Hereinafter, the word lines WL _i1 , WL _i2 , WL _i3 , and WL _i4 are also word lines WL _{(m + 1) 2} , WL at the same timing.
_{(m + 1) 3} and WL _{(m + 1) 4} fall, and the data of the i-th memory cell unit is stored in the (m + 1) -th memory cell unit.

As described above, in this embodiment, the two bit line contacts of the memory cell unit are selectively used for reading and writing data. That is, reading is sequentially performed from the memory cell closer to the right via the bit line contact on the right side of the memory cell unit, and writing is performed via the bit line contact on the side opposite to that at the time of reading, also on the right side of the memory cell unit. The memory cells are sequentially processed. That is, the order of reading data and the order of writing data are the same in the memory cell unit, in other words, the data array in the memory cell unit is the same as the state before reading and the state in which reading and writing are performed.

When the third memory cell unit is accessed next time, since the empty memory cell unit is the i-th memory cell unit, the data read from the third memory cell unit is the i-th memory cell unit. It is written in the memory cell unit.

FIG. 21 shows the word line drive circuit in this embodiment in correspondence with FIG. 5 of the previous embodiment. In this example, 1 since the memory cell unit per word line is five, WL _CKA0 ~WL _CKA4 also the control signal lines, WL
_{Five CKB0 to} WL _CKB4 are provided. 22 is the same as FIG.
1 is an operation waveform. / From RAS is input, the timing signal of raising or lowering the word line _{WL CKA0 ~WL CKA4, WL CKB0 ~WL} CKB4 is made by the timing signal CNT.

[0047] FIGS. 23 and 24 are timing signals as shown in FIG. _{22 WL CKA0 ~WL CKA4, WL CKB0} ~WL CKB4
It shows a circuit for generating. Figure 23 (a) (b) is a Johnson counter and the master slave flip-flop used therein, FIG. 24, the timing signal WL _CKA0 ~WL _CKA4 from a signal obtained from the counter of FIG. 23,
_This is a logic gate for obtaining WL _{CKB0 to} WL _CKB4 . A similar timing signal can be generated by using a shift register instead of the Johnson counter.

The address conversion circuit shown in FIG. 11 of the previous embodiment is used.
Basically the same configuration can be used. However, the identification register 114 and the inverting circuit 115 for determining the order of the data array are unnecessary.

In the previous embodiment, since there was only one contact with the bit line in the memory cell unit, reading and writing had to be performed through the same contact, so that the order of data to be read was access. It was reversed every time. In this embodiment, since the bit line contacts are located on both sides of the memory cell unit, by reading from one bit line contact and writing from the opposite bit line contact, the order of data to be read is It does not reverse every time it is accessed. Therefore, in this embodiment, a register for recognizing the reverse order of the data array is unnecessary. The address conversion circuit of FIG. 11 has an address register 112 that holds the converted internal address. As the address register 112, a CMOS flip-flop as shown in FIG. 12B is specifically used. A DRAM cell can also be used for this address register portion. Such an embodiment will be described below.

FIG. 25 shows the structure of the address register of such an embodiment. As shown in the figure, the address register is composed of a DRAM cell composed of two transistors and a capacitor connected in parallel. Latch circuit 113
_A, 113 _B is generally similar configuration as the bit line sense amplifier of DRAM, the buffer circuit 12 at its output
0 _A and 120 _B are provided. By replacing the address register 112 and the latch circuits 113 _A and 113 _B in FIG. 11 with this circuit, an address conversion circuit similar to that in FIG. 11 can be obtained.

Although not shown in the drawing, a write circuit for initial setting is provided at the storage node of the DRAM cell forming each address register 112. The gates of the two transistors of the DRAM cell of the address register section are selectively on / off controlled by the logic of the decode signal obtained from the address conversion decoder of FIG. 11 and the selection signals RWA, RWB, and the latch circuit 113 _A or 113. Data will be transferred to and from _B.

The circuit operation waveform in this case is shown in FIG. 26 corresponding to FIG. 18 of the previous embodiment. Similarly to the previous embodiment, when the address of the data Di is input, the corresponding internal address data is transferred from the address register 112 _i to the one latch circuit 113 _B and latched, and then via the buffer circuit 120 _B. It is sent to the row decoder. Then, the data corresponding to the empty address (m + 1) previously latched in the other latch circuit 113 _A is
It is written into the address register 112 _{i which} has been destructively read. Then, when another address of the data D3 is entered, the corresponding internal address data is transferred from the address register 112 ₃ to the latch circuit 120 _A and sent to the row decoder, and at this time, the address register 112 ₃ which has been destructively read.
The data held in the latch circuit 120 _B is written in. After that, address conversion is performed in the same manner as in the previous embodiment.

FIG. 27 is a modification of FIG. Figure 25
In contrast, two cell transistors of a DRAM cell forming an address register are connected to the same data line, whereas in this embodiment, two cell transistors are connected to different data lines forming a pair. There is. That is,
In FIG. 25, reading and writing of address data are performed through the same data line, whereas in FIG. 27, this is performed through separate data lines.

FIG. 28 shows operation waveforms in the case of the address register configuration of FIG. 27 in correspondence with FIG. Although detailed description is omitted, the basic operation of address conversion is the same.

As shown in FIG. 25 or FIG. 27, the address register can be composed of DRAM cells. Similarly, the identification register 113 for discriminating the order of data in the address conversion circuit of FIG. 11 is also DR.
It can be composed of AM cells. The present invention is not limited to the above embodiments, and various modifications can be carried out without departing from the spirit of the present invention.

[0056]

As described above, according to the present invention, NA
In the ND type DRAM, at least one memory cell unit which is always empty is provided in each bit line in the memory cell array, and when the data of the memory cell unit is read in time series, the empty memory cell unit is read out at the same time as the reading. By writing to, effectively NANA type DRA
The power consumption of M and the cycle time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory cell array of the same embodiment as FIG.

FIG. 3 is a diagram showing a configuration example of another memory cell array.

FIG. 4 is a timing diagram illustrating a read / write operation of the embodiment.

FIG. 5 is a diagram showing a configuration of a word line drive circuit unit of the same embodiment.

FIG. 6 is a waveform diagram of a word line drive timing signal of the same embodiment.

FIG. 7 is a diagram showing a basic signal generation circuit of a word line drive timing signal of the same embodiment.

FIG. 8 is a diagram showing a word line drive timing signal generation circuit of the same embodiment.

FIG. 9 is a diagram showing a word line drive timing signal generation circuit of the same embodiment.

FIG. 10 is an operation waveform diagram of FIGS. 7 to 9;

FIG. 11 is a diagram showing an address conversion circuit of the same embodiment.

12 is a diagram showing a circuit configuration of each part of FIG.

13 is a diagram showing the control signal generation circuit of FIG.

FIG. 14 is a diagram showing how address translation is performed in the embodiment.

FIG. 15 is a diagram showing how address translation is performed in the embodiment.

FIG. 16 is a diagram showing how address translation is performed in the embodiment.

FIG. 17 is a diagram showing how address translation is performed in the embodiment.

FIG. 18 is a diagram showing operation signal waveforms in FIG. 11.

FIG. 19 is a diagram showing a memory cell array configuration of another embodiment.

FIG. 20 is a view for explaining a read / write operation of the same embodiment.

FIG. 21 is a diagram showing a configuration of a word line drive circuit unit in the same example.

FIG. 22 is a waveform diagram of a word line drive timing signal in the same example.

FIG. 23 is a diagram showing a word line drive timing signal generation circuit of the embodiment.

FIG. 24 is a diagram showing a word line drive timing signal generation circuit of the embodiment.

FIG. 25 is a diagram showing an address register configuration in an address conversion circuit of another embodiment.

FIG. 26 is a view showing operation waveforms in the same example.

FIG. 27 is a diagram showing an address register configuration in an address conversion circuit of another embodiment.

FIG. 28 is a view showing operation waveforms in the same example.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Row decoder, 13 ... Column decoder, 14 ... Address conversion circuit, 15 ... Input / output buffer, MU ... Memory cell unit, BL ₀ , BL ₁ ... Bit line, 21 ₀ , 21 ₁ ... Bit line Sense amplifier, WL _i0 , WL _i1 , WL _i2 , WL _i3 ... Word line, 111 ... Address conversion decoder, 112 _{0 to} 112 _{m + 1} ... Address register, 113 _A , 113 _B ... Latch circuit, 114 _{0 to} 114 _{m +1} ... identification register, 115 _A, 115 _B ... inversion circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoharu Tanaka 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Research Institute

Claims (4)

[Claims] 1. A memory cell unit in which a plurality of 1-transistor / 1-capacitor memory cells are connected in series is arranged in a matrix, and each bit line has a dummy data cell and a spare cell in addition to a memory cell unit having a predetermined data storage capacity. A memory cell array to which different empty memory cell units are connected, and the data read to a bit line from a certain memory cell unit during read / write is amplified by a bit line sense amplifier and connected to that bit line. A means for writing to the cell unit, and at the time of reading / writing, converting an address between a memory cell unit in which predetermined data is stored before reading / writing and a memory cell unit in which data read from this is written, and Store this in the address register and Dynamic semiconductor memory device characterized by comprising a, and address conversion means for outputting the converted internal address to the input time. 2. The dynamic semiconductor memory device according to claim 1, wherein reading and writing are performed randomly in units of memory cell units. 3. A memory cell unit, wherein a plurality of memory cells connected in series have a storage node on one end side connected to a bit line through a transistor, and the memory cell unit is read from and written to the address register of the address conversion means each time. 2. The dynamic semiconductor memory device according to claim 1, further comprising an identification register for identifying the reverse of the data array to be inverted. 4. A memory cell unit, wherein storage nodes at both ends of a plurality of memory cells connected in series are connected to a bit line through a transistor, respectively, and data reading and writing are performed through different bit line contacts. hand,
2. The dynamic semiconductor memory device according to claim 1, wherein the data array in the memory cell unit is the same as that before reading and after writing.