JPH07192031A - Method and device for automatic layout for integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an automatic layout method and device revising the logic circuit information to secure hold time of a flip-flop so that the revision of the logic circuit information designed at first is not seen in an integrated circuit laid out by an automatic layout device. CONSTITUTION:After an integrated circuit based on a command is laid out, hold time of flip-flop circuits 18, 19 in the layout integrated circuit is calculated to decide whether or not hold margin is deficient. The flip-flop 19 whose hold margin is deficient is replaced with a flip-flop 20 prepared in advance and having the same size and the same input output terminal position and with a delay element whose delay differs. Thus, the revision to satisfy the hold time of the flip-flop is executed without revision of the logic circuit information and the layout pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout method and apparatus for an integrated circuit, and more particularly to a layout method capable of suppressing a hold time in a signal propagation path between flip-flops in the integrated circuit to a desired value. And equipment.

[0002]

2. Description of the Related Art In an integrated circuit controlled by a clock signal, a flip-flop (hereinafter referred to as F / F) of the integrated circuit is used.
When designing a circuit that limits the relationship between the propagation time of the data signal and the clock signal input to
A layout design that protects the hold margin against the hold time of is required.

The propagation path time of a signal is the sum of the delay time due to the elements included in the propagation path and the delay time due to the wiring between the elements, but the former has a unique value for each element. On the other hand, the latter depends on the wiring of the layout pattern. Therefore, in the layout design of the integrated circuit that needs to keep the hold margin, it is necessary to determine the wiring pattern of the data signal line in consideration of variations in delay time. In the layout design of the semiconductor integrated circuit that needs to satisfy the hold margin,
The conventional technique uses the following method.

One method is to manually modify the logic circuit in advance at the stage of logic design. FIG. 9 shows a part of a circuit diagram in a logic design stage by a conventional automatic layout apparatus. Clock signal 5 is for each F / F
6, 7 and 8 are supplied to the F / F 6 and the data signal between the F / F 7 and the F / F.
A data signal between the F and F / F 7 is supplied via the data signal wiring group 10. At this time, the data signal wiring 9
Since no element is connected, it can be seen that the propagation time of the data signal is short, and the designer inserts the delay element group 29 into the data signal wiring 9 as shown in FIG.
The circuit was designed to satisfy the hold margin.

Another method is a method of automatically inserting a delay element in accordance with connection information to perform layout, and adjusting a delay time of the inserted delay element (for example, Japanese Patent Laid-Open No. 3-84595). ). 11 and 12 are diagrams showing an example thereof. In FIG. 11, a delay element 30 is inserted between each F / F in FIG. 9 to change the logic circuit diagram. A layout pattern is generated using this logic circuit diagram.

The delay element is shown in FIGS. 12 (a) to 12 (f).
Prepare a cell as shown in. Prepared Figure 12 (a)
The cells indicated by (f) to (f) are elements having a constant delay time (in this case, the OR circuit 33) arranged in series, and have a size, an input terminal position 31 and an output terminal position 32.
Are equal. 12 (a) to 12 (f), the data transmission delay time of the data signal between F / F and the signal propagation delay time of the clock signal propagation path are calculated from the generated layout pattern, and the delay values satisfy the hold margin are shown in FIGS. It is possible to design to satisfy the hold margin without changing the layout pattern by selecting from the shown ones and replacing the original cell.

[0007]

Among the conventional methods, in the method of manually correcting the logic circuit diagram in advance at the logic design stage, since it is not the information after the layout, the influence of the layout wiring result is taken into consideration. It is necessary to insert more delay elements than the expected number of delay elements (delay time). For this reason, there are drawbacks that the design load in the circuit design stage becomes heavy and the number of extra elements and nets in the entire circuit increases.

In the method of changing the other delay element cell, since the delay element not used by the user in the design is inserted as the logic circuit information, the logic circuit information (circuit connection information) designed by the user and This is different from the logic circuit information used in the layout. Therefore, similar to the method of manually modifying the logic circuit diagram, there is a drawback in that the number of cell elements and the number of nets increase with respect to the user's design due to logic circuit information.

Further, these methods have a drawback that the user cannot understand the contents of the completed circuit unless the contents of the change are fed back to the user.

In view of the above-mentioned drawbacks, it is an object of the present invention to provide an integrated circuit layout method and apparatus which satisfy the F / F hold margin and hardly change the logic circuit information.

[0011]

The automatic layout method of the present invention requires a plurality of signal propagation paths as elements, and the hold margin to be within a desired value regarding the signal propagation delay time in each signal propagation path. A method of automatically laying out an integrated circuit including at least one signal propagation path, the first step of preparing a plurality of flip-flops having different internal delays but having the same size and input / output terminal position in advance; The second step of automatically generating layout pattern information based on the inter-element connection information and the hold time in each flip-flop in the signal propagation path is calculated from the generated layout pattern information, and the hold margin is insufficient. And a third stage of extracting replacement target flip-flops, which are the respective flip-flops, For the replacement target flip-flop in the generated layout pattern information, the replacement is a flip-flop that has a delay time equivalent to the sum of the hold margin shortage time extracted in the previous step and the internal delay of each replacement target flip-flop. The method has a fourth step of selecting a flip-flop and a fifth step of changing the selected replacement flip-flop and replacement target flip-flop based on the layout pattern generated in the previous step.

Further, the automatic layout apparatus of the present invention stores various circuit elements including at least wirings and flip-flops in the circuit element storage section as respective circuit patterns, and uses the stored circuit elements to synchronize with the clock signal. An automatic layout apparatus capable of automatically laying out an integrated circuit for transmitting a signal according to an instruction, wherein an outer edge shape including a connection terminal is the same as that of the flip-flop, and delay elements having different delay times are added. A flip-flop pattern storage unit with delay elements that stores a plurality of flip-flops with delay elements as circuit patterns, and an appropriate circuit element is selected from the circuit element storage unit according to the instruction, and the selected circuit element is used. A first layout section for laying out a desired integrated circuit and a first layout section. Part calculates the hold time of the flip-flops in the integrated circuit layout, it is determined whether hold margin is insufficient,
A hold margin determination unit that extracts a flip-flop whose hold margin is insufficient as a replacement target flip-flop and a replacement target flip-flop extracted by the hold margin determination unit are delayed by a delay corresponding to the hold margin shortage time of the replacement target flip-flop. And a second layout section which is replaced by a flip-flop with a delay element to which a delay element having time is added.

[0013]

According to the present invention, after laying out the integrated circuit based on the instruction, the hold time of each flip-flop in the laid out integrated circuit is calculated, and it is determined whether or not the hold margin is insufficient. The flip-flops having insufficient hold margins are changed to flip-flops with delay elements having the same size and the same input / output terminal position and different delay values prepared in advance. As a result, the change for satisfying the hold time of the flip-flop can be performed without changing the logic circuit information and the layout pattern.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a flow chart showing the main part of the automatic layout method of the present invention. FIG. 2 is a circuit diagram showing an integrated circuit instructed to be laid out (however, for simplification of description, only a flip-flop related to a propagation path portion of a clock signal and a data signal propagation path portion between the flip-flops are shown. Shown). 3 is a diagram showing a pattern of an integrated circuit laid out by the automatic layout apparatus of the present invention by a conventional method according to the circuit diagram of FIG. 2, and FIG. 4 is a diagram of the integrated circuit shown in FIG. 3 by the automatic layout apparatus of the present invention. FIG. 5 is a pattern diagram showing a result of calculating a hold time in each flip-flop and replacing a flip-flop having a short hold margin with a flip-flop with a delay element. FIG. 5 is a delay element prepared in advance for the replacement in FIG. FIG. 9 is a pattern diagram showing an example of a flip-flop with a switch.

As is apparent from FIG. 2, the clock signal supplied to the clock signal line 5 is the clock input to each flip-flop 6, 7, 8 (hereinafter referred to as F / F 6, 7, 8). Supplied to the terminal. The propagation of the data signal given from the data input line 4 to the input terminal of the F / F 6 is supplied to the data input terminal of the F / F 7 by the data signal wiring 9, and further the data input of the F / F 8 is input by the data signal wiring group 10. Supplied to the terminal. The propagation delay time of the data signal and the clock signal supplied to each F / F is represented by the sum of the delay time of each element of the signal path and the propagation delay time of the wiring path. Is constant, the transmission delay time of the wiring paths 5, 9 and 10 varies depending on the state of the wiring pattern of the layout.

An automatic layout method for such a circuit will be described with reference to FIG. When an instruction to produce a pattern of an integrated circuit as shown in FIG. 2 is given, the automatic layout and wiring program of the automatic layout apparatus performs the generation of the entire layout pattern as shown in FIG. S1). After the layout pattern is generated, the signal propagation delay time from the clock signal line 5 to each F / F is calculated and the data signal wirings 9 and 10 are calculated.
To F / F7, 8 are calculated, and whether or not the hold margin of F / F7, 8 is insufficient is extracted from the layout pattern (step S).
2).

Next, F where the hold margin is insufficient
/ F (for example, F / F 19 in FIG. 3), the F / F pattern with the shortest delay time within the range exceeding the shortage delay time is selected from FIGS. 5B to 5E (steps). S3). In order to satisfy the hold margin of the F / F 19, for example, the F / F of FIG. 5B is selected, and the selected F / F is selected.
F is replaced with F / F20 and F / F19 is replaced on the layout information (step S4). At this time, the layout wiring pattern 17 and the F / F 18 that is not the replacement target (F / F that satisfies the hold margin) are not subjected to relayout or replacement processing. Through the above processing, the hold margin can be satisfied without changing or relaying out the logic circuit information.

In the cellular F / F as shown in FIGS. 5A to 5E, an element having a constant delay time (buffer circuit 16 in this case) is connected in series in front of the F / F element 12. They are arranged side by side, cell size, input / output terminal position 1
The positions of 1, 13, 14, and 15 are made equal. However, the F / Fs shown in FIGS. 2 to 4 are regarded as only one type on the logic circuit diagram. The layout pattern of the F / F in the first automatic placement and routing is shown in FIG.
The one shown in (a) is used.

As the F / F with delay, as in the present embodiment, an element (buffer) having a constant delay time is used.
Even if the r circuit 16) is not arranged in series, the size of the F / F and the input / output terminal position may be the same.
As shown in FIG. 5, an element having different characteristics that influence the signal transmission delay time such as the driving ability of the cell connected as the delay element 21 may be used.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 7, it is assumed that the hold margins of all the F / Fs 23a, 23b, and 23c connected to the F / F 22 are insufficient. F / F 23a, 23b, 2 with insufficient hold margin
F / which has the shortest hold margin among 3c
The F / F with delay element having the delay element 28 shown in FIG. 8 on the output terminal side is selected based on the shortage delay time of F. As the selection method, the F / F having the smallest delay value in the range exceeding the hold margin is selected. F / F for replacement selected
Is replaced with the F / F 22, which is the sending side of the data signal propagation path. By laying out the above processing using the automatic layout apparatus, a highly integrated layout design satisfying the hold margin can be automatically realized.

[0021]

As described above, according to the present invention, the flip-flops for replacement in which the delay elements that bring the signal delays of various lengths into the signal propagation paths are incorporated are prepared and laid out in the automatic layout apparatus. If there is a hold margin shortage among the flip-flops in the integrated circuit, the function of extracting the flip-flop and replacing it with an appropriate replacement flip-flop is added to the conventional layout processing function. As a result, there is an effect that a layout satisfying the hold margin can be realized without manually or automatically changing the logic circuit information or performing a re-layout due to a shortage of the hold margin. Realization of layout design, automatic layout that does not cause mistakes due to changes in logic circuit information It has the effect that the current can be. Further, since the change of the circuit does not involve the change of the appearance, the designer before the change can easily understand the logic circuit information after the change.

[Brief description of drawings]

FIG. 1 is a flowchart showing a main part of an automatic layout method of the present invention.

FIG. 2 is a circuit diagram showing a part of a logic circuit of an integrated circuit to be created by the automatic layout device of the present invention.

FIG. 3 is a diagram showing a pattern of an integrated circuit laid out by a conventional method by the automatic layout apparatus of the present invention according to the circuit diagram of FIG.

FIG. 4 is a diagram showing an automatic layout apparatus of the present invention, which calculates a hold time at each F / F of the integrated circuit shown in FIG. It is a pattern diagram which shows the result of substitution.

5A and 5B are pattern diagrams showing an example of an F / F with a delay element prepared in advance for replacement.

FIG. 6 is a diagram showing another example of an F / F with a delay element.

FIG. 7 is a circuit diagram showing a second embodiment of the present invention.

8 is a pattern diagram showing an F / F with a delay element for replacement used in the embodiment of FIG.

FIG. 9 is a circuit diagram showing a part of a logic circuit of an integrated circuit to be created by a conventional automatic layout device.

10 is a circuit diagram showing a state where a delay element is added to the logic circuit of FIG. 9 by a conventional method.

FIG. 11 is a circuit diagram showing a delay element inserted in the logic circuit of FIG. 9 by a conventional method.

FIG. 12 is a pattern diagram showing an internal circuit of a conventional delay element.

[Explanation of symbols]

4 data input lines 5 clock signal lines 6, 7, 8, 18, 19, 22, 23a, 23b, 23
c F / F 9 data signal wiring 10 data signal wiring group 11, 24 input terminal 12 F / F element 13, 14, 25, 26 output terminal 15, 27 clock input terminal 16 delay element (Buffer circuit) 17 wiring 20 for replacement F / F

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[Procedure amendment]

[Submission date] June 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

5 (a) to ( e ) are pattern diagrams showing an example of an F / F with a delay element prepared in advance for replacement of the circuit of FIG.

Claims (3)

[Claims] 1. An integrated circuit comprising a plurality of signal propagation paths as elements and including at least one signal propagation path which requires a hold margin to be within a desired value with respect to a signal propagation delay time in each signal propagation path. In the automatic layout method, layout pattern information is automatically generated based on the first step of preparing a plurality of flip-flops having different internal delays but the same size and input / output terminal position, and the inter-element connection information of the integrated circuit. From the second stage of generation and the generated layout pattern information, the hold time at each flip-flop in the signal propagation path is calculated, and the flip-flops to be replaced, which are the flip-flops having insufficient hold margins, are calculated. Third stage of extraction and replacement pair in generated layout pattern information With respect to the flip-flops, a fourth stage of selecting a replacement flip-flop that is a flip-flop having a delay time corresponding to the sum of the hold margin shortage time extracted in the previous step and the internal delay of each replacement target flip-flop, and An automatic layout method comprising: a fifth step of changing the selected replacement flip-flop and the replacement target flip-flop based on the layout pattern generated in the previous step. 2. Various circuit elements including at least wirings and flip-flops are stored as respective circuit patterns in a circuit element storage section, and the stored circuit elements are used,
In an automatic layout device capable of automatically laying out an integrated circuit that transmits a signal in synchronization with a clock signal according to an instruction, a delay element having an outer edge shape including a connection terminal that is the same as the flip-flop and different delay times is provided. A flip-flop pattern storage unit with delay elements that stores each of a plurality of added flip-flops with delay elements as a circuit pattern and an appropriate circuit element from the circuit element storage unit according to the instruction, and select the selected circuit element. A first layout unit for laying out a desired integrated circuit using the flip-flop and a hold time of each of the flip-flops in the integrated circuit laid out by the first layout unit are calculated to determine whether or not a hold margin is insufficient. Replace flip-flops with insufficient hold margin Hold-margin determining unit for extracting as a target flip-flop, and a delay element having the replacement-target flip-flop extracted by the hold-margin determining unit with a delay element having a delay time corresponding to the hold-margin shortage time of the replacement-target flip-flop. An automatic layout device having a second layout section which is replaced by an attached flip-flop. 3. The automatic layout apparatus according to claim 2, wherein the delay element is a buffer circuit.