JPH0582725A - Delay-time control circuit, and automatic wiring layout - Google Patents

Abstract

PURPOSE:To provide a method of automatic layout for a signal delay control circuit, in which signal delay time can be adjusted without a change of cell arrangement after the completion of automatic wiring. CONSTITUTION:Capacitor cell arrays 41-44 are arranged in wiring channel regions 31-34 between cell arrays 21-25. Before automatic layout, nets N1 and N2 liable to be affected by signal delay are specified, and an allowable delay time between the specified nets is determined. When automatic layout is performed, capacitor selection cells X1 and X2 having switch elements are arranged. The specified nets N1 and N2 are connected with capacitor cells Y1 and Y2 through the selection cells. The on-off states of the switch elements are fixed to satisfy the allowable differential time delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal propagation delay time adjusting circuit used in a semiconductor integrated circuit such as a gate array system or a standard cell system, and an automatic placement and routing method.

[0002]

2. Description of the Related Art FIG. 7 shows a schematic structure of a gate array 10.

The gate array 10 includes a main body portion 11 and a bonding pad & I / O interface portion 1 around the main body portion 11.
It consists of 2. In the main body portion 11, basic cell rows 21 to 25 are arranged at equal intervals, and wiring channel regions 31 to 34 are secured between them.

A chip is designed by automatic placement and wiring using CAD. For example, the basic cell A of the basic cell row 22 and the basic cell B of the basic cell row 24 are connected by a net N1.
The basic cell A and the basic cell C of the basic cell row 21 are net N
It is assumed that they are connected by 2. These basic cells A to C are
It is a component of a functional cell. Basic cell A to basic cell B
And when the same signal is sent to the basic cell C at the same time, a difference in signal propagation delay time occurs according to the difference in wiring capacitance between the net N1 and the net N2, usually the difference between the length of the net N1 and the length of the net N2. .. When the clock frequency is increased, this difference causes a malfunction. Such a problem becomes more serious as the circuit becomes larger.

[0005]

Since automatic placement and routing is performed with the goal of achieving a wiring rate of 100%,
The above problem has not been solved, and as a result, the speeding up of the clock frequency has been hindered. In such a case, the basic cell A,
It is also possible to make the lengths of the net N1 and the net N2 substantially the same by changing the arrangement of B or C. However, since the cell rearrangement affects the arrangement of other cells, it is complicated to perform the manual placement and routing after the automatic placement and routing, and the wiring rate of 100% may not be achieved. Such a problem also occurs in the standard cell system.

In view of such problems, an object of the present invention is to perform cell placement rearrangement after automatic placement and routing.
It is an object of the present invention to provide a signal propagation delay time adjusting circuit and an automatic placement and routing method capable of adjusting the signal propagation delay time.

[0007]

The signal propagation delay time adjusting circuit according to the present invention will be described with reference to the reference numerals of the corresponding constituent elements in the drawings.

This signal propagation delay time adjusting circuit is, for example, as shown in FIGS. 2 to 4, capacitive elements C1 to C4 (capacitive cell rows 31 to 34) arranged in a wiring channel region, an input terminal and a plurality of output terminals. And capacitance selection cells X1 and X2 having switch elements T1 to T4 for selectively turning on and off the capacitance selection cells X1 and X2, and the wiring between the cells A to C other than the capacitance selection cells X1 and X2 is capacitance selection. The capacitance selection cells X1 and X2 are connected to the input ends of the cells X1 and X2, and the output ends of the capacitance selection cells X1 and X2 are capacitive elements C1 to C1.
The switch elements T1 to T4 are connected to C4, and ON / OFF of the switch elements T1 to T4 are fixed in accordance with the length of the inter-cell wiring to adjust the inter-cell signal propagation delay time.

In the present invention, the wiring channel regions 31 to 31 are formed.
Since the capacitor cell columns 41 to 44 are arranged in No. 4, the wiring channel region is not particularly limited. Also, since it is possible to make a connection for wiring capacity adjustment during automatic wiring, without rearranging cells after automatic placement and wiring,
It is possible to adjust the signal propagation delay time.

In the first embodiment of the present invention, the cell is composed of a basic cell on the gate array, and the capacitors C1 to C4 are formed on the semiconductor substrate 50 via the insulating film 55 and the electrodes 51 to 51 as shown in FIG. This is a configuration in which 54 is arranged. The semiconductor substrate 50 is, for example, an n-type, p-type, or one in which an impurity layer is formed.

Next, the automatic placement and routing method according to the present invention will be described.
It demonstrates based on FIG. 1 with reference to FIGS.

In this automatic placement and routing method, for example, as shown in FIG. 2, the wiring channel region 3 between the cell rows 21 to 25 is formed.
Capacitance elements (capacitance cell rows 31 to 34) are arranged in 1 to 34, and automatic wiring is performed after automatic arrangement as follows. Hereinafter, the numerical value in parentheses is the step identification number in the figure.

(1) Before automatic wiring, nets in which signal propagation delay time is a problem, for example, nets N1 and N2 shown in FIG.
And the allowable signal propagation delay time difference between the designated nets N1 and N2 is substantially set. Substantially means that instead of the allowable signal propagation delay time difference, an allowable wiring capacitance difference or an allowable wiring length difference may be set.

(2) Capacitors provided with switch elements T1 to T4 for selectively turning on and off between an input end and a plurality of output ends as shown in FIGS. 3 and 4 during automatic placement. The selected cell X1 is arranged as a kind of cell.

(3) When the automatic wiring is performed, the designated net N1,
N2 is connected to the input terminals of the capacitance selection cells X1 and X2, and the output terminals of the capacitance selection cells X1 and X2 are connected to the capacitance elements, for example, the capacitance elements of the capacitance cells Y1 and Y2, and the set allowable signal propagation delay time difference is set. To satisfy the switch elements T1 to T
Fix on / off of 4.

According to the method of the present invention, since the connection for adjusting the wiring capacity is made to the net which is a problem in the automatic wiring,
The signal propagation delay time can be adjusted without rearranging the cells after automatic placement and routing.

In the first aspect of the present invention, in the above (1), nets N1 and N2 are designated before automatic placement,
In the above (2), when the automatic placement is performed, the designated net N
1, the capacity selection cell X1, near the cell connected to N2,
Place X2.

In the case of this structure, it is possible to shorten the wiring connecting the designated net and the capacitance selection cell.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 2 shows a schematic structure of the gate array 10A. The same components as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

After the automatic placement by CAD, the basic cells A, B and C constituting the functional cell have the same placement as in FIG. In this state, if automatic wiring is performed by CAD as in the conventional case, the net N connecting the basic cell A and the basic cell B is connected.
The difference between the wiring capacity of 1 and the wiring capacity of the net N2 connecting the basic cell A and the basic cell C, that is, the difference between the two wiring lengths poses a problem as in the case of FIG.

In order to solve this problem, in this embodiment, in the wiring channel regions 31 to 34 between the basic cell columns 21 to 25 of the main body 11A, the capacitor cell columns 41 to 41 are respectively provided.
44 are formed. Then, by automatic wiring, the net N1 is connected to the input terminal of the capacity selection cell X1, the capacity cell Y1 is connected to the output terminal of the capacity selection cell X1, and the net N2 is connected to the input terminal of the capacity selection cell X2. Selected cell X2
The capacitance cell Y2 is connected to the output terminal of the. The remaining basic cells near the basic cell B are used as the capacity selection cell X1,
A remaining basic cell near the basic cell C is used as the capacity selection cell X2. In addition, the capacity cell Y1 has a capacity cell row 41.
Among the capacitance cell columns 41 to 44, those of the capacitance cell columns 41 to 44 that are close to the capacitance selection cell X2 are used.

As shown in FIGS. 3 and 4, the capacitance selection cell X
1 includes nMOS transistors T1 to T4,
The drains of the S transistors T1 to T4 are commonly connected to form an input terminal, and the nMOS transistors T1 to T4 are connected.
Each source of 4 is an output terminal. The capacity cell Y1 is
It is composed of capacitive elements C1 to C4, one end of each of which is nM.
It is connected to the sources of the OS transistors T1 to T4 and the other end is grounded. Therefore, the gates G1 to G4 of the nMOS transistors T1 to T4 are connected to the power supply line V, respectively.
By connecting either _CC or ground line V _SS ,
The wiring capacitance of the net N1 can be adjusted.

In FIGS. 2 and 3, the gates G1 and G3 are connected to the ground line V _SS , the gates G2 and G4 are connected to the power supply line V _CC, and the additional capacitance of the net N1 is approximately C3.
It is + C4.

Although the width of the capacitance cell Y1 in the column direction is not limited, in the present embodiment, it is the same as the width of the basic cell in the column direction. As shown in FIG. 4, the capacitive cell Y1 includes capacitive elements C1 to C1.
Since the sizes of C4 are different from each other, it is possible to finely select the capacity to be added to the net N1. For example,
When the capacity ratio is C1: C2: C3: C4 = 1: 2: 4: 8, 15 additional capacities with a constant difference can be selected. As shown in FIG. 5, the capacitance cell Y1 is formed on the semiconductor substrate 5
On the surface portion 0, electrodes 51 to 54 of different sizes are arranged via an insulating film, for example, a field oxide film 55.

The capacity selection cell X2 and the capacity cell Y2 are similar to the capacity selection cell X1 and the capacity cell Y1.

Therefore, by appropriately selecting the capacity to be added to each of the nets N1 and N2, the net N1
And the difference in signal propagation delay time between the net N2 and the net N2 can be adjusted according to the purpose.

This adjustment is performed during automatic wiring. That is, specify the problematic net before automatic placement, and
Set the allowable signal propagation delay time difference between nets, allowable wiring capacitance difference or allowable wiring length difference, and after normal automatic placement,
The remaining basic cells are used as capacity selection cells, and after normal automatic wiring is completed or in parallel with this, the above-mentioned wiring is performed for the specified net so as to satisfy the set allowable signal propagation delay time difference. Automatically design the connection for capacity adjustment.

According to this embodiment, the wiring channel region 3
Since the capacity cell columns 41 to 44 are arranged in 1 to 34,
The wiring area is not particularly limited. Further, automatic wiring is performed for the purpose of achieving a wiring rate of 100%, and the connection for adjusting the wiring capacity is performed during automatic wiring without rearranging cells, so that the achievement rate of the wiring rate of 100% is high. Moreover, there is no need to perform complicated manual placement and routing after automatic placement and routing.

It should be noted that the capacity selecting cells X1 and X2 are secured in advance near the basic cell to which the above-mentioned designated net is connected during the automatic arrangement, instead of using the remaining basic cells after the automatic arrangement, or It is also possible to use the one secured in a predetermined portion irrespective of this designated net.

(2) Second Embodiment In the first embodiment, the nMOS transistors T1 to T1 are connected.
The capacitance between the drain and gate of T4 is the capacitance elements C1 to C4.
NMOS transistors T1 to T
Since the drains of the nMOS transistors 4 are commonly connected, the capacitance thereof cannot be ignored depending on the size and the number of the nMOS transistors T1 to T4. Therefore, in the second embodiment,
As shown in FIG. 6A, a capacitance selection cell X1A is used instead of the capacitance selection cell X1 shown in FIG.

That is, the nMOS transistors T1 to T
The source of the nMOS transistor T0 is connected to the drain of No. 4 to reduce the capacitance of the capacitance selection cell X1A itself.

In addition, the selection control signals S1 and S2 are shown in FIG.
It is supplied to the gates G0 to G4 of the nMOS transistors T0 to T4 via the decoder 70 as shown in FIG. The decoder 70 includes AND gates 71 to 74,
The inverters 75 to 78 and the OR gate 79 are provided, and the values of the selection control signals S1 and S2 are “11”, “01”,
When it is "10" or "00", the nMOS transistors T1, T2, T3, and T4 are turned on, respectively, and at the same time, the nMO transistor is turned on.
The S transistor T0 is turned on. The selection control signals S1 and S2 are given from the power supply line V _CC or the ground line V _SS .

[0034]

As described above, in the signal propagation delay time adjusting circuit according to the present invention, since the capacitive element is arranged in the wiring channel area, the wiring channel area is not particularly limited, and in the case of automatic wiring. Since it is possible to make a connection for adjusting the wiring capacitance, it is possible to adjust the signal propagation delay time without rearranging the cells after automatic placement and wiring.

In the automatic placement and routing method according to the present invention, the connection for adjusting the wiring capacitance is made to the net which is a problem during the automatic routing. Therefore, the signal propagation is performed without relocating the cells after the automatic placement and routing. This has the effect of adjusting the delay time.

In the first aspect of the present invention, a net is designated before automatic placement, and at the time of automatic placement, a capacity selection cell is placed near a cell connected to the designated net. The effect is that the wiring connecting to the selected cell can be shortened.

[Brief description of drawings]

FIG. 1 is a flowchart showing a principle configuration of an automatic placement and routing method according to the present invention.

FIG. 2 is a schematic configuration diagram of a gate array according to a first embodiment of the present invention.

FIG. 3 is a signal propagation delay time adjustment circuit diagram.

FIG. 4 is an enlarged circuit diagram of a main part of FIG.

5A and 5B are configuration diagrams of a capacitance cell, FIG. 5A is a plan view of the capacitance cell, and FIG. 5B is a cross-sectional view taken along line BB of FIG.

FIG. 6 is a signal propagation delay time adjustment circuit diagram of a second embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a gate array for explaining a problem of the conventional technique.

[Explanation of symbols]

10, 10A Gate array 21-25 Basic cell column 31-34 Wiring channel region 41-44 Capacitance cell column A, B, C Basic cell X1, X2 Capacitance selection cell Y1, Y2 Capacitance cell N1, N2 Net C1-C4 Capacitance element T0 to T4 nMOS transistor V _CC power supply line V _SS ground line 50 semiconductor substrate 51 to 54 electrode 55 insulating film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H01L 27/118 H03K 19/173 7827-5J

Claims (4)

[Claims] 1. A switch element for selectively turning on / off between a capacitive element (41-44, C1-C4) arranged in a wiring channel region (31-34) and an input terminal and a plurality of output terminals. (T1 to T4) provided capacity selection cell (X
And X2), the wiring between cells other than the capacitance selection cell is connected to the input end of the capacitance selection cell, and the output end of the capacitance selection cell is connected to the capacitance element. An inter-cell signal propagation delay time is adjusted by fixing ON / OFF of the switch element according to a length of inter-cell wiring. 2. The cells are composed of basic cells on a gate array, and the capacitive elements (41 to 44, C1 to C4) have electrodes (51 to 54) on a semiconductor substrate (50) via an insulating film (55). )
2. The signal propagation delay time adjusting circuit according to claim 1, wherein the signal propagation delay time adjusting circuit is arranged. 3. A wiring channel region (31 to 31) between cell columns.
34) is an automatic placement and routing method in which capacitive elements (41 to 44, C1 to C4) are placed, and automatic routing is performed after automatic placement. Before the automatic routing, a net (N1, N2) is specified, and a permissible signal propagation delay time difference between the specified nets is substantially set (1), and at the time of the automatic placement, the input end and the plurality of output ends are selectively selected. A capacitance selection cell (X1, X2) having switching elements (T1 to T4) for turning on and off is arranged as a kind of cell (2), and the specified net is connected to the capacitance selection cell during the automatic wiring. Connecting the output terminal of the capacitance selection cell to the input terminal, connecting the output terminal of the capacitance selection cell to the capacitive element, and fixing ON / OFF of the switch element so as to satisfy the set allowable signal propagation delay time difference (3). An automatic placement and routing method. 4. The nets (N1, N) before the automatic placement.
2) is specified, and at the time of the automatic placement, the capacity selection cells (X1, X) are placed near the cells connected to the specified net.
2. The automatic placement and routing method according to claim 3, wherein 2) is placed.