JPH04333261A - Automatic arrangement and wiring processing method - Google Patents

Abstract

PURPOSE:To enable a wiring to be shortened in time required for regulating a delay value by a method wherein a delay controlling element is inserted in a path which does not meet timing specification, and the inner wiring of the delay controlling element is modified. CONSTITUTION:A delay controlling element 11 is previously inserted in a path which does not probably meet a required timing specification before an automatic arranging and wiring process is carried out. Then, the inner wiring of the delay controlling element 11 is modified, whereby an optional path can be changed in delay value. By this setup, a wiring can be controlled in delay value by the modification of the delay controlling element 11 in inner circuit without executing the modification of a wiring in logic or an automatic arranging and wiring process again for the control of a wiring in delay value, and a wiring can be shortened in time required for controlling a delay value.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and wiring processing method for automatically placing and wiring elements forming an LSI (large scale integrated circuit).

0002

2. Description of the Related Art FIG. 10 is a flowchart showing an LSI design flow employing a conventional automatic placement and wiring processing method. In FIG. 10, 1 is a step of inputting a logic diagram; 2 is a step of inputting a logic diagram;
is the step of performing logical timing verification with virtual delay,
4 is a step of performing automatic placement and wiring, 5 is a step of performing logic timing verification with actual delay, and 6 is a step of determining the logic timing verification result of step 5.

FIG. 11 is a diagram showing an example of a logic circuit diagram, FIG.
2 is a diagram showing the signal waveform of the logic timing verification result due to the virtual delay of the logic circuit diagram shown in FIG. 11, and FIG. 13 is the result of placement and routing using the conventional automatic placement and routing processing method based on the logic circuit diagram of FIG. 11. Figure 14 shows a part of Figure 13.
Figure 15 shows the signal waveform of the logic timing verification result with actual delay based on the automatic placement and wiring results of , and Figure 15 shows the logic circuit diagram as a result of making changes to the logic circuit diagram of Figure 11 to adjust the delay value. 16 is a diagram showing the result of automatic placement and wiring for the logic circuit diagram of FIG. 15, and FIG. 17 is a diagram showing the signal waveform of the logic timing verification result due to the actual delay in the automatic placement and wiring result of FIG. 16.

In FIGS. 11, 13, 15, and 16, for example, 8 is a NOT gate element, 9 is an AND gate element, and 10 is a flip-flop element. Figure 15
And in FIG. 16, for example, 9 is an AND gate element,
12 and 13 are NOT gate elements.

Next, the operation will be explained. Conventional LSI
As shown in the design flow of FIG. 10, first, in step 1, which is a logic diagram input step, a logic design is performed based on the required logic operation, and the logic circuit diagram shown in FIG. 11 is created. For this logic circuit diagram, Fan-in, Fan
Step 2 of logic and timing verification using virtual delays taking into consideration -out, etc. is performed to verify whether the circuit of this logic circuit diagram operates correctly. here,
For example, assume that required timing specifications are given such that the difference in signal changes between pins A and B of element 10 in the logic circuit diagram of FIG. 11 must be 2 ns or more. Looking at the signal waveform shown in FIG. 12, which is the result of logic and timing verification using virtual delay on the logic circuit diagram in FIG. .1ns, which satisfies the required timing specifications. Therefore, the next automatic placement and routing step is step 4.
Then, automatic placement and wiring is performed based on the logic circuit diagram of FIG. 11, and the automatic placement and wiring results shown in FIG. 13 are obtained.

Next, the automatic placement and wiring result shown in FIG. 13 is subjected to a step 5 of logic and timing verification using actual delay to determine whether the required timing specification is satisfied. This verification result is shown in FIG. 14, which shows that the difference in signal change between pin A and pin B of element 10 in the logic circuit diagram of FIG. 11 does not satisfy the required timing specification of 2 ns or more. ing. In this case, the process returns to step 1, where the logic diagram input process is performed, and the logic is changed so that the required timing specifications are satisfied. Figure 15 shows the logic circuit diagram after the logic has been changed. In this case, in order to delay the signal on pin B, elements 12 and 13 are inserted between elements 9 and 10 to ensure the delay. . Based on the logic circuit diagram of FIG. 15, logic and timing verification step 2 using virtual delay and automatic placement and routing step 4 are performed in the same manner as described above.
, re-execute logic and timing verification step 5 with actual delay. The steps from the logic diagram modification (input) step 1 to the logic and timing verification step 5 based on actual delay are repeatedly executed until the required timing specifications are satisfied, and finally a placement and wiring result that satisfies the required timing specifications is obtained.

[0007]

[Problem to be Solved by the Invention] Since the conventional automatic placement and wiring processing method is configured as described above, in order to satisfy the required timing specifications, it is necessary to automatically perform automatic placement and routing from logic design taking into account the characteristics of the element itself. The logic circuit diagram must be completely changed by repeatedly redoing the placement and routing, and it takes a long time to obtain a result that satisfies the required timing specifications. There was a problem that more time was required.

The present invention was made to solve the above-mentioned problems, and is an automatic method that can obtain placement and routing results that satisfy required timing specifications without changing logic or re-automatic placement and routing. The purpose of this invention is to provide a placement and routing processing method.

[0009]

[Means for Solving the Problems] The automatic placement and routing processing method according to the present invention inserts a delay adjustment element 11 in the middle of a route that does not satisfy timing specifications, and
By changing the internal wiring, the delay value of any route can be adjusted.

0010

[Operation] The delay adjustment element 11 is inserted in the middle of a route that does not satisfy the timing specifications, and the internal wiring of the delay adjustment element 11 is changed, so that the delay value of any route is adjusted. Therefore, there is no need to change logic and re-automatically place and route for delay value adjustment.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart showing an LSI design flow employing an automatic placement and wiring processing method according to an embodiment of the present invention. In FIG. 1, the steps corresponding to those shown in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 1, 3 is a step of inserting a delay adjustment element that adjusts the delay value of an arbitrary route in the LSI in the middle of a route that does not satisfy the timing specifications, and 7 is a step of inserting an arbitrary delay adjustment element to adjust the delay value of an arbitrary route in the LSI by changing the internal wiring of the delay adjustment element. This is a step of adjusting the delay value of the route.

FIG. 2 is a diagram showing an example of a logic circuit used to explain this embodiment, FIG. 3 is a diagram showing signal waveforms of logic and timing verification results due to virtual delay of the logic circuit diagram of FIG. 2, and FIG. A diagram showing a logic circuit diagram as a result of inserting a delay adjustment element for adjusting the delay value in the logic circuit diagram in FIG. 2, FIG. 5 is a diagram showing the result of automatically placing and wiring the logic circuit diagram in FIG. FIG. 6 is a diagram showing the signal waveform of the logic and timing verification results due to the actual delay in the automatic placement and routing results of FIG. 5, and FIG.
is a diagram showing the internal wiring of the delay adjustment element inserted in Figure 4, and Figure 8 shows the internal wiring as a result of changing the internal wiring to adjust the delay value for the delay adjustment element inserted in Figure 4. 9A and 9B are diagrams showing signal waveforms of logic and timing verification results due to actual delays in the automatic placement and wiring results of FIG. 5 and the internal wiring change implementation results of the delay adjustment element.

In FIGS. 2, 4 and 5, components corresponding to those shown in FIGS. 11 and 13 are denoted by the same reference numerals, and their explanations will be omitted. 11 in Figures 4 and 5
is the delay adjustment element described above. In FIG. 7, the delay adjustment element 11 includes a wiring 14 connecting the terminal 16 and the terminal 17;
and a delay element 15. In the delay adjustment element 11 in FIG. 8, the delay element 15 is connected to the terminal 17 via the wiring 18 and to the terminal 16 via the wiring 19.

Next, the operation will be explained. As shown in FIG. 1, the design flow of an LSI according to an embodiment of the present invention is as follows.
First, in step 1, which is a logic diagram input step, a logic design is performed based on the required logic operation.
Create a logic circuit diagram as shown in . This logic circuit diagram is subjected to step 2 of logic and timing verification using virtual delays that take into account Fan-in, Fan-out, etc., and it is determined whether or not the circuit in the logic circuit diagram of FIG. 2 operates correctly. Verify.

[0015] For example, assume that a required timing specification is given such that the difference in signal changes between pins A and B of the element 10 in the logic circuit diagram of FIG. 2 must be 2 ns or more. Looking at the signal waveforms as a result of logic and timing verification using virtual delays on the logic circuit diagram of FIG. The required timing specifications are satisfied. However, if this continues, automatic placement and routing step 4
Logic and timing verification step 5 with actual delay after
In this case, there is a possibility that the required timing specification that the difference in signal change between pin A and pin B of the element 10 is 2 ns or more may not be satisfied. In this case, the process proceeds to the next delay adjustment element insertion step 3, and a delay adjustment element 11 is inserted between elements 9 and 10 in order to delay the signal at pin B in the logic circuit diagram shown in FIG. The logic circuit diagram is shown in FIG. Next, proceeding to automatic placement and wiring step 4, automatic placement and wiring is performed based on the logic circuit diagram of FIG. 4, and the automatic placement and wiring result shown in FIG. 5 is obtained.

Next, regarding the automatic placement and wiring results shown in FIG.
A logic and timing verification step 5 using actual delay is performed to determine whether the required timing specifications are satisfied. This verification result is shown in FIG. 6, which shows that the difference in signal change between pin A and pin B of element 10 in the logic circuit diagram of FIG. 4 does not satisfy the required timing specification of 2 ns or more. ing. In this case, the process proceeds to the next delay adjustment step 7 and performs delay adjustment so as to satisfy the required specifications. Here, delay adjustment is performed by changing the internal wiring of the delay adjustment element 11. Figure 7 shows the internal wiring before changing the internal wiring.
In this case, the terminal 16 is directly connected to the terminal 17 by the wiring 14, and the delay cannot be adjusted as it is. Further, the element 15 is a delay element, and may be considered to be an element equivalent to an element generally used for delay, and several of the same elements 15 are connected in series. The wiring 14 in FIG. 7 is arranged to satisfy the required timing specifications by adjusting the delay by connecting the delay element 15 as the wiring 18 and the wiring 19 as shown in FIG. Get wiring results.

As described above, according to the above embodiment, since the delay adjustment element is inserted in advance before automatic placement and routing is performed in a location where there is a possibility that the required timing specification may not be satisfied, the adjustment of the delay value can be easily performed. Therefore, the delay value can be adjusted only inside the delay adjustment element without changing the logic or re-automatically placing and wiring, and the time for adjusting the delay value can be reduced by, for example, 30% or more compared to adjustment using the conventional technology.

[0018]

As described above, according to the present invention, by inserting a delay adjustment element in the middle of a path that does not satisfy timing specifications and changing the internal wiring of this delay adjustment element,
Since the delay value of any route is adjusted, it is possible to obtain a placement and routing result that satisfies the required timing specifications without changing the logic or re-automatic placement and routing. This has the effect of further shortening the time and improving LSI manufacturing efficiency.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing an LSI design flow employing an automatic placement and routing processing method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a logic circuit diagram for explaining this embodiment.

FIG. 3 is a diagram showing signal waveforms of logic and timing verification results based on virtual delays in the logic circuit diagram of FIG. 2;

4 is a diagram showing a logic circuit diagram resulting from inserting a delay adjustment element for adjusting a delay value in the logic circuit diagram of FIG. 2; FIG.

FIG. 5 is a diagram showing the result of automatic placement and wiring of the logic circuit diagram of FIG. 4;

6 is a diagram showing signal waveforms of logic and timing verification results due to actual delay in the automatic placement and wiring results of FIG. 5; FIG.

FIG. 7 is a diagram showing internal wiring of the delay adjustment element inserted in FIG. 4;

8 is a diagram showing internal wiring as a result of changing the internal wiring for adjusting the delay value of the delay adjustment element inserted in FIG. 4; FIG.

9 is a diagram showing signal waveforms of logic and timing verification results due to actual delays in the automatic placement and wiring results and the internal wiring change implementation results of the delay adjustment element in FIG. 5; FIG.

[Figure 10] LS using conventional automatic placement and routing processing method
3 is a flowchart showing an I design flow.

FIG. 11 is a diagram showing an example of a logic circuit diagram for explaining this conventional example.

FIG. 12 is a diagram showing signal waveforms of logic timing verification results based on virtual delays in the logic circuit diagram shown in FIG. 11;

13 is a diagram showing a part of the result of placement and routing using a conventional automatic placement and routing processing method based on the logic circuit diagram of FIG. 11; FIG.

14 is a diagram showing signal waveforms of logic timing verification results with actual delay based on the automatic placement and wiring results of FIG. 13; FIG.

FIG. 15 is a diagram showing a logic circuit diagram resulting from implementing changes to the logic circuit diagram of FIG. 11 for adjusting delay values;

16 is a diagram showing the result of automatic placement and wiring for the logic circuit diagram of FIG. 15. FIG.

17 is a diagram showing signal waveforms of logic timing verification results based on actual delays in the automatic placement and wiring results of FIG. 16; FIG.

[Explanation of symbols]

8, 9, 10 elements 11 Delay adjustment element 14, 18, 19 Wiring 15 Delay element

Claims (1)

[Claims] Claim 1: In an automatic placement and routing processing method for automatically placing and wiring elements forming an integrated circuit, a delay adjustment element for adjusting the delay value of an arbitrary route is inserted in the middle of a route that does not satisfy timing specifications. An automatic placement and routing processing method characterized in that the delay value of an arbitrary route is adjusted by changing the internal wiring of this delay adjustment element.