JP2002076125A - Layout design method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize clock skew. SOLUTION: The method comprises a step 2 for recognizing flip flop cells and latch cells where the same clock signal is supplied directly before determining the number of stages of a clock tree and the number of buffer cells or inverter cells interposed as the clock tree, a step 3 for recognizing cells except the flip flop cells and the latch cells where the same clock signal is supplied directly and recognizing the flip flop cells and the latch cells where a clock signal is supplied through the cells, and a step 4 for changing a netlist of a logic level to the netlist of the configuration where buffer cells are interposed in the path through which the same clock signal is supplied directly to the flip flop cells and the latch cells. As a result, the clock signal is supplied to all flip flop cells and latch cells through other cells, and thus the clock skew is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method of a semiconductor integrated circuit for reducing clock skew.

[0002]

2. Description of the Related Art In a conventional layout design method of a semiconductor integrated circuit, clock tree synthesis for minimizing clock skew is performed by inputting a clock signal or an output terminal of a circuit for driving the clock signal from a buffer cell or an inverter cell. In this method, a clock tree is inserted so that a clock signal reaches a flip-flop or a latch cell connected to the clock signal almost simultaneously.

FIG. 6 shows a processing flow in a conventional layout design method for a semiconductor integrated circuit according to this method.

As shown in FIG. 6, first, in a data input step 2001, a logic level netlist necessary for a layout design, a physical layout of standard cells, technology data of a layout, and arrangement positions of terminals of functional blocks are controlled. Data, the arrival time of the desired clock signal, and the desired clock skew are input. Note that the equivalent of a standard cell or a macro cell is called a logic level, and data describing the connection relation of the terminals of each standard cell or macro cell is a logic level netlist. In the standard cell-based design, AND, NAND, OR, NOR, BUFFER, IN
Cells having specific functions such as VERTER, XOR, flip-flop, latch, etc. are prepared, and the transistors in the cells and the wiring connecting the transistors are:
It consists of physical mask figures, and the physical mask figure of these cells is called a physical layout. Also,
The layout technology data is data obtained by converting process rules, such as a minimum wiring width and a minimum wiring interval determined in a semiconductor process, for layout.

FIG. 2 shows an example of a connection relationship of clock signals described in a logic-level netlist.
100 is an input terminal for the clock signal CLK1, 101 is an input terminal for the control signal CNTL1, 110 is an AND logic cell, 11
1 is an inverter cell, and 1001 to 1040 are flip-flop cells. NETCLK1 has an input terminal 100 for a clock signal CLK1, an AND logic cell 110, an inverter cell 111, and flip-flop cells 1001 to 10
This is a net connecting to the Internet 20. The NET 110 includes an AND logic cell 110 and flip-flop cells 1021 to 103
This is a net connecting 0. The NET 111 is a net that connects the inverter cell 111 and the flip-flop cells 1031 to 1040. NETCNTL1 is the control signal CNTL1
Is a net connecting the input terminal 101 and the AND logic cell 110.

Next, step 2002 for recognizing flip-flops and latches connected to the same clock signal.
In FIG. 2, 20 flip-flop cells 10
It is recognized that 01 to 1020, the AND logic cell 110 and the inverter cell 111 are connected to the same clock signal CLK1. Here, the flip-flop cell 102
Nos. 1 to 1040 cannot recognize that they are connected to the same clock signal CLK1 because there is an AND logic cell 110 and an inverter cell 111 between them and the terminal 100.

Next, in a step 2003 for determining the number of clock tree stages and the number of buffer cells or inverter cells to be inserted, the number of clock tree stages, the number of clock tree stages, Determine the number of cells to be inserted into the clock tree and the driving capability of the cells.

Next, in step 2004 for inserting the cell arrangement and the clock tree, the terminals 100 and 101 are arranged according to the data for controlling the arrangement positions of the terminals of the functional blocks, and the flip-flop cells 1001 to 1040 are ANDed.
Logic cell 110 and inverter cell 111 are arranged.
After the completion of the cell placement, the buffer cell 70 as shown in FIG.
A clock tree composed of 0,701 is inserted.

Next, in step 2005 for performing wiring,
Schematic wiring and detailed wiring are performed, and then, in step 2006 for outputting data, a layout result is output.

In this conventional method, it is possible to make the arrival times of the clock signals to the flip-flop cells 1001 to 1020, the AND logic cell 110, and the inverter cell 111 substantially equal.
It is not possible to make the arrival times of the clock signals 021 to 1040 substantially equal.

[0011]

As described above, in the conventional method, a clock signal can be supplied to a flip-flop or a latch cell directly connected to a clock signal almost at the same time, but the clock signal can be supplied to a circuit other than the flip-flop or the latch cell. When the clock signal is supplied to a flip-flop or a latch cell after passing through a cell other than the flip-flop or the latch cell, there is a problem that a clock skew increases because a delay occurs for the clock signal to pass through cells other than the flip-flop and the latch cell.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a path for directly supplying a clock signal to a flip-flop or a latch cell and a path for supplying a clock signal to a flip-flop or a latch cell through a cell other than the flip-flop or a latch cell. It is an object of the present invention to provide a layout design method of a semiconductor integrated circuit which can minimize clock skew even when the numbers are mixed.

[0013]

According to a first aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit, wherein a clock signal is supplied based on data including a logic-level netlist required for the layout design of the semiconductor integrated circuit. A layout design method for a semiconductor integrated circuit in which, after determining the number of clock tree stages to be inserted into a path and the number of buffer cells or inverter cells to be inserted as a clock tree, cell placement and insertion of the clock tree and wiring are performed. Recognizing a flip-flop cell and a latch cell to which the same clock signal is directly supplied based on a logic level netlist before determining the number of clock tree stages and the number of buffer cells or inverter cells to be inserted as a clock tree. Based on the logic level netlist Recognizing cells other than the flip-flop cell and the latch cell to which the clock signal is directly supplied, and recognizing the flip-flop cell and the latch cell to which the clock signal is supplied through the cell; Changing to a netlist having a configuration in which a buffer cell is inserted into a path directly supplied to a flip-flop cell and a latch cell.

According to the first aspect, the logic-level netlist is changed to a netlist having a configuration in which a buffer cell is inserted in a path through which the same clock signal is directly supplied to the flip-flop cell and the latch cell. The number of stages of the clock tree and the number of buffer cells or inverter cells to be inserted as the clock tree are determined, the cell arrangement, the insertion of the clock tree, and the wiring are performed to directly flip the clock signal in the netlist before the change. The clock skew can be minimized even when a path for supplying the flip-flop cell or the latch cell and a path for supplying the flip-flop cell or the latch cell through cells other than the flip-flop cell or the latch cell are mixed.

According to a second aspect of the present invention, the same clock signal is directly supplied to the flip-flop cell and the latch cell in the step of changing the netlist. The buffer cell and the flip-flop cell are set so that the time required for the clock signal to pass through the buffer cell inserted in the path to be inserted and the time required for the clock signal to pass through the cells other than the flip-flop cell and the latch cell are substantially equal to each other. And a cell other than the latch cell is changed to an equivalent logic cell having an appropriate drive capability.

According to the second aspect, the clock skew can be further minimized.

According to a third aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit according to the first or second aspect, wherein the number of clock tree stages to be inserted into a path to which a clock signal is supplied and the clock are selected. The number of buffer cells or inverter cells to be inserted as a tree is determined by the sum of the input terminal capacitances of all flip-flop cells and latch cells to which the same clock signal is supplied, the arrival time of the specified clock signal, and the clock tree. And the driving capability of the buffer cell or the inverter cell to be inserted.

It is preferable to determine the number of stages of the clock tree and the number of buffer cells or inverter cells to be inserted as the clock tree.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit layout designing method according to the first or second aspect, wherein when the cell arrangement and the insertion of the clock tree are performed, the input terminal of the clock signal is used. A clock tree is inserted between cells other than the flip-flop cell and the latch cell to which the clock signal is directly supplied, and cells other than the flip-flop cell and the latch cell to which the clock signal is directly supplied, and cells other than the flip-flop cell and the latch cell. A clock tree is inserted between the flip-flop cell and the latch cell connected to the clock tree.

According to a fifth aspect of the present invention, in the layout designing method of a semiconductor integrated circuit according to the first or second aspect, after wiring is performed, the clock skew is checked, and the clock skew becomes smaller. Thus, the driving capability of the buffer cell or the inverter cell inserted as a clock tree is changed.

According to the present invention, the clock skew can be further minimized.

[0022]

FIG. 1 is a diagram showing a processing flow in a layout design method for a semiconductor integrated circuit according to the present invention.

The difference between a clock tree composed of buffer cells and a clock tree composed of inverter cells is that the number of stages of the clock tree composed of inverters must be even so as not to invert the clock signal. Only. Hereinafter, in the present embodiment, the clock tree is configured by buffer cells.

As shown in FIG. 1, first, in a data input step 1, a logic level netlist necessary for layout design, a physical layout of standard cells, layout technology data, a desired clock signal arrival time and a desired clock signal arrival time are obtained. Input clock skew.

FIG. 2 shows an example of the connection relationship of clock signals described in the logical level netlist.
100 is an input terminal for the clock signal CLK1, 101 is an input terminal for the control signal CNTL1, 110 is an AND logic cell, 11
1 is an inverter cell, and 1001 to 1040 are flip-flop cells. NETCLK1 has an input terminal 100 for a clock signal CLK1, an AND logic cell 110, an inverter cell 111, and flip-flop cells 1001 to 10
This is a net connecting to the Internet 20. The NET 110 includes an AND logic cell 110 and flip-flop cells 1021 to 103
This is a net connecting 0. The NET 111 is a net that connects the inverter cell 111 and the flip-flop cells 1031 to 1040. NETCNTL1 is the control signal CNTL1
Is a net connecting the input terminal 101 and the AND logic cell 110.

Next, in step 2 for recognizing flip-flops and latches connected to the same clock signal, the instance names and numbers of the flip-flop cells and latch cells connected to the clock signal CLK1 in the netlist are recognized. By this step 2, the clock signal CLK1 described in the logical level netlist shown in FIG.
, There are 20 flip-flop cells 1001 to 1020.

Next, the above-described network is executed by step 3 in which cells other than flip-flops and latches connected to the same clock signal are recognized, and flip-flop cells and latch cells to which clock signals are supplied through the cells are recognized. A cell other than the flip-flop cell and the latch cell connected to the clock signal CLK1 in the list is searched, the type, the instance name and the number of each cell are recognized, and the clock signal is supplied through the cells other than the flip-flop cell and the latch cell. The number of flip-flop cells and latch cells, and the instance and cell name of each flip-flop cell and latch cell are recognized.

By this step 3, the clock signal CLK1 described in the logical level netlist shown in FIG.
Are connected to the AND logic cell 110 and the inverter cell 11 except for the flip-flop and the latch.
It is found that the number of flip-flop cells connected to the AND logic cell 110 is 101, 1021 to 1030, and the number of flip-flop cells connected to the inverter cell 111 is 1031 to 1040.

Next, step 4 for changing the netlist
By inserting the buffer cell into the path where the clock signal is directly supplied to the flip-flop or latch cell, the time required for the clock signal to pass through the inserted buffer cell and the clock signal passing through the cells other than the flip-flop or latch cell The inserted buffer cells and cells other than flip-flops and latch cells are changed to equivalent logic cells having appropriate driving capacities so that the time required to pass through is approximately equal to each other.

By this step 4, as shown in FIG. 3, the buffer cell 112 is connected between the input terminal 100 of the clock signal CLK1 and the flip-flop cells 1001 to 1020.
Add. NETCLK1 is connected to the input terminal of the buffer cell 112, and the net connecting the output terminal of the buffer cell 112 and the flip-flop cells 1001 to 1020 is NET1.
It is assumed to be 12. Further, a plurality of cells having different input terminal capacitances, transistor sizes, and the like are prepared for the AND logic cell, the inverter cell, and the buffer cell, and the AND logic cell 110, the inverter cell 111, and the buffer cell 1 are prepared.
12 is a logic cell 11 in which the clock signal CLK1 is AND
0, a cell having substantially the same delay time from the input terminal to the output terminal of the inverter cell 111 and the buffer cell 112 is selected. For cell replacement, it is effective to classify cells having the same delay time from the input terminal to the output terminal and determine the rules for cell replacement.

Next, in step 5 for determining the number of clock tree stages and the number of buffer cells or inverter cells to be inserted, the configuration of the clock tree to be inserted into the net NETCLK1 and the buffer cells are determined. In addition, net NET110, NET11
1, the structure of the clock tree to be inserted into NET112 and the buffer cells are also determined. This is because the number of clock tree stages is the same, and the number of buffer cells is the net NET110, NET.
It is determined depending on the number of flip-flop cells connected to 111 and NET112. In this embodiment mode, the number of flip-flop cells driven by one buffer cell is about 10, and the number of buffer cells driven by one buffer cell is about four. The buffer cell is composed of two inverter cells connected in series.
This is a cell that is made by connecting individual cells.

According to this step 5, as shown in FIG. 4, the number of cells connected to the net NETCLK1 is three, that is, the AND logic cell 110, the inverter cell 111, and the buffer cell 112. Therefore, the input terminal 100 of the clock signal CLK1 and A
A designation is made to insert a buffer cell 400 as a clock tree between the ND logic cell 110, inverter cell 111, and buffer cell 112. Next, since the number of flip-flop cells is 20 between the buffer cell 112 and the flip-flop cells 1001 to 1020, the buffer cells 500 and 5
01 are specified to be inserted. AND
Logic cell 110 and flip-flop cells 1021 to 1
Since the number of flip-flop cells is 10 between 030 and 030, it is specified to insert the buffer cell 502 as a clock tree. Since the number of flip-flop cells is 10 between the inverter cells 111 and the flip-flop cells 1031 to 1040, a designation is made to insert the buffer cell 503 as a clock tree.

Note that 1 inserted as a clock tree
The number of flip-flop cells and the number of buffer cells driven by the number of buffer cells (or inverter cells) are determined by the input terminal capacity of the flip-flop cells and the buffer cells,
The number of flip-flop cells and the number of buffer cells driven by one buffer cell (or inverter cell) defined in the present embodiment is simplified because it depends on the drive capability of the buffer cell (or inverter cell). Therefore, the number of clock tree stages to be configured and the number of buffer cells (or the number of inverter cells) to be inserted are not limited. When the clock tree is composed of inverter cells, the basic processing is the same as that in the case where the buffer cells are used, except that the clock tree is formed in even-numbered stages.

Next, in step 6 for inserting the cell arrangement and the clock tree, the cell arrangement is performed. After the cell arrangement, the buffer cells are inserted according to the number of clock tree stages specified in step 5 and the number of buffers to be inserted. I do. In the cell arrangement, the buffer cell 4 inserted thereafter is
Cells other than 00, 500 to 503 are arranged (the buffer cells 112 are processed by cell arrangement). The cell arrangement is performed by the automatic arrangement function of the layout tool in consideration of the functional block area, wiring congestion degree, timing, and the like from the netlist. The terminals 100 and 101
The layout position is specified by the designer around the function block, or the tool automatically determines the layout position.

Here, the buffer cell 400 is obtained from the AND logic cell 110 and the inverter cell 111.
The clock signal CLK1 is supplied from the buffer cell 400 to the AND logic cell 110, the inverter cell 111, and the buffer cell 112 almost simultaneously at the position where the signal reaches the buffer cell 112 at substantially the same time. It is possible to minimize the clock skew, which is the difference between the minimum time and the maximum time at which the clock signal arrives at the AND logic cell 110, the inverter cell 111, and the buffer cell 112.

The buffer cells 500 and 501 are inserted between the buffer cell 112 and the twenty flip-flop cells 1001 to 1020 connected to the buffer cell 112, so that the flip-flop cells 1001 to 1020 can be arranged according to their positions. The cell is divided into a cell connected to the buffer cell 500 and a cell connected to the buffer cell 501. here,
For the sake of simplicity, the flip-flop cells connected to the buffer cell 500 are designated as 1001 to 1010, and the flip-flop cell connected to the buffer cell 501 is designated as 1
011 to 1020.

The buffer cell 500 is arranged at a position where a signal reaches each of the flip-flop cells 1001 to 1010 at substantially the same time.

The buffer cell 501 is arranged at a position from which a signal reaches each of the flip-flop cells 1011 to 1020 in substantially the same time.

The buffer cell 502 is arranged at a position from which a signal reaches each of the flip-flop cells 1021 to 1030 at substantially the same time.

The buffer cell 503 is arranged at a position from which a signal reaches each of the flip-flop cells 1031 to 1040 in substantially the same time.

The above-described clock tree insertion method uses the same method as the clock tree insertion in the conventional clock tree synthesis.

Next, in step 7 for examining the clock skew and changing the configuration of the clock tree, the buffer 112
, The arrival times of the signals from the AND logic cell 110 to the flip-flop cells 1021 to 1030, and the arrival times of the signals from the inverter cell 111 to the flip-flop cells 1031 to 1040. Estimate time and clock skew is much larger than desired,
If the correction cannot be made by changing the drive capacity of the buffer cell, the number of stages of the clock tree and the number of buffer cells to be inserted are changed. Here, when the clock skew is equal to or less than a desired value, it is not necessary to change the clock skew.

FIG. 5 shows the arrival time of the signal from the buffer 112 to each of the flip-flop cells 1001 to 1020, the arrival time of the signal from the AND logic cell 110 to each of the flip-flop cells 1021 to 1030, and the arrival time of the signal from the inverter cell 111 to each of the flip-flop cells. Psewell 1031-
This figure shows the result of changing the configuration of the clock tree when the clock skew is large compared to the arrival time of the signal up to 1040.

In the configuration of the clock tree shown in FIG. 4, when the difference between the distance from buffer cell 112 to buffer cell 500 and the distance from buffer cell 112 to buffer cell 501 is large, buffer cell 112 to buffer cell 500 There is a case where the difference between the time when the signal reaches the buffer cell 112 and the time when the signal reaches the buffer cell 501 from the buffer cell 112 becomes large. Therefore, the buffer cell 5
By arranging the buffer cell 600 at a position where the signal arrives at approximately the same time as 00 and 501, the signal arrives at the buffer cell 500 from the buffer cell 112 and the signal arrives at the buffer cell 501 from the buffer cell 112. It is possible to make the difference from the time required for the operation almost zero.

When the buffer cell 600 is arranged, the flip-flop cells 1001 to 102
The arrival time of each signal to 0 is determined by the logic cell 1 of the AND.
Compared with the arrival time of each signal from 10 to each flip-flop cell 1021 to 1030 and the arrival time of each signal from inverter cell 111 to each flip-flop cell 1031 to 1040, it is delayed by the time passing through buffer cell 600. Therefore, clock skew occurs.

Therefore, as shown in FIG. 5, by further adding buffer cells 601 and 602, the buffer 11
2, the arrival time of each signal from the flip-flop cells 1001 to 1020, the arrival time of each signal from the AND logic cell 110 to each of the flip-flop cells 1021 to 1030, and the arrival time of each signal from the inverter cell 111 to each of the flip-flop cells 1031 to 1040. , The arrival times of the respective signals up to approximately the same.

Next, in wiring step 8, global wiring and detailed wiring are performed, and the layout is completed.

Next, the buffer cells 400, 500, 501, 502, 503, and 503 are checked by checking the clock skew and changing the drive capability of the buffer cell (or inverter cell) inserted as a clock tree.
By finely adjusting the drive capabilities of the flip-flop cells 600, 601 and 602, the clock signal CLK1
Clock skew is minimized by making the times to reach each of 1 to 1040 approximately equal. When finely adjusting the buffer cell capacity, it is necessary to prepare a plurality of buffer cells having the same cell size and cell input / output terminal positions and different drive capacities. The method of fine-tuning the buffer cell capacity is to adjust the wiring resistance of the net driven by the buffer cell,
The wiring capacity and the gate capacity of the cell are calculated, and a rule is established so that a buffer cell having a driving capacity according to the delay time is allocated.

Finally, step 10 for outputting data
Output the layout result and the netlist into which the clock tree is inserted.

As described above, according to the present embodiment, in step 4, the logical-level netlist is transferred to the buffer cell (the buffer cell 11 in FIG. 3) through the path where the same clock signal is directly supplied to the flip-flop cell and the latch cell.
By changing to the netlist of the configuration in which 2) is inserted, after the change, a clock signal is supplied to all flip-flop cells and latch cells via cells other than flip-flop cells and latch cells (including inserted buffer cells). Therefore, in the logic-level netlist before the change, a path for directly supplying a clock signal to a flip-flop cell or a latch cell and a path for passing a clock signal to a flip-flop cell or a latch cell through a cell other than the flip-flop cell or a latch cell are included. Even if they are mixed, the clock skew can be minimized.

As described above, in step 4, FIG.
AND logic cell 110 and inverter cell 11
1. Making the buffer cells 112 cells with the same delay time contributes to minimizing clock skew.

Further, the processing in steps 7 and 9 also contributes to minimizing clock skew.

The same applies to the case where a latch cell is used instead of flip-flop cells 1001 to 1040 in the above embodiment. In addition, 1001
The same applies to the case where the flip-flop cells and the latch cells are mixed as the cells of ~ 1040.

[0054]

As described above, according to the present invention, the logical-level netlist is changed to a netlist having a configuration in which buffer cells are inserted in a path where the same clock signal is directly supplied to flip-flop cells and latch cells. As a result, after the change, the clock signal is supplied to all the flip-flop cells and the latch cells via cells other than the flip-flop cells and the latch cells (including the inserted buffer cells). Even if a path for directly supplying a clock signal to a flip-flop cell or a latch cell and a path for supplying a flip-flop cell or a latch cell through a cell other than the flip-flop cell or a latch cell are mixed, clock skew can be minimized. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow in a layout design method of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a connection diagram of a clock signal CLK1 at the time of data input in the embodiment.

FIG. 3 is a connection diagram of the clock signal CLK1 when a buffer cell 112 is inserted between the clock signal CLK1 and flip-flop cells 1001 to 1020 in FIG.

FIG. 4 is a connection diagram of a clock signal CLK1 in which a clock tree is inserted into the clock signal CLK1 of FIG. 3;

FIG. 5 is a connection diagram of a clock signal CLK1 in which the number of stages of a clock tree inserted into the clock signal CLK1 of FIG. 4 is changed.

FIG. 6 is a view showing a processing flow in a conventional semiconductor integrated circuit layout design method.

FIG. 7 is a connection diagram of a clock signal CLK1 in which a clock tree has been inserted by a conventional semiconductor integrated circuit layout design method.

[Explanation of symbols]

 Reference Signs List 100 Input terminal of clock signal CLK1 101 Input terminal of control signal CNTL1 110 Logic cell of AND 111 Inverter cell 112 Buffer cell 400 Buffer cell 500 Buffer cell 501 Buffer cell 502 Buffer cell 503 Buffer cell 600 Buffer cell 601 Buffer cell 602 Buffer cell 1001 〜１０1040 flip-flop cell

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822

Claims (5)

[Claims] 1. Based on data including a logic level netlist required for a layout design of a semiconductor integrated circuit,
After deciding the number of stages of a clock tree to be inserted into a path to which a clock signal is supplied and the number of buffer cells or inverter cells to be inserted as the clock tree, a cell arrangement and the insertion of the clock tree are performed to perform wiring. An integrated circuit layout design method, wherein, before determining the number of stages of the clock tree and the number of buffer cells or inverter cells to be inserted as the clock tree, the same clock signal is directly output based on the logical level netlist. Recognizing flip-flop cells and latch cells to be supplied; and recognizing cells other than flip-flop cells and latch cells to which the same clock signal is directly supplied, based on the netlist of the logic level, and passing through the cells. Flick to which the clock signal is supplied Recognizing a flop cell and a latch cell; and changing the logic level netlist to a netlist having a configuration in which a buffer cell is inserted in a path where the same clock signal is directly supplied to the flip-flop cell and the latch cell. A layout design method for a semiconductor integrated circuit, characterized in that: 2. The method according to claim 1, wherein in the step of changing the netlist, a time required for the clock signal to pass through a buffer cell inserted in a path through which the same clock signal is directly supplied to the flip-flop cell and the latch cell; The buffer cell and the cells other than the flip-flop cell and the latch cell are changed to equivalent logic cells having appropriate driving capabilities so that the time required for the clock signal to pass through the cell is substantially equal to each other. 2. The layout design method for a semiconductor integrated circuit according to claim 1, wherein: 3. The determination of the number of clock trees to be inserted into a path to which a clock signal is supplied and the number of buffer cells or inverter cells to be inserted as the clock tree is determined by all flip-flops to which the same clock signal is supplied. Sum of the input terminal capacitances of the positive and negative cells,
3. The layout design method for a semiconductor integrated circuit according to claim 1, wherein the method is performed based on a designated clock signal arrival time and a drive capability of a buffer cell or an inverter cell inserted as the clock tree. 4. When a cell is placed and a clock tree is inserted, the clock tree is inserted between a clock signal input terminal and a cell other than a flip-flop cell and a latch cell to which the clock signal is directly supplied. Inserting the clock tree between cells other than the flip-flop cells and latch cells to which the clock signal is directly supplied, and flip-flop cells and latch cells connected to cells other than the flip-flop cells and latch cells. 3. The layout design method for a semiconductor integrated circuit according to claim 1, wherein: 5. The method according to claim 1, wherein after wiring is performed, a clock skew is checked, and a driving capability of a buffer cell or an inverter cell inserted as a clock tree is changed so as to reduce the clock skew. 2. A layout design method for a semiconductor integrated circuit according to item 2.