JPS61144040A - Equal-capacity wiring method of lsi - Google Patents

Abstract

PURPOSE:To extremely simply equalize the capacity by correcting the capacity balance between wirings. CONSTITUTION:It is a matter of common knowledge that capacity is generated in a wiring pattern between it and a substrate, between it and wiring of another layer and between other wirings of the same layer. Capacity value Cc per unit area is determined for the wiring layers by taking those influence into consideration. An area S is obtained in an layout for the capacity value Ca to be compensated to set the capacity pattern, and the shape of the pattern is decided to match to it. The area S is obtained by Ca/Co. Here, the capacity pattern is performed by a rectangular shape, an inlaid net or mesh in response to the compensating capacity value C, and the type number of the capacity pattern is determined by the relationship between the value C of the variation in the capacity value to be compensated and the capacity value to be compensated.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a method for wiring an LSI.

(Prior Art) A block signal in a logic circuit is supplied to the input terminal of a large-scale integrated circuit (hereinafter referred to as "Lll"), and is sent to each flip-flop (hereinafter referred to as F/F) via a distribution gate block. Although it is propagated to the input terminal, the wiring results of each block circuit realized by placement and wiring design do not have the same shape, so the wiring from the LSI block input terminal to each F/F
There is usually a difference in the delay time to the input terminal.

This time difference is called a block-schiera, and must be kept as small as possible in order to realize a high-speed logic circuit with a short block cycle time. LSI
The delay time due to wiring can generally be expressed by the following equation.

'l'pd=αCR+β Here, Tpd is the delay time, C is the capacitance, R is the output resistance of the block terminal, and α and β are constants determined by C and H.

In other words, K, which matches 'l' pd between different routes, can be adjusted by simply adjusting the value of C.

The first document showing the prior art (A. H. Dansky).

“Bipolar C1rcuit Design f
or a 5000-Circuit VLSI Ga
te Array, "IBM J, RE8°D] A'1
LOP, VOL, 2s No3 MAY 1981.
), the delay time is adjusted by changing the value of the resistor R to compensate for the speed of the critical path. #! Fi of document 1
In g3, a resistor of 81 (Ω) is installed in parallel in the basic circuit, and depending on the delay time of the circuit, one resistor can be used, or
Distinguish whether to use both, and Ω to 4.

and 8 kg. The layout method for these two resistance values is determined by whether or not to make a contact at the position where the resistance line and the power supply cross.

When using this method, since the processing is closed within a block, it does not affect the placement or wiring results between blocks, so it is possible to evaluate the delay time and compensate for it as post-processing of the wiring. can. However, the resistors must be built into the basic circuit, and they must have a constant value, and there is a limit to their number. Therefore, when used for delay time compensation, there remains the problem that fine adjustment is not possible. Also, changing the resistance involves increasing or decreasing the power, which increases the speed of high-speed LS.
In order to realize I, an excessive amount of electric power may be required.

Alternatively, for blocks with the same function, the power value,
In some cases, multiple types of alternative blocks with different delay times are prepared and the optimal one is selected after wiring.

Literature (R. Donze et al., “PHILO-Human VLSID
ESIGN 8TSTEM,” 19th Des
ign Automation Conference
e, Jane 1982. pp, 163-169
) This method has the advantage of being able to compensate for the delay time in the subsequent process, even if no special consideration is taken during placement and wiring, as in the above-mentioned example.

(Problems to be Solved by the Invention) However, there is a drawback that the number of types of alternative blocks that must be prepared increases, and if the method is limited to only those that are possible in practice, the purpose of finely adjusting the delay time cannot be achieved.

An object of the present invention is to provide an equal capacitance wiring method that solves the above-mentioned drawbacks.

(Means for Solving the Problems) The method of the present invention uses a capacitor pattern having a plurality of types of capacitance values, and a block provided with at least one region in which the capacitor pattern is installed at the input and output terminals of the block. Use, L
A method for wiring an LSI with equal capacitance, characterized in that the capacitance of one circuit is made equal in the following steps in order to compensate for signal propagation delay time in an SI circuit.

A first step of inputting circuit connection data, block terminal position information, and block structure information; a second step of arranging the blocks based on the information input in the first step; The third step is to perform wiring between blocks based on the arrangement information obtained in step 1, the terminal position information and circuit connection information input in the first step, the step M4 is to calculate the capacity of all circuits, etc. A fifth step is to find the maximum capacitance value within the circuit group that requires capacitance, and the difference between the maximum value obtained in this fifth step and the capacitance value of each circuit is calculated and compensated. Obtain the power capacitance value,
a sixth step of selecting a capacitance pattern with that compensation value, a seventh step of editing the nine device and wiring results obtained in the third step for the mask pattern, and if the circuit requires equal capacitance. and an eighth step of embedding the pattern selected in the sixth step into the mask pattern created in the seventh step.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 3, the signal distribution circuit applied to the present invention includes a block terminal 9 that inputs a block signal from the outside, and a distribution gate 201 (distribution gate) 20 that receives the block signal from the block terminal 9 and distributes the block signal. It consists of circuits 45-48, and F/Fs 51-54 connected to these circuits 45-48.

Referring to FIG. 4, the distribution gate 20 shown in FIG.
The signal distribution block 821 including the master slice LSI
An example composed of is shown.

The master slice L19I is a cell in which elements such as transistors and resistors are pre-fabricated (as is well known), and is used as an LSI
The structure is arranged in a matrix of mxn on the step, and in the block that realizes the function, the cells are kxl (1≦m).

The cells are used in a matrix of 1 x 1 x n) and are realized by providing metallized wiring between the elements within the cell.

Here, the distribution block is configured using three cells from cell 1 to cell 3. In cell 1, the capacitance pattern installation section 11 is connected to the external terminal 21, and the capacitance pattern installation section is connected to the external terminal 22. 12 are available. Similarly, in one cell 3, a capacitive pattern installation section 32 for the external terminal 23 and a capacitive pattern installation section 31 for the external terminal 24 are prepared. The cell 2 is realized by the distribution gate 20 itself and has an input terminal 25 and output terminals 21-24. The distribution gate section 20 is connected to each capacitor pattern installation section by extending connection lines 41 to 44.

FIG. 5 shows nine examples in which the signal distribution block shown in FIG. 3 and including the nine distribution gates 20 is constituted by a building block LSI.

Building Block LSI (Matahiro Polycell LSI
) is intended to facilitate the layout design of the entire LaI by preparing blocks with fixed internal layouts (for example, Nant Gate, 7 Lips, etc.) in advance.

The big difference from the master slice method is that the LSI tip surface is not fixed, so the layout is designed to minimize the chip area (the area occupied by the blocks cannot be reduced, so the wiring area between blocks is reduced). Reach your goal.

``The details of rLSI technology written by ah & Ben et al.'' Institute of Electronics and Communication Engineers, 1975
4.3 can be referred to.

Inside the package 7, there are capacitance pattern installation sections 11, 12, 3.
1.32, distribution gate 20, input terminal 25, output terminals 21-24 and connection lines 41-44 are installed.

Capacity pattern installation part 1 shown in FIGS. 4 and 5
1, 12, 31, and 32 are left as empty areas in the block itself, so that the function of the block itself will not be impaired even if a capacitance pattern selected as a delay compensation for the wiring result between the pulls and the pulls is placed. Make it. Next, a method for selecting a capacitance pattern for capacitance compensation will be explained in detail using Fig. 6 and Fig. 6B.

It is a well-known fact that capacitance occurs between a wiring pattern, the substrate, wiring on another layer, and other wiring on the same layer. Taking these influences into consideration, the capacitance value (co) per unit area is determined for each wiring layer.

When installing a capacitance pattern, the capacitance value to be compensated (C
For a), find the area 0 on the layout and decide the shape of the baton to match it.

This relationship is shown in FIG. 6A. FIG. 6B shows an example of the shape of the capacitance pattern depending on the capacitance value to be compensated.

Here, the capacitance pattern is realized in a rectangular, zigzag, or mesh shape depending on the compensation capacitance value (ΔC).

For example, the capacitance (CO) per unit area of one layer is 5X 1
When 0-'Pk'/pm2, an area of 2000 μrtN is required for compensation of 0.1 PF. The 18Ii class number of the capacitance pattern is determined by the relationship between the value of the change in capacitance value to be compensated (ΔC) and the maximum value of the valley ii:ak to be compensated.

Next, a capacitance compensation method will be described in detail with reference to the drawings. FIG. 1 is a flowchart showing a control method for realizing the equal capacitance self-e-line according to the present invention, and is composed of a plurality of processing boxes and judgment boxes. This process can be realized by creating a program and running it on the computer according to this flowchart, or it can be done by
- It can also be realized by operating it as software.

This can also be achieved by performing all processing manually. And it is clear that the results achieved with each of them will be the same.

Therefore, among these implementation methods, the following explanation focuses on the case where it is implemented by a program.

FIGS. 2A to 2C show various types of information necessary to implement the process shown in FIG. 1, and are generally stored in the memory of the combiator.

FIG. 2A shows terminal capacitance values 83 and capacitance pattern installation positions @84 for each terminal 82 of blocks 821 and 822. Here, the blocks 821° and 822 correspond to the above-mentioned distribution gate blocks 821° F/Fs 51 to 54. Of course, for blocks that do not have a capacitance pattern installation area, the capacitance pattern installation position f[i, 84
has no information. In FIG. 2B, circuit information that requires equal capacitance is shown, and for each circuit group 85 that requires equal capacitance, the circuit name 86 in that group, the capacitance 1 value 87, the compensation answer Ji[sa, the capacitance There is information on pattern salt 89 and capacitance pattern installation position f891. Here, the circuit group 85 that requires equal capacitance corresponds to a group of circuits 45 to 48 shown in FIG. 3. Therefore, the circuit name 86 describes these circuits 45 to 48. The capacitance (i87, compensation capacitance fi [88,) is stored after the capacitance calculation. Also, the capacitance pattern salt 89, capacitance) (the turn installation position 891 is also calculated from the compensation capacitance value to the capacitance) is stored after selecting a turn. Therefore, in the initial state, the circuit name is 86.
It is displayed only because it is stored.

FIG. 2C shows the correspondence between the compensation capacitance value and the capacitance turn name. Here, the first compensation capacitance value 810 and the second compensation capacitance value 811 have a magnitude relationship with respect to the first compensation capacitance value 810.
A capacitance pattern salt 812 is used to compensate for the capacitance that falls within the range from the first compensation capacitance value 810 to the second compensation capacitance value 811.

Ideally, it would be better to prepare one capacitor (turn name) for each compensation capacitance value, but there would be an infinite number of capacitor turns. Therefore, by specifying a certain range and using a common capacity pattern, the number of types is reduced.

Based on the above information, FIG. 1 will be explained below.

(Placement and Routing) Circuit connection information 701 and physical structure information 702 of LSI and blocks are inputted in a processing box 71, and placement positions between the blocks are determined in a processing box 72. Next, a processing box 73 performs wiring between blocks based on the arrangement information, block terminal position information, and circuit connection information.

(Equivalent capacitance) Next, circuit capacitance calculations are performed for all circuits. In the decision box 74, it is determined whether or not the processing of all circuits has been completed, and if the processing has been completed, the process moves to a decision box 76.

If it is not finished, the process moves to processing box 75 and calculates the capacity of the circuit.

The capacitance of the circuit is calculated from the terminal capacitance C1 and the wiring capacitance CW, as described above.

To find the terminal capacitance C1, check the blocks 821 and 822 and the terminal name 82 in Figure 2A based on the circuit configuration blocks and terminals, extract the corresponding capacitance value 83, and calculate each extracted terminal capacitance. The terminal capacitance value is determined by adding up the terminal capacitance values. The wiring capacitance value CW is determined by the total line length of each wiring layer of the circuit wiring result, 11, and the line width of each wiring layer (W+
) and the capacitance value (C, t) per unit area.

(Note: Here, it is assumed that there are two wiring layers.) The capacitance of the corresponding circuit is determined by adding up the wiring capacitance C and the terminal capacitance ct thus obtained.

The capacitance value obtained here is stored as the capacitance value 87 for the corresponding circuit name 86 when the circuit is registered in the g2B diagram as a circuit that requires equal capacitance. If the circuit does not require equal capacitance, this process is unnecessary.

In decision box 76, it is determined whether all of the circuit groups 85 that require the same capacity as shown in FIG. 2B have been completed, and if they have been completed, the process moves to decision box 710.

If the process has not been completed, the process moves to processing box 77.

In processing box 77, the maximum capacitance value within the circuit group requiring equal capacitance is determined. For this method, the second
The capacitance values 87 of the circuits 86 in the circuit group 85 that require certain equal capacitances in diagram B are compared, and the maximum value is determined.

The judgment box 78 judges whether all the circuits in the circuit group have been completed, and when they have been completed, the process moves to the judgment box 76 and processes the next circuit group.

If the process has not been completed, the process moves to processing box 79.

In a processing box 79, the difference between the maximum capacitance 1 obtained in the processing box and the capacitance value 87 of the circuit shown in FIG. 2B is calculated, a compensation capacitance [L88] is obtained, and a capacitance pattern is selected. In this method, it is checked whether the compensation capacitance value falls within one of the range designations of the first compensation capacitance value 810 and the second compensation capacitance value 811 shown in FIG. 2C, and the capacitance corresponding to the corresponding range designation is determined. The pattern 812 is determined and used as the capacitance pattern salt 89 of the corresponding circuit shown in FIG. 2B. Further, the installation position t1891 is determined by adding up the arrangement position of the block on the LSI and the capacitance pattern installation position @84 in the package shown in FIG. 2A.

(Mask information creation) In the judgment box 710, it is determined whether processing of all blocks to be exchanged with mask information has been completed, and when the processing has been completed,
Move to judgment pox 12. If the process has not been completed, K moves to processing box 711.

In processing box 711, the block placement result is edited for mask information, outputted to mask information file 717, and the process returns to decision box 710.

In the decision box 712, it is determined whether the processing of all circuits for converting into mask information has been completed, and when the processing has been completed, the processing is completed.

If the process ends and there is no one left, the process moves to processing box 713.

In processing box 713, the wiring result is edited for mask information, outputted to mask information file 717, and the process moves to decision box 714.

In decision box 714, it is determined whether the circuit requires equal capacitance, and if the circuit does not require equal capacitance, the process returns to decision box 712. If the circuit requires equal capacitance, the process moves to decision box 715.

In the decision box 715, it is determined whether all the capacitance patterns of the circuit have been installed, and when the installation has been completed, the process returns to the decision box 712.

If it is not finished, the line moves to processing box 716.

The capacitance pattern 89 selected by the processing box 79 shown in FIG.
Output to.

When the processing in processing box 716 is completed, judgment box 71 is displayed.
Return to step 5.

An example of how to implement the procedure described above is shown in FIGS. 7A and 7B. FIG. 7A shows distribution gate block 821 having capacitance pattern installation parts 11 and 12, F/Fs 51 and 52, and circuits 45 and 46 connecting distribution gate block 821 and F/Fs 51 and 52. As a result of calculating the capacitance of the circuit in the processing box 75 of FIG. 1, the capacitance value of the circuit 45 is 10FF, and the capacitance value of the circuit 46 is 8PF.
Suppose that it becomes If it is necessary to equalize the capacitance between the circuit 45 and the circuit 46, use the processing box 79 in FIG.
The compensation capacitance value of 2PF is required for the circuit 46, and the roaring capacitance pattern b is selected.

Then, this selected capacitance pattern b is installed in the capacitance pattern installation section 12 according to the processing box 716 in FIG.

As described above, equal capacity is achieved.

(Effects of the Invention) The present invention enables equal capacitance to be achieved without any changes to the layer 9 results after placement and wiring, and also eliminates the need for complicated programs that are required when equal capacitance is performed by automatic routing. This has the effect of avoiding changes.

According to the present invention, fine adjustment of block spacing can be achieved by expanding the capacitance pattern, and delay adjustment can be realized without increasing power.

[Brief explanation of the drawing]

1st ri! Company i, a flowchart showing the processing procedure of the capacitance wiring method, jllE2A, 2B, 2CvAa, Fig. 1 A diagram showing the information necessary to perform the processing and judgment in the O flow diagram, Fig. 3 is a block system Circuit diagram showing signal distribution of the circuit, Figure 4 line, distribution gate block is master slice LSI
FIG. 5 is a diagram showing an example in which the distribution gate block is constructed with a building block LSI.
FIG. 7g is a diagram for explaining a method of selecting a capacitance pattern for compensating for damage to children, and FIGS. 7 and 7B are diagrams showing an example of equalization of capacitance. In Figures 1 to 78, 82...Song block terminal name, 83...Song terminal capacitance value, 84...Song capacity pattern installation position, 85...Circuit group requiring equal capacitance, 86...Circuit name that requires equal capacity, 8
7...Circuit capacitance value, 88...Song compensation capacitance value,
89...capacity pattern salt, 891...music capacity pattern name installation position, 81O...first compensation capacitance value, 8
11... Second compensation capacitance value, 812...
・Capacity pattern salt, 821...Tune distribution gate block,
822...Block 2.9...Block terminal, 2o...Track distribution gate, 45-48...-m path, 51-54...Flip hoop (F /F
), 11.12.31゜32... Capacity pattern installation section, 1, 2.3...---4 le, 41-44.
・Song connection 5-in, 21-24...Song output terminal, 25...
...Input terminal, 7...Block, 3rd
Figure Z5 ・Hekahide F letter 14 [! I

Claims (1)

[Claims] Compensation for signal propagation delay time of an LSI circuit using capacitance patterns having a plurality of types of capacitance values and a block having at least one area for installing the capacitance pattern at the input and output terminals of the block. An LSI equal capacitance wiring method characterized in that circuits are made equal in capacitance by the following steps. A first step of inputting circuit connection data, block terminal position information, and block structure information, a second step of arranging between blocks based on the information input in the first step, and a second step of inputting circuit connection data, block terminal position information, and block structure information; A third step of wiring between blocks based on the arrangement information obtained in step 1 and the terminal position information and circuit connection information input in the first step, and a fourth step of calculating the capacity of all circuits. The fifth step is to calculate the maximum capacitance value within the circuit group that requires equal capacitance, and calculate the difference between the maximum value obtained in this fifth step and the capacitance value of each circuit, and calculate the compensated value. Obtain the capacitance value that should be,
The sixth step is to select a capacitance pattern with the compensation value, the seventh step is to edit the placement and wiring results obtained in the third step for the mask pattern, and if the circuit requires equal capacitance. and an eighth step of embedding the pattern selected in the sixth step into the mask pattern created in the seventh step.