JPH07191866A - Arithmetic execution error detecting system - Google Patents

Abstract

PURPOSE:To perform error deciding processing at high speed and to secure the safety of the outputted result concerning the arithmetic execution error detecting system for a program. CONSTITUTION:Concerning an instruction processing means for successively storing input data in a storage means corresponding to bits, performing arithmetic while using the data of correspondent bits in this storage means, transferring the arithmetic result to the prescribed bit of the storage means and storing the result, this means is provided with a flag memory 10 corresponding to the respective bits of an executing example storage means, and a store instruction 14 is provided with plural operands OP 1 and OP 2 as the instruction words of arithmetic. At the time of any arithmetic execution error, a reading instruction performs error detection by checking two operands of the store instruction 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program execution error detecting method.

[0002]

2. Description of the Related Art As a language expression for a programmable controller, there is a block diagram expression, for example, as shown in FIG. In the figure, Z0 to Z3 are input data, f
0, f1, and f2 indicate calculation. In addition, FIG.
Indicates a work memory used for instruction processing in this language expression, and FIG. Each of the operations f0, f1, and f2 is a load instruction (LD) 12 that reads the first operand, and an operation instruction (f that reads the second operand and performs an operation on the first operand.
0, f1, f2) 13 and a store instruction (ST) 14 indicating the storage destination of the operation result.
Note that FIG. 9B shows the content of the calculation f2 as an example.

A conventional instruction processing method using such a block diagram representation is performed as follows. First, input data Z
0 to Z3 are substituted into the respective bits of T0 to T3 of the work memory 11 configured in the vertical direction in the vertical direction in the bit unit shown in FIG. Next, the calculation f0 is performed using T0 and T1 of the work memory 11 corresponding to the input, and the calculation result is substituted into T0 of the work memory 11.

Similarly, the calculation f1 is performed using T2 and T3 of the work memory 11 corresponding to the input, and the calculation result is substituted into T2 of the work memory 11. Since this calculation result is also used in the calculation f2, it is transferred to T1 of the work memory 11 (this is represented by the vertical connection 15 in FIG. 3).

Further, the calculation f2 is also performed by using T0 and T1 of the work memory 11 corresponding to the input, as in the above.
The calculation result is substituted into T0 of the work memory 11.
In this way, the final result is output from the work memory T0 to the memory Z4.

By the way, when an operation execution error (division by 0, BCD code error, etc.) occurs in the instruction processing process in the operations f0 to f2, the instruction is notified to the store instruction 14, and the store instruction is notified. NOP (no opera
tion). At this time, the warning flag is turned on to warn the user. In the programmable controller, the NOP process does not perform any process and shifts to the next instruction execution.

[0007]

In the conventional instruction processing method as described above, there is no means for notifying the operation of the next stage even if an operation execution error occurs. Therefore, the instruction of the next stage using the same work memory is used. If the command ends normally, there was a problem that it would be output as if it were a normal result, even though the data in error was used. Therefore, if the user misses the warning, there is a risk that the control may be abnormal after the actual operation.

In order to solve this problem, there is also a system in which a bit memory corresponding to a bit is added to each work memory, judgment is made by an instruction word in which a read operation is performed, and a store instruction is notified. There was a problem that it became slow and it was lacking in practicality.

According to the present invention, not only the operation resulting in the operation execution error, but also the operation instruction using the operation result is NOP, so that the safety of the output result is guaranteed and the determination is made only by the store instruction. The purpose of the present invention is to realize an operation execution error detection method that enables high-speed error determination processing.

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in FIG. 1 (a), each bit T0, T1, ... Of the work memory 11 as a storage means.
Is provided with a bit memory 10 having bits t0, t1, ... Corresponding to
2B, a plurality of operand information, that is, not only the first operand OP1 indicating the store destination but also the second operand OP2 is added to the store instruction 14 in FIG.

[0011]

In such a structure, when an operation execution error occurs, first, the flag of the corresponding flag memory 10 is turned on by the store instruction of the operation in which the operation execution error occurred. Next, in the process for the vertical connection 15 (FIG. 3), the error data and the flag that has been turned on are transferred.

The instruction that performs the read operation executes the instruction regardless of whether or not there is an operation execution error in the preceding stage. Then, the store instruction 14 determines on / off of the flags corresponding to the first and second operands and determines whether the data in which the operation execution error has occurred is used. As a result, it is possible to detect an operation execution error and quickly notify that there is an operation execution error in the next stage.

[0013]

EXAMPLES Examples will be described based on the principle of the present invention. In this embodiment, in the instruction processing shown in the block diagram of FIG. 3, processing when an execution error occurs in the operation f1 will be described. Note that this processing is executed based on the instruction stored in the program memory 9 using the work memory 11 and the flag memory 10 shown in FIG.

First, when an execution error occurs in the operation f1 of FIG. 3, the store instruction turns on the flag t2 of the flag memory 10 corresponding to the bit T2 of the work memory 11 and also turns on the warning flag for the user. At this time, in the process indicated by the vertical connection 15, the data is copied from T2 of the work memory 11 to T1, and t2 of the flag memory 10 is copied to t1. As a result, the error information (flag turned on) is copied to the flag corresponding to the operation of the next stage.

[0015] Here, operation f2, as shown in Figure 2, relative to T0 read out to the work register by the load instruction LD by "instruction 12, executes the arithmetic f ₂ with instruction 13 in T1, the instruction 14 stores the result in the first operand OP1 and the second operand OP2 by the store instruction ST ". Then, the load instruction 12 and the operation instruction 13 do not check on / off of the error flag, but the store instruction 14 checks and sets the error flag.

That is, in the store instruction 14, since the memory used in the operation is known from the first operand T0 and the second operand T1, the bits t0 and t1 of the corresponding flag memory 10 are checked. Since the bit t1 is turned on here, it is processed as an execution error. That is, the flag t ₁ of the flag memory 10 is turned on by transferring the flag t ₁ without performing the store process.

As a result, all operation instructions that use the T2 bit of the work memory 11 that has once become an error are NO.
P. If the user can monitor and access the flag memory 10, it is possible to provide more detailed error information (identification of error occurrence location, etc.).

[0018]

According to the present invention, the second operand is added to the store instruction in addition to the first operand indicating the store destination, and it is set to ON when an operation execution error occurs during execution of the store instruction. Only by checking the flags corresponding to the first and second operands, it is possible to detect an error and inform at a high speed that there is an execution operation error in the next stage, and an operation execution error has occurred. By setting not only the operation but also the operation instruction using the operation result to NOP, an excellent effect such as ensuring the safety of the output result can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing the contents of a calculation f2 in the embodiment.

FIG. 3 is a diagram showing an example of a block diagram expression as a language expression for a programmable controller.

FIG. 4 is a diagram showing a work memory used in FIG. 3 and contents of calculation.

[Explanation of symbols]

 10 flag memory 11 work memory 12 load instruction 13 operation instruction 14 store instruction

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location B32B 27/04 A 8413-4F G05B 19/048 G06F 11/30 320 C 9290-5B // B29K 105 : 08 B29L 9:00

Claims (2)

[Claims] 1. An instruction processing means for sequentially storing input data corresponding to bits in a storage means, performing an operation using the bit data of the storage means, and transferring the operation result to a predetermined bit of the storage means for storage. In the flag memory (1
0) is provided, and a plurality of operands (OP1, OP2) are provided in the store instruction (14) as the instruction word of the above operation, and error detection is performed by checking the operands of the store instruction. Error detection method. 2. The operation instruction word is a load instruction (12) for reading a first operand (OP1), and an operation for reading a second operand (OP2) and performing an operation with the first operand (OP1). An instruction (13) and a store instruction (14) indicating a storage destination of the operation result,
The operation execution error detection system according to claim 1, wherein a second operand (OP2) is provided as an operand of the store instruction (14) in addition to the first operand (OP1) indicating a store destination.