JPH05165874A - Vector arithmetic processor - Google Patents

Abstract

PURPOSE:To prevent the arithmetic processing speed by an overhead from reducing. CONSTITUTION:In a vector arithmetic processor provided with a first register 3 holding a number of a next arithmetic element for which a processing is to be resumed for the occurrence of an arithmetic interruption reason such as an interruption, etc., in the process of the vector arithmetic processing of an arithmetic element held in a vector register 1, a second register 5 saving the content of the first register 3 at the time of starting the vector operation of the arithmetic element held in the vector register 1 and a control means 6 performing the zero clear of the first register 3 after performing the saving operation for this second register 5 and returning the content of the second register 5 to the first register 3 for the occurrence of the arithmetic interruption reason are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector operation processing device, and more particularly, to a process for a reason for interrupting an operation such as an interrupt in the middle of vector operation processing of an operation element held in a vector register. The present invention relates to a vector operation processing device including a register that holds the number of the next operation element that should resume processing after the end.

[0002]

2. Description of the Related Art Conventionally, as an arithmetic processing unit suitable for repeatedly performing the same processing on a plurality of data, "IBM System / 370 Vector Op" of IBM Corporation has been used.
", or JP-A-63-31570.
There is known a vector arithmetic processing device as described in Japanese Patent Laid-Open Publication No. Hei 1-309174 or the like.

In such a vector operation processing device, an instruction code indicating the operation contents such as addition and subtraction, index data for specifying the operation element number at which the operation is to be started, and an operation element number for ending the operation are provided. Operand data consisting of a specified vector count value is read from the storage device, and based on this operand data, the operation element (data) to be operated held in the vector register is accessed, and the instruction code is accessed. Performs the operation specified by the command.

In this case, it is sometimes desired to interrupt the vector calculation process due to the internal environment of the system different from the vector calculation process. For example, this is a time when an operation interruption reason such as an internal or external interruption of the device occurs and the processing for the operation interruption reason must be prioritized.

However, when the arithmetic processing is interrupted, if the processing for the reason for the arithmetic interruption is completed, the arithmetic operation must be restarted from the next arithmetic element after the interruption. Therefore, a vector index register (first register) for holding the operation element number for restarting the processing is provided, and when the processing for the reason for interrupting the operation is completed, the operation of the operation element number indicated by the contents of this vector index register is performed. It is configured to resume processing from the element.

This vector index register designates the number of the first vector element in the vector register to be processed by a vector facility instruction (VF instruction) such as addition and subtraction which interrupts are allowed during the operation. However, normally, "0" is set at the start of execution of the instruction. Then, it is not updated until a reason for interrupting the operation such as an interrupt occurs in the middle of the vector operation processing for the VF instruction. However, when the reason for interrupting the operation occurs, the content of the vector index register is updated by adding the number of processing elements up to that point to the content of the vector index register, and the operation element to be processed next is set. .. Then, when the processing for the vector instruction is completed, the processing is cleared to zero on the condition that the processing for the reason for interrupting the operation such as interruption is completed.

If the index register is cleared to zero without confirming that the processing for the reason for interrupting the operation such as interruption is completed, the next operation element for which the operation processing is interrupted becomes unknown and the operation becomes impossible.

[0008]

In the above-described conventional vector arithmetic processing device, as described above, when the processing for the vector instruction is completed, the processing for the reason for interrupting the arithmetic operation such as the interrupt is finished. Since it is determined whether or not it has been completed and zero-cleared on the condition that it has been completed, the determination time is required for each VF instruction, and the processing time per instruction becomes longer by that much, and arithmetic processing by the overhead is performed. There was a problem that a decrease in speed was inevitable.

That is, as shown in FIG. 3, considering the case where data A and B having n operation elements are simultaneously processed in accordance with a VF instruction, an interrupt or the like occurs at the time t when the processing for the VF instruction is completed. It is judged whether or not the processing for the reason for the operation suspension of is finished, and the index register is cleared to zero on the condition that the processing is finished. Therefore, regardless of whether or not the reason for interrupting the operation has occurred, the VF
The judgment time T is required for each instruction, the processing time per instruction is increased by T time, and a reduction in the operation processing speed due to the overhead between vector operation instructions cannot be avoided.

It is an object of the present invention to provide a vector arithmetic processing device capable of preventing a reduction in arithmetic processing speed due to overhead.

[0011]

In order to achieve the above object, the present invention is directed to the reason for interrupting an operation, such as an interrupt, during the vector operation of an operation element held in a vector register. In a vector arithmetic processing device having a first register for holding the number of the next arithmetic element which should resume the processing after the processing is completed, the content of the first register is stored in the vector register. The second register saved at the start of vector operation and the first register for this second register
After the contents of the register are saved, the first register is cleared to zero, and the contents of the second register are restored to the first register in response to the occurrence of the operation interruption reason.

[0012]

According to the above means, the contents of the first register are saved in the second register at the beginning of execution of the vector operation instruction, and then the first register is cleared to zero. Then, if a reason for interrupting the operation occurs during execution of the vector operation instruction,
When the content of the second register is restored to the first register and the processing for the reason for interrupting the operation is completed, the operation is started from the operation element of the operation element number indicated by the content of the first register. For this reason, it is not necessary to determine whether the processing for the reason for interrupting the operation such as an interrupt is completed when the processing for the vector operation instruction is completed, and the overhead is eliminated.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which is a vector register (VR) holding arithmetic elements.
1 is provided. This vector register 1 is 0
It is composed of 16 registers of F, and each has elements for the section size.

Further, a vector mask register (VMR) 2 for holding a mask bit for validating or invalidating the calculation for each calculation element of the vector register 1 is provided. The vector mask register 2 is composed of the same number of bits as the number of elements of each register of the vector register 1, and one bit corresponds to one element.

Further, 0 to 0 in the vector register 1
A vector number register 3 for designating the numbers of 16 F registers is provided.

Further, a vector facility instruction (VF instruction) such as addition and subtraction for which interruption is allowed during the operation
A vector index register (VIX) 4 for designating the number of the first operation element in the vector register 1 to be processed by is provided, and the vector operation of the operation element held in the vector register 1 is performed by the content of the vector index register. After saving the contents of the vector index register 4 to the second register (SVIX) 5 to be saved at the start of
A control unit 6 is provided which clears the vector index register 4 to zero and restores the contents of the second register 5 to the vector index register 4 in response to the occurrence of an operation interruption reason such as an interrupt.

Here, 7 is an adder for adding the signal inc indicating the number of processing elements already processed to the content of the vector index register 4, and the addition result is input to the selector 8 where the control unit is. It is selectively output by the selection control signal S1 generated from 6 and set in the vector index register 4. The setting operation in this case is controlled by the control signal S1 generated from the control unit 6. The operation of setting the value output from the vector index register 4 in the second register 5 is as follows.
Similarly, it is controlled by a control signal S2 generated from the controller 6.

In such a configuration, the vector index register 1 is normally set to "0" at the start of execution of the vector operation instruction.

In the present invention, unlike the prior art, as shown in the explanatory diagram of FIG. 2, a control signal S2 is generated at the beginning of execution of a vector operation instruction (VF instruction), and the contents of the vector index register (VIX) 1 are changed. Second register (SV
IX) 5. After that, the control signal S1 is generated and the vector index register 1 is cleared to zero. When a reason for interrupting the operation such as an interrupt occurs during the execution of the vector operation instruction, the content selector 8 of the second register 5 is used to restore the vector index register 1 and the number n of the operation elements that have already been processed is returned to the content.
Is added by the adder 7, and the addition result is set in the index register 1.

After that, when the processing for the reason for interrupting the operation is completed, the operation is started from the operation element of the operation element number indicated by the contents of the index register 1.

By updating the vector index register by such an operation, it becomes unnecessary to judge whether or not the processing for the reason for interrupting the operation such as an interrupt is completed at the time when the processing for the vector operation instruction is completed.

That is, in the present invention, the vector index register is cleared to zero at the start of execution of the vector operation instruction, and if a reason for interrupting the operation occurs, the contents of the second register are restored to the index register. Therefore, the vector index register can be cleared to zero during the processing of the vector operation instruction. As a result, it is not necessary to provide time for clearing the vector index register to zero before moving to the next vector operation instruction, and it is possible to eliminate the overhead between vector operation instructions, and as shown in FIG. It is possible to move to the execution of vector operation instructions.

It is needless to say that the present invention is not limited to the above-mentioned embodiment and can be modified within the scope of the invention.

[0025]

As described above, according to the present invention,
After saving the contents of the first register to the second register at the beginning of execution of the vector operation instruction, the first register is cleared to zero, and if the reason for operation interruption occurs during the execution of the vector operation instruction, the second operation is executed. Since the contents of the register of No. 1 are restored to the first register and the operation element number to be processed first after the operation is interrupted is recovered, the processing for the reason for interrupting the operation such as the interrupt at the time when the processing for the vector operation instruction is completed. It is no longer necessary to judge whether or not the processing has been completed each time, there is no overhead between vector operation instructions, and the processing cycle per instruction can be shortened, which is an extremely excellent effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the embodiment of the present invention.

FIG. 3 is an explanatory diagram for explaining a conventional problem.

[Explanation of symbols]

1 ... Vector register, 2 ... Vector mask register,
4 ... Vector index register, 5 ... 2nd register, 6 ... Control part, 7 ... Adder, 8 ... Selector.

Front page continued (72) Inventor Fujio Wakui 1 Horiyamashita, Hadano City, Kanagawa Prefecture, Hitachi Computer Engineering Co., Ltd. Within the corporation

Claims (1)

[Claims] 1. When an operation interruption reason such as an interrupt occurs during the vector operation processing of an operation element held in a vector register, the next operation element to be restarted after the processing for the operation interruption reason is completed. In a vector operation processing device having a first register for holding a number, a second register for saving the contents of the first register at the start of vector operation of an operation element held in the vector register; 1st for 2 registers
And a control means for resetting the contents of the second register to the first register when the reason for interrupting the operation is cleared and after the contents of the register are saved. A characteristic vector processing device.