JPH07176626A - 半導体集積回路の形成方法 - Google Patents

半導体集積回路の形成方法

Info

Publication number
JPH07176626A
JPH07176626A JP6287231A JP28723194A JPH07176626A JP H07176626 A JPH07176626 A JP H07176626A JP 6287231 A JP6287231 A JP 6287231A JP 28723194 A JP28723194 A JP 28723194A JP H07176626 A JPH07176626 A JP H07176626A
Authority
JP
Japan
Prior art keywords
layer
conductor layer
conductor
type well
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6287231A
Other languages
English (en)
Japanese (ja)
Inventor
Kuo-Hua Lee
リー クォ−ヒャー
Horng-Dar Lin
リン ホーン−ダー
Ran-Hong Yan
ヤン ラン−ホン
Chen-Hua D Yu
ダグラス ユー チェン−ホァ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of JPH07176626A publication Critical patent/JPH07176626A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP6287231A 1993-10-29 1994-10-28 半導体集積回路の形成方法 Pending JPH07176626A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/145,272 US5468669A (en) 1993-10-29 1993-10-29 Integrated circuit fabrication
US145272 2002-05-14

Publications (1)

Publication Number Publication Date
JPH07176626A true JPH07176626A (ja) 1995-07-14

Family

ID=22512350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6287231A Pending JPH07176626A (ja) 1993-10-29 1994-10-28 半導体集積回路の形成方法

Country Status (5)

Country Link
US (1) US5468669A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0660394A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH07176626A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR950012716A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW286424B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034751A (ja) * 2006-07-31 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550079A (en) * 1995-06-15 1996-08-27 Top Team/Microelectronics Corp. Method for fabricating silicide shunt of dual-gate CMOS device
DE19525069C1 (de) * 1995-07-10 1996-10-24 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
DE19535629C1 (de) * 1995-09-25 1996-09-12 Siemens Ag Verfahren zur Herstellung einer integrierten CMOS-Schaltung
US5759886A (en) * 1995-09-28 1998-06-02 National Semiconductor Corporation Method for forming a layer of metal silicide over the gates of a surface-channel CMOS device
US6150247A (en) * 1996-03-19 2000-11-21 Vanguard International Semiconductor Corporation Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits
KR100240615B1 (ko) * 1997-03-13 2000-01-15 김영환 반도체장치의제조방법
KR100268920B1 (ko) * 1997-04-21 2000-12-01 김영환 반도체소자의제조방법
JP3606515B2 (ja) 2000-09-05 2005-01-05 沖電気工業株式会社 デュアルゲート型ｃｍｏｓ半導体装置及びその製造方法
JP2002217310A (ja) * 2001-01-18 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2005167116A (ja) * 2003-12-05 2005-06-23 Nec Electronics Corp 半導体装置及びその製造方法
US7737500B2 (en) * 2006-04-26 2010-06-15 International Business Machines Corporation CMOS diodes with dual gate conductors, and methods for forming the same
CN104103588B (zh) * 2013-04-10 2017-02-15 上海华虹宏力半导体制造有限公司 Cmos器件的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582068A (ja) * 1981-06-26 1983-01-07 Toshiba Corp 半導体装置およびその製造方法
US4435896A (en) * 1981-12-07 1984-03-13 Bell Telephone Laboratories, Incorporated Method for fabricating complementary field effect transistor devices
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
US4555842A (en) * 1984-03-19 1985-12-03 At&T Bell Laboratories Method of fabricating VLSI CMOS devices having complementary threshold voltages
US4931411A (en) * 1985-05-01 1990-06-05 Texas Instruments Incorporated Integrated circuit process with TiN-gate transistor
JPH0666437B2 (ja) * 1987-11-17 1994-08-24 富士通株式会社 半導体記憶装置及びその製造方法
JPH01265542A (ja) * 1988-04-15 1989-10-23 Toshiba Corp 半導体装置
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH0613472A (ja) * 1992-06-29 1994-01-21 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034751A (ja) * 2006-07-31 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP0660394A1 (en) 1995-06-28
KR950012716A (ko) 1995-05-16
TW286424B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-09-21
US5468669A (en) 1995-11-21

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