JPH0713232Y2 - サーディップ型半導体装置 - Google Patents

サーディップ型半導体装置

Info

Publication number
JPH0713232Y2
JPH0713232Y2 JP10122688U JP10122688U JPH0713232Y2 JP H0713232 Y2 JPH0713232 Y2 JP H0713232Y2 JP 10122688 U JP10122688 U JP 10122688U JP 10122688 U JP10122688 U JP 10122688U JP H0713232 Y2 JPH0713232 Y2 JP H0713232Y2
Authority
JP
Japan
Prior art keywords
recognition
lead
melting point
point glass
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP10122688U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0224556U (US07935154-20110503-C00006.png
Inventor
健二 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP10122688U priority Critical patent/JPH0713232Y2/ja
Publication of JPH0224556U publication Critical patent/JPH0224556U/ja
Application granted granted Critical
Publication of JPH0713232Y2 publication Critical patent/JPH0713232Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP10122688U 1988-07-30 1988-07-30 サーディップ型半導体装置 Expired - Lifetime JPH0713232Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10122688U JPH0713232Y2 (ja) 1988-07-30 1988-07-30 サーディップ型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10122688U JPH0713232Y2 (ja) 1988-07-30 1988-07-30 サーディップ型半導体装置

Publications (2)

Publication Number Publication Date
JPH0224556U JPH0224556U (US07935154-20110503-C00006.png) 1990-02-19
JPH0713232Y2 true JPH0713232Y2 (ja) 1995-03-29

Family

ID=31330028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10122688U Expired - Lifetime JPH0713232Y2 (ja) 1988-07-30 1988-07-30 サーディップ型半導体装置

Country Status (1)

Country Link
JP (1) JPH0713232Y2 (US07935154-20110503-C00006.png)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0723961Y2 (ja) * 1988-10-14 1995-05-31 京セラ株式会社 半導体素子収納用パッケージ
JP2572461Y2 (ja) * 1991-03-15 1998-05-25 ソニー株式会社 サーディップタイプ固体撮像素子のインナーリード形状

Also Published As

Publication number Publication date
JPH0224556U (US07935154-20110503-C00006.png) 1990-02-19

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