JPH07123114B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a structure of a scribe line in a method for manufacturing a semiconductor integrated circuit device.

<< Summary of the Invention >> As shown in FIG. 1 in the semiconductor integrated circuit device, the present invention allows the SiO ₂ film to be present on the scribe line even when the patterning of the passivation film is completed by performing the lymph predeposition on the scribe line, and thereby the chip It is possible to reduce chipping during dicing, and to prevent solder bump formation products from cutting the sputtered film due to Si digging on the scribe line and forming unnecessary solder.

<< Conventional Technology >> As shown in FIG. 2, in the conventional scribe line structure, since the gate oxide film on the scribe line and the gate oxide film in the active region have almost the same thickness, Si is not formed when etching the contact hole. Exposed. Therefore, there was no SiO ₂ on the scribe line even after the patterning of the passivation film.

<< Problems to be solved by the invention >> Therefore, in the conventional scribe line structure, chipping occurs during chip dicing, and Si is exposed in solder bump products, so Si is dug during etching such as plasma SiN passivation. However, the sputtered film for forming bumps is broken, and the bump shape does not become the desired shape, and unnecessary solder is formed.

<< Means for Solving the Problems >> In order to solve the above problems, the present invention forms an oxide film on the N ⁺ diffusion layer having a high surface concentration with a thickness about three times that of other portions. I took advantage of the fact that Rin's predepot was done only on the scribe line.

<< Action >> As described above, since phosphorus was predeposited on the scribe line, it was about 3 times larger than the active region during gate oxidation.
It was possible to form a gate oxide film having a double thickness, and when the etching of the contact hole in the active region was completed, a part of the gate oxide film could be left on the scribe line.

<< Example >> FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device manufactured by the manufacturing method of the present invention.

Embodiments will be described in the order of manufacturing steps with reference to FIGS. Si substrate 31 in a state where formation of P ^- WELL32, N ^- WELL33, formation of Pad oxide film 37, formation of SiN film 38, and formation of LOCOS oxide film 36 which is a field insulating film in the isolation region are completed.
[FIG. 3 (a)] patterned to remove the SiN and SiO ₂ on the scribe line area to resist 40 on the Third Figure (b)]. Then, the resist 40 is removed, and phosphorus is predeposited on the substrate surface in the scribe line region to form a phosphorus predeposition layer 42 which is an N-type impurity region. [FIG. 3 (c)]. Then, SiN 38 and SiO ₂ 37 in the active region are removed and gate oxidation is performed [FIG. 3 (d)]. Next, the gate electrode 48 of POLYSi is formed, the source / drain 46 of the MOS Tr. Is formed,
The intermediate insulating layer 47 is formed [FIG. 3 (e)]. Next, when the contact hole 50 is etched, the monitor is set to the film thickness of the active region, and the etching is stopped when the contact hole in the active region is etched [FIG. 3 (f)]. Next, FIG. 1 is a diagram completed by forming an Al electrode, forming a passivation film and patterning.

<< Effects of the Invention >> As described above, the present invention reduces chipping during chip dicing by adding a simple manufacturing process of performing phosphorus predeposition only on the scribe line, and in the solder bump forming product, the scribe line It is possible to prevent breakage of sputtered film due to Si digging and formation of unnecessary solder.

[Brief description of drawings]

FIG. 1 is a sectional view of a completed state of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a sectional view of a conventional semiconductor integrated circuit device in a completed state. 3A to 3F are cross-sectional views in the order of manufacturing steps of the semiconductor integrated circuit device using the present invention. 1 ... Si substrate, 2 ... P ^- WELL, 3 ... N ^- WELL, 4 ... P
^± field dope, 5 ... N ^± field dope, 6
...... LOCOS oxide film, 7 ・ ・ ・ N ⁺ diffusion layer according to the present invention, 8 ・ ・ ・
… Gate oxide film, 9 …… POLYSi gate electrode, 10 …… MOST
Source or drain of r., 11 ... intermediate insulating layer, 12 ...
… Oxidized oxide film left on the scribe line, 13 ……
Al electrode, 14 ... passivation film, 15 ... center line showing chip edge, 21 ... scribe line with exposed Si,
31 …… Si substrate, 32 …… P ^- WELL, 33 …… N ^- WELL, 34 …… P
^± field dope, 35 …… N ^± field dope, 36
...... LOCOS oxide film, 37 …… Pad oxide film, 38 …… SiN film, 39
…… Center line showing chip edge, 40 …… resist, 41…
… Exposed Si surface, 42 …… Phosphorus predeposition layer, 43 …… Gate oxide film in active area, 44… Gate oxide film on scribe line, high concentration N ⁺ , so about 3 times that on active area A film thickness of 45 ... N ⁺ diffusion layer,
46 …… source or drain of MOSTr., 47 …… intermediate insulating layer, 48 …… POLYSi gate electrode, 49 …… oxide film left on scribe line, 50 …… contact hole.

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit, the surface of a semiconductor substrate of which includes a scribe line region, an active region and a field region, the step of forming a field insulating film in the field region, and a film thickness thinner than the field insulating film. Forming a first thermal oxide film in the scribe line region, forming a second thermal oxide film having a thickness smaller than that of the first thermal oxide film in the active region, and A step of forming an intermediate insulating film on the intermediate layer, and a step of leaving a part of the first thermal oxide film in the scribe line region and removing all of the second thermal oxide film in the active region to be a contact hole. A step of etching the film, the first thermal oxide film and the second thermal oxide film, and the semiconductor through the first thermal oxide film in the scribe line region. The method of manufacturing a semiconductor integrated circuit, characterized in that comprising a step of scribing the substrate. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising a step of introducing N-type impurities into the surface of the scribe line region before forming the first thermal oxide film. Method. 3. The method of manufacturing a semiconductor integrated circuit according to claim 1, further comprising a solder bump forming step.