JPH07111253A - シリサイド形成方法および半導体装置の製造方法 - Google Patents

シリサイド形成方法および半導体装置の製造方法

Info

Publication number
JPH07111253A
JPH07111253A JP6039457A JP3945794A JPH07111253A JP H07111253 A JPH07111253 A JP H07111253A JP 6039457 A JP6039457 A JP 6039457A JP 3945794 A JP3945794 A JP 3945794A JP H07111253 A JPH07111253 A JP H07111253A
Authority
JP
Japan
Prior art keywords
film
forming
silicide
semiconductor device
reaction chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6039457A
Other languages
English (en)
Japanese (ja)
Inventor
Takeshi Suwa
剛 諏訪
Osamu Kasahara
修 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6039457A priority Critical patent/JPH07111253A/ja
Priority to TW083104717A priority patent/TW291577B/zh
Priority to KR1019940020073A priority patent/KR950006968A/ko
Publication of JPH07111253A publication Critical patent/JPH07111253A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP6039457A 1993-08-20 1994-03-10 シリサイド形成方法および半導体装置の製造方法 Pending JPH07111253A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6039457A JPH07111253A (ja) 1993-08-20 1994-03-10 シリサイド形成方法および半導体装置の製造方法
TW083104717A TW291577B (enrdf_load_stackoverflow) 1993-08-20 1994-05-24
KR1019940020073A KR950006968A (ko) 1993-08-20 1994-08-16 실리사이드 형성방법 및 반도체장치의 제조방법

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP5-206387 1993-08-20
JP20638793 1993-08-20
JP6039457A JPH07111253A (ja) 1993-08-20 1994-03-10 シリサイド形成方法および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH07111253A true JPH07111253A (ja) 1995-04-25

Family

ID=26378851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6039457A Pending JPH07111253A (ja) 1993-08-20 1994-03-10 シリサイド形成方法および半導体装置の製造方法

Country Status (3)

Country Link
JP (1) JPH07111253A (enrdf_load_stackoverflow)
KR (1) KR950006968A (enrdf_load_stackoverflow)
TW (1) TW291577B (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11200050A (ja) * 1998-01-14 1999-07-27 Mitsubishi Electric Corp タングステンシリサイド膜の形成方法、半導体装置の製造方法、及び半導体ウェーハ処理装置
US6498095B2 (en) 1998-03-16 2002-12-24 Nec Corporation Cvd method for producing an interconnection film by depositing a lower layer to fill a recess performing a cleaning step to remove dissociated reactant gas, and consequently depositing an upper layer that has a smaller impurity concentration than the lower layer
KR100659918B1 (ko) * 1998-12-14 2006-12-21 프리스케일 세미컨덕터, 인크. 반응 물질들의 유입을 변경시킴으로써 증착된 층을 가지는 반도체 디바이스를 형성하는 방법
US7189659B2 (en) 2002-11-15 2007-03-13 Fujitsu Limited Method for fabricating a semiconductor device
JP2008187190A (ja) * 2008-02-21 2008-08-14 Renesas Technology Corp タングステンシリサイド膜の形成方法及び半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11200050A (ja) * 1998-01-14 1999-07-27 Mitsubishi Electric Corp タングステンシリサイド膜の形成方法、半導体装置の製造方法、及び半導体ウェーハ処理装置
US6498095B2 (en) 1998-03-16 2002-12-24 Nec Corporation Cvd method for producing an interconnection film by depositing a lower layer to fill a recess performing a cleaning step to remove dissociated reactant gas, and consequently depositing an upper layer that has a smaller impurity concentration than the lower layer
KR100659918B1 (ko) * 1998-12-14 2006-12-21 프리스케일 세미컨덕터, 인크. 반응 물질들의 유입을 변경시킴으로써 증착된 층을 가지는 반도체 디바이스를 형성하는 방법
US7189659B2 (en) 2002-11-15 2007-03-13 Fujitsu Limited Method for fabricating a semiconductor device
JP2008187190A (ja) * 2008-02-21 2008-08-14 Renesas Technology Corp タングステンシリサイド膜の形成方法及び半導体装置の製造方法

Also Published As

Publication number Publication date
KR950006968A (ko) 1995-03-21
TW291577B (enrdf_load_stackoverflow) 1996-11-21

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