JPH07105440B2 - 絶縁された単結晶シリコンアイランドの製法 - Google Patents

絶縁された単結晶シリコンアイランドの製法

Info

Publication number
JPH07105440B2
JPH07105440B2 JP3504178A JP50417891A JPH07105440B2 JP H07105440 B2 JPH07105440 B2 JP H07105440B2 JP 3504178 A JP3504178 A JP 3504178A JP 50417891 A JP50417891 A JP 50417891A JP H07105440 B2 JPH07105440 B2 JP H07105440B2
Authority
JP
Japan
Prior art keywords
layer
groove
silicon
single crystal
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3504178A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05506749A (ja
Inventor
ホルガー フォークト
Original Assignee
フラウンホーファー・ゲゼルシャフト ツア フェルデルンク デル アンゲワンテン フォルシュンク アインゲトラーゲナー フェライン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by フラウンホーファー・ゲゼルシャフト ツア フェルデルンク デル アンゲワンテン フォルシュンク アインゲトラーゲナー フェライン filed Critical フラウンホーファー・ゲゼルシャフト ツア フェルデルンク デル アンゲワンテン フォルシュンク アインゲトラーゲナー フェライン
Publication of JPH05506749A publication Critical patent/JPH05506749A/ja
Publication of JPH07105440B2 publication Critical patent/JPH07105440B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H10P30/209—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
JP3504178A 1990-02-27 1991-02-26 絶縁された単結晶シリコンアイランドの製法 Expired - Lifetime JPH07105440B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4006158.2 1990-02-27
DE4006158A DE4006158A1 (de) 1990-02-27 1990-02-27 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel
PCT/DE1991/000162 WO1991013463A1 (de) 1990-02-27 1991-02-26 Verfahren zum erzeugen einer isolierten, einkristallinen siliziuminsel

Publications (2)

Publication Number Publication Date
JPH05506749A JPH05506749A (ja) 1993-09-30
JPH07105440B2 true JPH07105440B2 (ja) 1995-11-13

Family

ID=6401063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3504178A Expired - Lifetime JPH07105440B2 (ja) 1990-02-27 1991-02-26 絶縁された単結晶シリコンアイランドの製法

Country Status (4)

Country Link
EP (1) EP0517727B1 (https=)
JP (1) JPH07105440B2 (https=)
DE (2) DE4006158A1 (https=)
WO (1) WO1991013463A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4201910C2 (de) * 1991-11-29 1995-05-11 Fraunhofer Ges Forschung Verfahren zum Herstellen einer Halbleiterstruktur für eine integrierte Leistungsschaltung mit einem vertikalen Leistungsbauelement
US5457068A (en) * 1992-11-30 1995-10-10 Texas Instruments Incorporated Monolithic integration of microwave silicon devices and low loss transmission lines
GB2327146A (en) * 1997-07-10 1999-01-13 Ericsson Telefon Ab L M Thermal insulation of integrated circuit components
DE102010028044B4 (de) * 2010-04-21 2017-08-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Drucksensor und Verfahren zu dessen Herstellung
DE102017212437B3 (de) 2017-07-20 2018-12-20 Infineon Technologies Ag Verfahren zum Herstellen einer vergrabenen Hohlraumstruktur

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62266875A (ja) * 1986-05-14 1987-11-19 Nippon Denso Co Ltd 半導体圧力センサ
JPS6467935A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Manufacture of semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
DE2451861A1 (de) * 1973-11-02 1975-05-15 Hitachi Ltd Integrierte halbleiterschaltungsbauelemente
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
KR910009318B1 (ko) * 1987-09-08 1991-11-09 미쓰비시 뎅끼 가부시기가이샤 반도체 장치의 제조 및 고내압 파묻음 절연막 형성방법
JPH01185936A (ja) * 1988-01-21 1989-07-25 Fujitsu Ltd 半導体装置
JP2788269B2 (ja) * 1988-02-08 1998-08-20 株式会社東芝 半導体装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62266875A (ja) * 1986-05-14 1987-11-19 Nippon Denso Co Ltd 半導体圧力センサ
JPS6467935A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH05506749A (ja) 1993-09-30
WO1991013463A1 (de) 1991-09-05
DE59103366D1 (de) 1994-12-01
DE4006158A1 (de) 1991-09-12
EP0517727B1 (de) 1994-10-26
EP0517727A1 (de) 1992-12-16
DE4006158C2 (https=) 1992-03-12

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