JPH0695852A - Serial multiplier with adding function - Google Patents

Abstract

PURPOSE:To make also an addition arithmetic operation possible to be carried out by feedback-processing an output signal before one clock without operating a bit shift in a serial amplifier, and fixing a coefficient data input to 1. CONSTITUTION:Data 1 to be inputted in parallel and coefficient data 2 to be serially inputted by an LSB first are multiplied in parallel one bit by a one bit multiplier 4, and the multiplied result is added to a signal obtained by one bit-shifting and feedback-processing the entire outputs before one clock by a full adder 5. Then, a function which fixes the coefficient data to '1' and a function which feedback-operates the entire output data before one clock without shifting the data are added to the serial multiplier which delays the output of the full adder 5 by one clock by a register, so that the addition arithmetic operation can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit and an arithmetic circuit for multiplying or adding input parallel data.

[0002]

2. Description of the Related Art In recent years, with the integration of digital signal processing circuits, the processing capacity and circuit configuration of arithmetic circuits that perform various processes on input data have become major factors in determining the overall circuit scale.

The structure of a conventional arithmetic circuit will be described below with reference to the drawings. First, FIG. 3 shows a configuration of a conventional serial multiplication circuit. In FIG. 3, 4 is a 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data 1 (D3, D2, D1, D0) and 1-bit coefficient data 2 (K3, K2, K1, K0), and 5 is a serial A full adder for adding a signal obtained by feeding back the output of the entire multiplier one clock before and an output of the 1-bit multiplier 4 is an output register 6 for latching the output of the full adder 5 by a clock signal 9.
Further, a clear circuit 7 resets the feedback signal to all zeros by the clear signal 8.

The operation of the conventional serial multiplier configured as described above will be described below. FIG. 4 shows the timing of each signal. The input parallel data 1 holds the same value for 4 clocks of the clock signal 9, and the 1-bit coefficient data 2 is LSB first and the clock signal 9 is 1
Data is input serially for each clock. First, in the first clock, the clear signal 8 becomes low level in synchronization with the clock signal 9, and the feedback signal 10
Is reset to all zeros. At the same time, the data D3 (1) input from the input parallel data 1
The 1-bit multiplier 4 outputs the result of parallel 1-bit multiplication of D 0 (1) and K 0 (1) which is the LSB of the coefficient data input from the 1-bit coefficient data 2.

Since the output of the clear circuit 7 is zero, the output of the 1-bit multiplier 4 becomes the output of the full adder 5 as it is. At this time, the carry input of the least significant bit of full adder 5 is set to "0" as shown in FIG. And carry output 1 of the full adder 5
The bits and the upper 3 bits of the sum output are latched by the output register 6, and the parallel data output 3 is directly fed back as the feedback signal 10. Since the clear signal 8 becomes high level at the second clock, the feedback signal 10 is input to the full adder 5 in a form in which the output of the full adder 5 one clock before is shifted in the LSB direction by 1 bit. In the 1-bit multiplier 4, the input data D3 (1) to D0 (1) and the coefficient data K1 (1) are multiplied in parallel by 1 bit, and the feedback signal 10 and the output of the 1-bit multiplier 4 in the full adder 5 are obtained. Is added and the addition result is latched again in the output register 6. Further, the same operation is repeated while changing the value of the 1-bit coefficient data 2 every clock, and the output parallel data 3 at the fifth clock is D3 (1) to D0 (1) and K3 (1) to K0 (1). It is the multiplication result (upper 4 bits).

Next, the configurations of the conventional adder and subtractor are shown in FIGS. 5 (a) and 5 (b). The full adder 5 and the output register 6 in FIG. 5 are the same as those in FIG. Reference numeral 11 is an inverter for inverting each bit of the inputs B3 to B0. In the adder shown in FIG. 5A, the carry input of the least significant bit of the full adder 5 is set to "0", and the inputs A3 to A0 and the input B3 are set.
By inputting ~ B0 into the full adder 5, both are added. Then, after that, the addition result is latched by the output register 6 in synchronization with the clock signal 9. Further, in the case of the subtracter shown in FIG. 5B, the carry input of the least significant bit of the full adder 5 is set to "1", and the input B3 to B0 are bit-inverted by the inverter 11 and the input A3 to A0. Is added with full adder 5. As a result, the inputs B3 to B0 are subtracted from the inputs A3 to A0. Then, the subtraction result is latched by the output register 6 in synchronization with the clock signal 9.

[0007]

However, in the above-mentioned configuration, different arithmetic circuits are required depending on the type of operation. Further, when outputting the operation result to the same data bus, a transfer gate or a selector is required at the output section of each operation circuit in order to prevent the output signals of each operation circuit from colliding with each other. Therefore, there is a problem that the circuit scale becomes very large especially when the number of bits of the input parallel data is large.

The present invention has been made to solve the above-mentioned conventional problems, and has been made with the object of reducing the circuit scale by performing various arithmetic processes in one arithmetic circuit.

[0009]

In order to solve the above problems, a serial multiplier with an addition function according to the present invention comprises a 1-bit multiplier for performing parallel 1-bit multiplication between input parallel data and 1-bit coefficient data, and a serial A clear circuit that resets the parallel feedback signal from the output parallel data of the entire multiplier to zero, a full adder that adds the output of the 1-bit multiplier and the clear circuit, and an output register that delays the output of the full adder by one clock. , A selector for switching between returning the output of the register by 1 bit for feedback and for returning without shifting, 1-bit coefficient data is serially input every clock at LSB first during multiplication, and the register The output parallel data of the entire serial multiplier, which is the output of, is shifted 1 bit to the MSB side. The input parallel data and the 1-bit coefficient data are serially multiplied by the feedback, and the 1-bit coefficient data is fixed to "1" at the time of addition, and the output parallel data of the entire serial multiplier is not shifted. By feeding back to the output register, the addition operation of the value stored in the output register and the input parallel data is performed.

[0010]

With the above-described structure, the present invention can also serve as a full adder and an output register, which are required separately for each arithmetic circuit in the conventional arithmetic circuit. Further, since the number of outputs as the arithmetic circuit is one, the transfer gate and the selector are not required unlike the conventional case when outputting the arithmetic result to the data bus. Therefore, especially when the number of bits of input parallel data is large, the circuit scale can be significantly reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A serial multiplier with an addition function of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a serial multiplier with an addition function according to an embodiment of the present invention. In FIG. 1, a 1-bit multiplier 4, a full adder 5,
The output register 6 and the clear circuit 7 are the same as those shown in FIG. Further, 12 is an EX-OR gate for rotating the input parallel data 1 normally or inverted and inputting it to the 1-bit multiplier 4, 13 is a first switch for switching between normal rotation and inversion of the EX-OR gate, 14 Is a second switch for switching the input of the 1-bit multiplier 4 to the 1-bit coefficient data 2 or "1" or "0", 1
5 is a third switch for switching the carry input of the least significant bit of the full adder 5 to "0" or "1", and 16 is to return the output of the output register 6 without shifting or by shifting it by 1 bit. Is a fourth switch for switching between. Further, 17 is an OR gate for setting a specific bit in the feedback signal cleared by the clear circuit 7, and is controlled by the set signal 18. Output parallel data 3 (S3 to S0), which is the output of the entire serial multiplier with the addition function
Becomes an output signal of the fourth switch 16.

The operation of the serial multiplier with the addition function of the present invention having the above-described structure will be described below. First, when serial multiplication is performed first, the first switch 13 is fixed to "0" and the second switch 14 is set to "1".
The third switch 15 is fixed to "0", and the fourth switch 16 is moved to the side for shifting 1 bit, to the bit coefficient data 2 side. By setting in this way, the serial multiplier with an addition function according to the present invention shown in FIG.
This is exactly the same as the conventional serial multiplication circuit shown in FIG. Therefore, the operation timing is also exactly the same as the timing chart shown in FIG. In addition, in FIG.
As in the conventional example, in order to clear the feedback signal 10 to all zero before starting the calculation, the set signal 18 may be fixed to zero. However, the serial multiplier with the addition function according to the present invention can add a certain value in advance to the value obtained as a result of multiplication by setting a specific bit after clearing all of the feedback signal 10. is there. In FIG. 1, a signal obtained by inverting the clear signal 8 is added as a set signal 18 to set "1" as an initial value.
The value such as "000B" is added. By this processing, the bits after the decimal point can be rounded by rounding operation in the finally obtained multiplication result.

Next, the case of performing the addition operation will be described with reference to the timing chart shown in FIG. First, the first switch 13 is first fixed to "0", the second switch 14 is fixed to "1", and the third switch 15 is set to "0".
Fixed to. Then, the fourth switch 16 is tilted to the non-shifting side. As a result, the input parallel data 1 "D
(1) ”will be input to the full adder 5 as it is. Then, the clear signal 8 and the set signal 18 are set to the low level at the first first clock, the feedback signal 10 is reset to all zeros, and is input to the full adder 5. As a result, the output of the full adder 5 becomes the input parallel data 1 "D
(1) ”, and the input parallel data 1 to be added at the next clock is stored in the output register 6. Then, by setting the clear signal 8 to the high level at the second clock, the data previously stored in the output register 6 is fed back as it is and added to the data "D (2)" newly added from the input parallel data 1. , Addition result “D
(1) + D (2) "is latched in the output register 6 and output at the third clock.

When subtraction is performed, first, the input parallel data 1 "D (3)" is input in the same procedure as in the case of addition.
Is stored in the output register 6. At the second clock, the clear signal 8 is set to high level, and at the same time, the first switch 13 is set to "1" to input the parallel data 1 "D (4)".
Bit invert. Further, the carry input “+1” is added to the full adder 5 by setting the third switch 15 to “1”. As a result, the input parallel data 1 is newly added from the data “D (3)” initially stored in the output register 6.
The added data "D (4)" is subtracted, and the subtraction result "D (3) -D" is output to the output register 6 at the third clock.
(4) ”is latched and output.

Further, the second switch 14 is set to "0" to clear the input parallel data 1 to all zeros, the third switch 15 is fixed to "0" and the fourth switch 16 is fixed to the non-shift side, and a clear signal is given. It is also possible to hold the data "D (3) -D (4)" stored in the output register 6 by setting 8 to high level and the set signal 18 to low level.

When the addition / subtraction operation is continuously performed after the serial multiplication is completed, it is not necessary to store the input parallel data 1 in the output register 6 at the first clock. That is, if the second switch operation in the addition or subtraction operation is performed while the fourth switch 16 is turned to the side that shifts by 1 bit, the addition / subtraction operation of the multiplication result and the input parallel data 1 is performed in one clock. Can be done.

[0017]

As described above, the serial multiplier with the addition function of the present invention is a 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data and 1-bit coefficient data,
A clear circuit for resetting the parallel feedback signal from the output parallel data of the entire serial multiplier to zero;
A full adder that adds the output of the bit multiplier and the clear circuit, an output register that delays the output of the full adder by 1 clock, and a switch between the feedback of the output of the register by 1 bit and the feedback without shifting A selector, and serially inputs 1-bit coefficient data every LSB first at the time of multiplication, and outputs the output parallel data of the entire serial multiplier, which is the output of the register, to the MSB side by 1-bit and returns it. Therefore, the input parallel data and the 1-bit coefficient data are serially multiplied, the 1-bit coefficient data is fixed to "1" at the time of addition, and the output parallel data of the entire serial multiplier is fed back without being shifted. By
By performing the addition operation of the value stored in the output register and the input parallel data, it is possible to use the full adder and the output register separately required for each operation circuit in the conventional operation circuit. Since there is only one output as the arithmetic circuit, a transfer gate and a selector are not required when outputting the arithmetic result to the data bus as in the conventional case. Therefore, especially when the number of bits of the input parallel data is large, there is an effect that the circuit scale can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a serial multiplier with an addition function according to an embodiment of the present invention.

FIG. 2 is a diagram showing the timing of a serial multiplier with an addition function of the present invention.

FIG. 3 is a configuration diagram of a conventional serial multiplier.

FIG. 4 is a diagram showing a timing of a conventional serial multiplier.

5A is a configuration diagram of a conventional adder, and FIG. 5B is a configuration diagram of a conventional subtractor.

[Explanation of symbols]

 4 1-bit Multiplier 5 Full Adder 6 Output Register 7 Clear Circuit 11 Inverter 12 EX-OR Gate 13 First Switch 14 Second Switch 15 Third Switch 16 Fourth Switch 17 OR Gate

Claims (4)

[Claims] 1. A 1-bit multiplier for performing parallel 1-bit multiplication of input parallel data and 1-bit coefficient data, a clear circuit for resetting a parallel feedback signal from output parallel data of the entire serial multiplier to zero, and A full adder that adds the 1-bit multiplier and the output of the clear circuit, an output register that delays the output of the full adder by 1 clock, and a feedback of whether the output of the register is shifted by 1 bit or returned without shifting A selector for switching, 1-bit coefficient data is serially input every clock at LSB first during multiplication, and the output parallel data of the entire serial multiplier, which is the output of the register, is shifted by 1 bit to the MSB side and fed back. By doing so, serial multiplication of the input parallel data and the 1-bit coefficient data is performed. In addition, at the time of addition, the 1-bit coefficient data is fixed to "1" and the output parallel data of the entire serial multiplier is fed back without being shifted, so that the value stored in the output register and the input parallel data are A serial multiplier with an addition function characterized by performing addition operations. 2. An EX-OR gate or the like is used to switch between inputting the input parallel data to the 1-bit multiplier as it is or inverting all bits and then inputting, and carrying the least significant bit of the full adder. Input "0"
The serial multiplier with an addition function according to claim 1, wherein the subtraction operation can be performed in addition to the serial multiplication and the addition operation by switching between "1" and "1". 3. The clear circuit is provided with a function of setting a feedback signal to all zeros as well as a function of setting it to a specific value, and an addition operation of the input parallel data and a specific value is also possible. The serial multiplier with an addition function according to claim 1, characterized in that. 4. The value stored in the output register is held by fixing the 1-bit coefficient data to "0" and feeding back the output parallel data of the entire serial multiplier without shifting. The serial multiplier with an addition function according to claim 1, wherein