JPH05257649A - Serial multiplier - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a serial multiplier that multiplies numerical values expressed in two's complement format, even if the numerical range of the multiplier (data) to be handled is expanded to the maximum range that can be represented by the number of bits,
The purpose is to obtain a correct multiplication result. [Structure] The sign bit addition unit 4 is provided in all modules that generate partial sums up to each digit of a multiplier. The sign bit adding unit 4 latches the MSB of the multiplicand and the next bit, detects the difference between the MSB of the multiplicand and the next bit by the two exclusive OR logics, and controls the selector with the detection signal to control the partial operation. Only the MSB of the sum data is added with the sign bit of the held multiplicand data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial multiplier for multiplying two numerical values represented in a two's complement form by bit serial to obtain a product.

In a digital filter or the like, it is necessary to multiply a numerical value represented by a binary number consisting of a predetermined number of bits of data that is serially input by a similarly input coefficient. The serial multiplier path used for this often handles data (multiplicand) and coefficients (multiplier) in two's complement format.
In the adder for generating the partial sum that constitutes the multiplier,
Sign extension processing is performed on the most significant bit of data in serial operation, but in this case, restrictions are imposed on the data to be handled.

[0003]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional serial multiplier, FIG. 5 is a block diagram of the basic module of FIG. 4, FIG. 6 is a block diagram of a full adder, and FIG. Is.

Each of the serial multipliers of FIG. 4 represents a product of a 6-bit multiplicand (data) and a 6-bit multiplier (coefficient) which are expressed in 2's complement format and are serially input from the LSB, and output the product. Circuit. This calculation is performed by multiplying the multiplicand by one digit of the multiplier for each digit of the multiplier in order from the lower digit of the multiplier, shifting the result, and adding the result to obtain the partial sum of the products.

In FIG. 4, 1 is a first stage module, 2-1
2 to 3 are basic modules, and 3 is a final stage module, all of which are modules for obtaining a partial sum of products up to a certain digit of the multiplier, and are connected in cascade in this order.

Details of the basic module in the prior art shown in FIG. 4 will be described with reference to FIG. The data, the coefficient, and the partial sum of the product from the previous stage are input to this module, and the value obtained by multiplying the data by the specific digit (k digit) of the coefficient is used to calculate the partial sum of the product up to the previous stage (that is, 0 digit of the coefficient). To k-1 digits to the data and the partial sum of products up to k digits is obtained,
Further, the partial sum is preceded by one bit clock with respect to the multiplicand (data), and the digit is moved right by one digit to be output.

For data input, 6-bit data (multiplicand) is input in order from LSB. Similarly to the coefficient input, a 6-bit coefficient (multiplier) is sequentially input from the LSB. DA is a D flip-flop operated by a bit clock synchronized with the bit of the data input, and delays the data by one clock.

DB is a D flip-flop for taking out the bit of the k-th digit from the multiplier, and takes in the bit of the k-th digit of the coefficient by a word clock having a cycle of n times the bit clock (the number of data digits) and holds it for one word time length. To do. Then, AND1 is controlled by the k-digit value of the held multiplier, and if the k-digit bit is 1, the input data (multiplicand) is unchanged, and if it is 0, 0 continuous is output to the adder input A of the full adder ADD. By doing so, the multiplicand is multiplied by the k-th digit multiplier.

DC is a D flip-flop for bit expansion, which captures data with an expansion clock T2 that rises at the MSB timing of partial sum data up to k-1 digit of the multiplier input from the previous stage and continues for a 2-bit clock width. By rewriting the LSB of the next word with the value of the MSB bit of the partial sum data from the previous stage to make a new MSB, and shifting the partial sum by one digit in the lower direction by advancing the data by 1 bit. , To the augend input B of the full adder ADD.

ADD is a full adder, and as shown in detail in FIG. 6, a D flip-flop FF1 and two EX-OR gates.
G20, G21, three AND gates G22 to G24, one OR
It is composed of a gate G25 and adds the data input to A and B bit by bit, and outputs the addition result from the Σ terminal and the carry from the Co terminal, respectively. The Co output is delayed by one bit clock through a delay circuit DA composed of a D flip prop FF2 and carried, and is re-input to the Ci terminal to be added simultaneously when the next digit is added.

The first-stage module 1 in FIG. 4 obtains a partial sum up to the second digit of the multiplier. A multiplier circuit for the first digit of the multiplier is provided in front of the basic module for generating the partial sum for the second digit. It is added.

The final stage module 3 is the multiplier MSB.
Is a part for multiplying the sign digit, and when the multiplier is positive, the multiplicand multiplied by 0 is all 0, so
10000 with 111110 and carry 1 in the second lower digit
00 is added, and the partial sum up to the first digit remains unchanged and is output as a positive product. When the multiplier is negative, the multiplicand is bit-inverted, but 2 of the multiplicand obtained by adding 1 to the LSB is used.
By adding the complement of to the partial sum up to the first digit, 2
This is the part that outputs the negative product of the complement expression of. Note that Tz
Is a level signal of "0" only for the timing of the LSB of the data and "1" at other times.

[0013]

In the conventional serial multiplier described above, when the partial sum of the products up to a certain digit of the multiplier is moved by one bit to generate the partial sum with the multiplication result of the next digit of the coefficient. , The most significant digit of the augend is generated by bit extension in order to match the digit of the augend with the number of digits of the addend (k digit of coefficient and partial product of data). At this time, when handling a multiplicand in which the value of the MSB bit and the value of the next significant bit are different, the most significant digit of the numerical value obtained as the partial sum up to a certain digit of the multiplier is different from the value of the sign bit of the multiplicand. There is. When such a partial sum is digit-shifted by bit extension to generate the augend, the numerical value changes and an error occurs in the multiplication result.

This will be described with reference to the calculation example of FIG. Figure 3
Indicates the progress of the multiplication by the above-mentioned serial multiplication circuit in which the multiplier (coefficient) and the multiplicand (data) are both 6 bits, and the multiplicand is 0.11100 (= + 0.87).
5) is larger than 0.5 (that is, a number different from the next significant bit of the sign bit), and the multiplier is 00.0111 (= + 0.
4375) and the product is 0.01100 (= + 0.375≈correction = 0.3828125). b ₀ ~b
₅ is a partial product of the data and 1 bit of coefficient and is a full adder ADD
The bit string to be input to the augend terminal A of D _{0 to} D ₄ is moved by one digit by advancing the partial sum of the products up to the preceding stage by 1 bit with respect to the data, and is input to the addend terminal B of ADD. Σ is a carry for adding a partial sum to be output to the next-stage module for Σ ₀ to Σ ₄ , and Ci is a carry for adding because 0 is the product of the multiplier and the sign bit of the multiplier in the final-stage module. The final calculation results are shown.

The partial sum output up to the second digit of the multiplier by the first-stage module is 101010. When this is moved to the right by one digit and the digit is moved to the partial product of the next digit, a sign bit is added. Since it is performed by bit extension, the sign bit of the partial sum, which should originally be 0, becomes 1. Therefore, the product output is 0.0000 (= 0.125), and the correct operation is not performed.

In order to avoid this, the number of digits of the data is limited by one digit so that the second bit of the multiplicand (data) has the same value as the MSB. For example, with 6 bits, 1>M> 1 would be the case.
It is necessary to limit the multiplicand M that can represent the range of 0.5 to the range of 0.5>M> −0.5, or to prevent overflow at the final stage of the digital filter when 1>M> −1.

Therefore, the conventional technique has a problem that the circuit scale is increased or the range of data that can be handled is limited. The present invention was created in view of the above problems, and an object thereof is to provide a serial multiplier that can obtain a correct multiplication result even if the range of the multiplicand to be handled is expanded to the maximum range that can be represented by the number of bits.

[0018]

FIG. 1 is a diagram showing a basic module for generating a partial sum of products used in a serial multiplier according to the present invention.

In order to solve the above problems, the serial multiplier of the present invention is applied to all modules (1, 2-1 to 2-3, 3 in FIG. 4) that generate partial sums up to each digit of the multiplier. The sign bit adding unit 4 shown in FIG. 1 is provided. The sign bit adding unit 4 latches the MSB of the multiplicand and the next bit, detects the difference between the MSB of the multiplicand and the next bit by the two exclusive OR logics, and controls the selector with the detection signal to control the partial operation. Only the MSB of the sum data is added with the sign bit of the held multiplicand data.

[0020]

When the high-order 2 bits of the multiplicand have the same sign, the sign bit of the multiplicand is forcibly inserted into the bit after the partial sum from the preceding stage, so that the partial sum is always bit-extended correctly. It is possible to perform multiplication correctly up to the maximum range that can be represented. Therefore, when applied to a digital filter, it is not necessary to take measures against overflow, and the circuit scale can be reduced.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a basic module for generating a partial sum of products used in a serial multiplier of the present invention, FIG. 2 is a detailed diagram of a sign bit adding section, and FIG. 3 is a diagram showing an example of operation according to the present invention.
The same reference numerals denote the same objects throughout the drawings.

The feature of the present invention resides in that each of the modules 1, 2-1 to 2-3, and 3 at each stage for generating the partial sum of the products shown in FIG. The sign bit adding unit 4 is provided between the Dc and the full adder ADD, and the other points are the same as in the conventional example described above with reference to FIGS.

In FIG. 1, the basic module is representatively used in the intermediate stage, but the configuration and operation of the sign bit adding unit 4 are the same in both the initial stage module and the final stage module. In FIG. 1, the sign bit addition unit 4 includes a control unit 41 and a selector 42, and is provided between the bit extension D flip-flop Dc and the full adder ADD.

The partial sum data of the products from the preceding-stage module passes through the bit extension D flip-flop Dc and is sent to the MS.
The value of the B-1th bit is expanded to generate and output the MSB.

Multiplicand data is input to the control unit 41 to generate a B input signal and a switching control signal for the selector 41, and the selector 41 selectively outputs the B input signal at a predetermined timing according to the switching control signal.

The control unit 41 holds the MSB of the multiplicand data and the upper 2 bits of the next bit, outputs the MSB to the B input to the selector 41, and checks the difference between the values of the upper 2 bits. If the values are different, M of partial sum data
At the timing of SB, the selector 42 controls so as to select the B input for one bit long time. When the values of the upper 2 bits are the same, the partial sum data to which the MSB is added is input to the addend terminal B of the full adder ADD as it is through the bit extension D flip-flop Dc. When the values of the upper two bits of the multiplicand are different, the MSB of the partial sum data after passing through the bit expansion D flip-flop Dc is replaced by the sign bit of the multiplicand and is input to the addend data terminal B of the full adder ADD. ..

The details of the sign bit adding section will be described with reference to FIG. The control unit 41 includes a shift register 41a, an EX-OR gate 41b, and an AND gate 41c.

The shift register 41a is a 2-bit serial input parallel output shift register, and the MSB of the input data (multiplicand) within one word period of the input data (multiplicand).
The higher-order 2 bits of the input data are latched in advance by the clock T2 which rises twice at the timing of the −1st bit and the MSB. Then, Q1 which is the value of the MSB is output to the B input of the selector 41. In the EX-OR gate 41b,
The Q1 and Q2 outputs of the shift register 41a, that is, the values of the upper 2 bits of the latched data are input. The EX-OR gate 41b outputs 1 when the values of the upper 2 bits are different. Since the clock T3 that becomes "1" only at the timing of the MSB of the partial sum data is input to the AND gate 41c, the switching control signal S becomes "1" only at this timing, and the selector 42 sets the MSB1 bit of the partial sum data. For minute, B input is selectively output. Selector 42 otherwise
Selects the A input which is the output of the bit extension D flip-flop Dc (FF2). When the upper two bits of the multiplicand are equal to each other by the above bit adding unit, the value of the sign bit of the multiplicand is forcibly inserted as MSB in the partial sum data from the preceding module, so that the MSB of the input data and the next Even if the value of the place bit is different, an operation error does not occur in the partial sum generation process, and the data range can be widened.

FIG. 3 shows an arithmetic process in the serial multiplier of the present invention for the same multiplier and multiplicand as in FIG. Since the value of the sign bit of the multiplicand and the value of the next significant bit are different, the sign bit addition unit operates in each stage of the partial sum generation module to add the sign bit of the multiplicand to the partial sum data to perform digit movement. ..

Partial sum data Σ ₁ up to the second digit of the multiplier and 3
With partial sum data Σ ₂ up to the digit Has the most significant bit of 1, but since the sign bit 0 is correctly inserted in the MSB when the data is digit-shifted to generate D1 and D2,
It shows that a correct calculation result of Σ = 0.01100 is obtained.

[0031]

As described above, according to the present invention, it is possible to provide a serial multiplier capable of operating over a wide data range, and a digital filter using this multiplier can reduce the overflow detection circuit. effective.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic module for generating a partial sum of products used in a serial multiplier of the present invention.

FIG. 2 is a detailed diagram of a sign bit addition unit.

FIG. 3 is a diagram showing a calculation example according to the present invention.

FIG. 4 is a block diagram of a conventional serial multiplier.

5 is a block diagram of the basic module of FIG.

FIG. 6 is a block diagram of a full adder

FIG. 7 is a diagram showing a calculation example in a conventional technique.

[Explanation of symbols]

1 ... First stage module, 2-1 to 2-3 ... Basic module, 3
... final stage module, 4 ... Sign bit addition unit, 41 ... Control unit, 42 ... Selector, Dc ... Bit extension D flip-flop

Claims (2)

[Claims] 1. A multiplicand and a multiplier represented in a two's complement format to be serially input are moved from a lower digit to an upper digit of the multiplier while moving a digit by a partial product obtained by multiplying the multiplicand by each digit of the multiplier. In a serial multiplier that multiplies by cumulatively adding to obtain a partial sum of products, if the most significant bit and the next most significant bit of the multiplier are different, the sign bit of the sign bit to be added as MSB to the partial sum that moves is shifted. A serial multiplier characterized in that a value of a sign bit of a multiplicand is used as a value. 2. The addition of the sign bit is performed by the multiplicand MS.
B and the next-order bit are latched, the difference between the MSB of the multiplicand and the next-order bit is detected by the exclusive-OR logic of the two bits, and the selector is controlled by the detection signal to control the partial-sum MS.
The serial multiplier according to claim 1, wherein a sign bit is added only to B.