JPH0381174B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to an arithmetic device, and particularly to an arithmetic device having a circuit for converting fixed point numbers to floating point numbers and from floating point numbers to fixed point numbers.

(Prior art) Generally, a negative number in a fixed-point number is represented by a binary complement, and a negative number in a floating-point number is represented by its absolute value and a sign bit representing the negative number. When converting from a floating point number to a fixed point number, the conversion from a negative fixed point number (binary complement) to a positive fixed point number with the same absolute value, and this It is necessary to convert the opposite positive fixed-point number to a negative fixed-point number with the same absolute value.

In order to do this, in the prior art, as will be explained in detail later, an inverting circuit with a control function and an A+1
This is done using an arithmetic circuit (1 adder circuit).

This has the drawback of complicating the circuit and reducing the calculation speed.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to convert fixed-point numbers to floating-point numbers and from floating-point numbers to fixed-point numbers using simpler circuits and with improved calculation speed. An object of the present invention is to provide an arithmetic device including a circuit that performs conversion.

(Structure of the Invention) The device of the present invention is an arithmetic device having a function of converting from a fixed point number to a floating point number and from a floating point number to a fixed point number. an exponent calculation circuit that performs a specific operation on the exponent part of a number and outputs the result; a shift circuit that performs a shift on the output of the input register according to the output of the exponent calculation circuit and outputs the result; and a fixed-point number. a first selection circuit that selects the output of the input register or the output of the shift circuit depending on whether the conversion is to a floating point number or from a floating point number to a fixed point number; -1 arithmetic circuit that subtracts 1 from the output of the selection circuit and inverts the bits of each digit of the result and outputs the result; and the output of the first selection circuit or the -1 arithmetic circuit;

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes an input sign register 1, an input exponent register 2, an input mantissa register 3, an exponent calculation circuit 4, a shift circuit 5, a floating/fixed instruction circuit 6, a first selection circuit 7, and a -1 calculation circuit 8. , second selection circuit 9, index generation circuit 10, third selection circuit 1
1, fourth selection circuit 12, output sign register 13,
It includes an output exponent register 14 and an output mantissa register 15.

There are a total of 64 registers on the input and output sides.
Sign registers 1 and 13 have a width of 1 bit, the exponent registers 2 and 14 have a width of 7 bits from the 1st bit to the 7th bit, and the mantissa. part register 3
and 15 have a width of 56 bits from the 8th bit to the 63rd bit.

For floating point numbers, the exponent part is 16 (hexadecimal
10). The decimal point of the mantissa is assumed to be to the left of the most significant bit of the mantissa (therefore, the mantissa represents the part below the decimal point), and is expressed by its absolute value, regardless of whether it is positive or negative, and the sign is the sign bit. Therefore, negative numbers are “1” and positive numbers are “0”
It is expressed as

For fixed-point numbers, the decimal point is assumed to be to the right of the least significant bit (thus always representing an integer), and only the least significant 32 bits are used as significant digits. In the case of a positive number, all digits above it (that is, from the 0th bit to the 31st bit) are 0. Negative numbers are expressed as two's complement numbers, so for example -1 is FF...F (16 hexadecimal Fs), and -2 is FF...FF (15 hexadecimal Fs).
It is represented by one hexadecimal E. Generally, a negative number |X| is expressed as F=-(|X|-1). However, it is assumed that F= represents a number in which all target bits are set to "1".

Therefore, for both floating point numbers and fixed point numbers, the contents of sign registers 1 and 13 are "0" for positive numbers and "1" for negative numbers.

Next, the operation of this embodiment will be explained.

First, we will explain conversion from a fixed-point number to a floating-point number in the case of a positive number.

First, a positive fixed-point number Then, X is stored within the width of the lower 32 bits of the input mantissa register 3.

On the other hand, in the case of conversion from a fixed point number to a floating point number, the floating/fixed instruction circuit 6 outputs "0", thereby causing the first selection circuit 7, the third selection circuit 11 and the fourth selection circuit 11 to The selection circuit 12 selects each input as described later and outputs it to the lower stage.

First, the first selection circuit 7 selects the input mantissa register 3
The output side (line 3000 side) is selected and supplied to one input side of the arithmetic circuit 8 and the second selection circuit 9.

In the case of a positive number, the “0” content of the input sign register 1 is supplied and stored as is to the output sign register 13, and this “0” is added as a selection control signal to the second selection circuit 9. As a result, circuit 9 outputs the output of first selection circuit 7 (line 7000 side)
is selected and supplied to the third selection circuit 11 and the fourth selection circuit 12, respectively.

The third selection circuit 11 selects the output side (line 1000 side) of the exponent generation circuit 10 based on the output "0" of the circuit 6 described above, and supplies and stores it in the output exponent register 14.

Further, the fourth selection circuit 12 selects the input (line 9000L) that enters from the left side of the output from the second selection circuit 9 based on the “0” of the output of the circuit 6 described above, and stores it in the output mantissa register 15. Supply and store. When the fourth selection circuit selects the input on the line 9000L side, the output of the second selection circuit 9 is output so that the lower 32 bits are located at the upper 32 bits of the output mantissa register 15 ( In other words, it is stored shifted to the left by 24 bits).

As a result of the above, the output sign register 13 is “0”
However, the output exponent register 10 stores the output of the exponent generation circuit 10, and the output mantissa register 15 stores X in the upper 32 bits.

As mentioned above, in the case of floating point numbers, it is assumed that the water point is to the left of the topmost part of the mantissa register 15, so that X is currently shifted to the right by 32 bits from the true value. expressed in the form. In order to cancel this, the exponent generation circuit 10 outputs 8 and stores it in the output exponent register 14 as described above (8 determined by 2 ³² =(2 ⁴ ) ⁸ =(16) ⁸ ).

With the above, the conversion of the positive fixed-point number X to a floating-point number is completed (however, the normalization process of the floating-point number is not included in the current target).

Next, the conversion from a fixed point number to a floating point number in the case of a negative number is as follows.

When a negative fixed-point number X is input to the input side,
As mentioned above, the contents of the input sign register 1 are "1", the contents of the input exponent register 2 are all "1", and the mantissa register 3 is F=-(|X| -1) is stored. However, F represents a number in which all bits of the target digit are "1" as described above.

The instruction circuit 6 outputs "0" as described above,
Therefore, the output of input mantissa register 3 is line 3000.
is selected by the first selection circuit 7 and output to the lower stage.

Now, in the case of a negative number, since the content of the input sign register 1 is "1", the second selection circuit 9 selects the output side of the -1 arithmetic circuit 8, which is opposite to the case of the above-mentioned positive number. -1 arithmetic circuit 8 assumes that the input is A, always considers A to be a positive integer, and then calculates 1
This is an arithmetic circuit that subtracts the result and inverts each bit of the result. That is, when the input is A, -1 is output.

As mentioned above, the input to this arithmetic circuit 8 is currently F=(|X|-1), so the output is F=-(||-1)-1=F=-|||=| X|, and the absolute value |X| of the input fixed-point negative number is obtained.

Anything below this is converted to a floating point number in exactly the same way as the positive number described above, and the output sign register 13
The conversion to a floating point number representing a negative number is completed with the value "1".

In this way, in the case of a negative number, it is necessary to calculate the absolute value of the negative number, and in this embodiment, this is performed using the -1 calculation circuit 8.

Next, conversion from floating point numbers to fixed point numbers will be explained. In this case, the sign, exponent, and mantissa of the input floating-point number are stored in input sign register 1, input exponent register 2, and input mantissa register 3, respectively.

First, let the input floating point number be a positive number.
In this case, the contents of input sign register 1 are “0”
As a result, the contents of the register 13 also become "0".

Now, in the case of conversion from a floating point number to a fixed point number, the output of the instruction circuit 6 becomes "1",
As a result, the first selection circuit 7, the third selection circuit 11, and the fourth selection circuit 12 all select the opposite side in the case of conversion from a fixed point number to a floating point number and output it to the lower stage.

As a result, the first selection circuit 7 first selects the output side (line 5000 side) of the shift circuit 5 and outputs it to the lower stage.

The shift circuit 5 shifts the output of the mantissa register 3 to the right by the number specified by the output of the exponent calculation circuit 4 and outputs the result.

On the other hand, the exponent calculation circuit 4 outputs a value obtained by subtracting the contents of the input exponent register 2 (that is, the exponent of the input floating point number) from 14 (E in hexadecimal).

As a result, the shift circuit 5 outputs the input floating point number converted into a fixed point number with the decimal point position to the right of the least significant bit.

For example, the MSB of the mantissa of a floating point number whose exponent part value is 0 represents the bit to the right of the decimal point. In this case, the output of the exponent part calculation circuit 4 is 14 - 0 = 14 As a result, the output of the mantissa register 3 is transferred by the shift circuit 5 to 14×4=
The original MSB is shifted to the right by 56 bits.
It can be seen that the bit position next to the above-mentioned fixed point, which is one bit to the right of the least significant bit, is correctly shifted and converted into a fixed point number. Of course, when a floating point number with an exponent part of 0 is converted to a fixed point number, it underflows and becomes 0, so the exponent part must be a number larger than 0 in order to actually perform an effective conversion.

The output of the circuit 5 converted into a correct fixed-point number in this way is selected by the first selection circuit 7, and as a result of the output of the register 1 being "0", the output of this circuit 7 is selected by the second selection circuit 9. It is selected as is and output to the bottom row.

Since the output of the instruction circuit 6 is "1", the third selection circuit 11 selects the output side of the second selection circuit 9 and supplies and stores it in the register 14.

Similarly, since the output of the instruction circuit 6 is "1", the fourth selection circuit 12 receives an input from the right side of the output from the second selection circuit 9 (line
9000R) side is selected and supplied to and stored in the register 15. When the fourth selection circuit 12 selects the input on the line 9000R side, the output of the second selection circuit 9 is directly supplied to and stored in the register 15 without being shifted.

Through the above operations, in this case, the input floating point number is converted to a fixed point number by the shift circuit 5, which is stored as it is in the output register via each selection circuit, and the floating point number is converted into a fixed point number. The conversion to is completed.

Finally, we will explain conversion from a floating point number to a fixed point number when the input is a negative number.

In the case of a negative number, compared to the case of a positive number described above, only the contents of sign register 1 change to "1", and the contents of exponent register 2 and mantissa register 3 are positive with the same absolute value. The same is true for input floating point numbers.

Therefore, in the same way as described above, the output of the shift circuit 5 is the absolute value of the input floating point number correctly converted into a positive fixed point number.

The first selection circuit 7 selects the output of the shift circuit 5 and supplies it to the -1 arithmetic circuit 8 .

On the other hand, the content “1” of input sign register 1 is
It is supplied and stored in the output sign register 13 and is also supplied as a selection control input to the second selection circuit 9, which controls the circuit 9 to select the output side of the -1 arithmetic circuit 8 and output it to the lower stage.

As mentioned above, the input of the -1 arithmetic circuit 8 is the number |X| obtained by converting the absolute value of the input floating point number into a fixed point number. It performs the operation of inverting the bits of the digit and outputs the result. As a result, ||-1 is output.

Now, for any positive number A =F=-A...(1) There is a relationship between

Using this, | It can be seen that |X| is a fixed-point number converted into a negative number by taking binary complement.

The output of the second selection circuit 9 is as described above.
It is selected by the third selection circuit 11 and the fourth selection circuit 12, and is supplied to and stored in each output register 14 and 15, and by this and the contents of the register 13, it is possible to provide an output correctly converted to a negative fixed-point number. Become.

As described above, in the case of a negative number, the input floating point number is converted by the shift circuit 5 into a fixed point number with the corresponding absolute value, and this is converted into a negative fixed point number (binary complement) by the -1 calculation circuit 8. number), which is converted into the third selection circuit 11 and the fourth selection circuit 11.
It is selected by the selection circuit 12 and is supplied to and stored in the output registers 14 and 15.
3 gives an output converted to a negative fixed-point number.

In this way, when converting a negative floating point number to a fixed point number, an operation is required to convert the absolute value to a negative number (binary complement), but in this example, this is also performed as described above. The same -1 arithmetic circuit 8 used for calculating the absolute value of a negative number is used as is.

Now, through the above operations, this embodiment converts a fixed-point number to a floating-point number, and from a floating-point number to a fixed-point number. Comparing this with the conventional example, as described below, the present embodiment The embodiment has the advantage of being simpler in structure and faster in calculation speed.

A block diagram of a conventional example is shown in FIG.

Circuit elements that are the same as those in this embodiment described above are indicated by the same reference numerals with a dash.

As is clear from FIG. 2, the difference between the conventional example and the above-described embodiment is that an inverting circuit 16' is included, and instead of the -1 arithmetic circuit 8, an A+1 arithmetic circuit 18' is used. The point is that it is used.

When the content of the input sign register 1' is "0" (input is a positive number), the inverting circuit 16' switches to the first selection circuit 7'.
If the output of is output as is to the lower stage without inverting it, and the content of register 1 is "1" (input is a negative number),
This is an inverting circuit with a control function that inverts each bit of the output of the first selection circuit 7' and outputs it to the lower stage.
For this reason, the circuit becomes more complex than an inversion circuit that inverts each bit in a fixed manner, and the time delay increases accordingly.

Further, the A+1 arithmetic circuit 18' is an arithmetic circuit that, when input is A, adds 1 to it and outputs the result.

Now, the conversion operation according to the conventional example shown in FIG. 2 is as follows.

First, if the input is a positive number, both for conversion from fixed point number to floating point number, and vice versa, for conversion from floating point number to fixed point number.
The inverting circuit 16' does not perform inversion, and as is clear from the above description, in this case, the second selection circuits 9 and 9' operate on the side of the -1 arithmetic circuit 8 and the A+1 arithmetic circuit 18', respectively. Since they are not selected, neither of these arithmetic circuits participates in the calculation. Therefore, when the input is a positive number, both the conventional example and the above embodiment perform exactly the same operation, and it is clear from the above description of this embodiment that correct conversion is performed.

Next, when converting from a negative fixed point number to a floating point number, the output of the first selection circuit 7' is F=-(|X|-1) as described above, and this is the output of the inverting circuit 16. ′ is converted as follows.

F=-(||-1)=|X|-1 (see formula (1)) 1 is added to this in the A+1 arithmetic circuit 18', and from |X|-1+1=|X|, it becomes |X|, and the circuit Since the output of circuit 18' is in this case exactly the same as the output of circuit 8 described above, it is clear that the conversion is carried out in exactly the same manner as in the present embodiment described above.

In addition, in the case of conversion from a negative floating point number to a fixed point number, the output of the first selection circuit 7' is the absolute value of the input negative floating point number, as explained in this embodiment. The value |X| is obtained by converting the value into a fixed-point number, and this is the inverting circuit 1.
6' inverts each bit to become ||, and further, in the A+1 arithmetic circuit 18', 1
is added and output as ||+1.

However, ||+1F = - | It is clear that the transformation takes place exactly as in the example.

As described above, the conventional example and this embodiment perform completely similar conversion, but the conventional example includes an inversion circuit 16', and as described above, this circuit 16' is inverted depending on the contents of the input sign register 1'. Since this is an inverting circuit with a control function that controls whether or not to invert, the circuit becomes more complex than an inverting circuit which inverts in a fixed manner, and the time delay increases accordingly. Therefore, it is clear that this embodiment, which does not include this, is superior in terms of hardware simplicity and calculation speed.

Note that the above is one embodiment of the present invention, and the present invention is not limited to the above embodiment.

For example, in this embodiment, the bit widths of the exponent part and the mantissa part are 7 bits and 56 bits, respectively, but this is just an example, and there is no need to be limited thereto.

Further, in this embodiment, the exponent part specifies a power of 16, but this is also an example, and it is also possible to specify a power of 2, for example.

Of course, depending on these, the bit width of each register,
Exponent calculation circuit 4, exponent generation circuit 10 and fourth
It is necessary to appropriately select each parameter used in the selection circuit 12.

(Effects of the Invention) As described above, when the present invention is used, when converting from a fixed-point number to a floating-point number and from a floating-point number to a fixed-point number, it can be used in common with a general arithmetic circuit used for floating-point arithmetic. In this case, by using a -1 arithmetic circuit to convert from a binary complement to an absolute value and from an absolute value to a binary complement, the hardware can be simplified and an arithmetic device with improved processing speed can be provided. .

This makes it possible to improve the performance of the arithmetic device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. In the figure, 1...input sign register, 2...input exponent register, 3...input mantissa register,
4... Exponent calculation circuit, 5... Shift circuit, 6...
...Floating/fixed instruction circuit, 7...First selection circuit, 8
...-1 arithmetic circuit, 9... second selection circuit, 10
...Exponent generation circuit, 11...Third selection circuit, 12
...Fourth selection circuit, 13...Output sign register,
14...Output exponent register, 15...Output mantissa register.

Claims (1)

[Scope of Claims] 1. In an arithmetic unit having a function of converting from a fixed point number to a floating point number and from a floating point number to a fixed point number, an input register that stores information on the number of inputs to be converted; an exponent calculation circuit that performs a specific operation on the exponent part and outputs the result; a shift circuit that performs a shift on the output of the input register according to the output of the exponent calculation circuit and outputs the result; a first selection circuit that selects the output of the input register or the output of the shift circuit depending on whether the conversion is to a decimal point number or from a floating point number to a fixed point number; and the first selection circuit. a -1 arithmetic circuit that subtracts 1 from the output of the output, inverts the bits of each digit of the result, and outputs the result; and a second selection circuit that selects an output of the circuit.