JPH0691549B2 - Loop synchronization circuit - Google Patents

Description

The present invention relates to a loop for correcting loop transmission delay time in a loop type data transmission system for transmitting information between arbitrary data transmission devices connected in a loop. It relates to a synchronous circuit.

[Conventional technology]

Conventionally, this kind of loop synchronization circuit has been composed of a memory, a write address counter, and a read address counter. The read address counter is reset by a transmission frame number pulse and the write address counter is received by a frame timing pulse. It was designed to be reset.

[Problems to be Solved by the Invention] However, the above-described conventional loop synchronization circuit is designed to reset the write address counter with a reception signal frame timing pulse, so that an error occurs in the reception signal, When the received second frame timing pulse is abnormally reproduced, the write address counter is frequently reset and only the vicinity of the address "0" of the memory is rewritten, and most of the rest remains past data written. Become. Therefore, there is a problem that apparently normal data may be output in the received signal even though the received signal is abnormal.

[Means for Solving the Problems]

In order to solve such a problem, the loop synchronization circuit of the present invention comprises a memory, a write address counter, and a read address counter, and resets the read address counter with a transmission signal frame timing pulse, When the loop transmission delay time is corrected by resetting the address counter with the received signal frame timing pulse, the received signal frame timing pulse and the write address counter overflow pulse, which both have a periodic signal that coincides in time under normal conditions, when the loop transmission delay time is corrected And are input to the AND circuit, and the output of this AND circuit is input to the mono-multi circuit to generate a pulse signal for the read time of the read data of the read address counter from the mono-multi circuit. Read from the memory according to the output It is obtained so as to secure the "0" or "1" data.

[Action]

Therefore, in the present invention, the AND signal is used for ANDing the frame timing pulse of the received signal and the overflow pulse of the write address counter, and the period of the output pulse is monitored by the mono-multi circuit 5. It is possible to determine whether the cycle of the frame timing pulse is normal or abnormal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. The drawing is a circuit diagram showing an embodiment of a loop synchronization circuit according to the present invention. In the figure, 1 is a memory circuit, 2
Is a write address counter circuit, 3 is a read address counter circuit, 4 and 6 are AND circuits, 5 is a mono-multi circuit,
7 and 8 are OR circuits.

That is, this embodiment is different from the above-mentioned conventional example in that it operates by the AND circuit 4 for inputting the received signal frame timing pulse RDF and the overflow pulse of the write address counter circuit 2 and the output of this AND circuit 4. The AND circuit 6 is controlled by the output of the mono-multi circuit 5 to fix the read signal from the memory circuit 1, that is, the read data to “0”.

The loop synchronizing circuit configured in this way is a write address counter circuit 2 which performs a reset operation with a received signal frame timing pulse RDF or its own overflow pulse.
The received count RD is written to the memory circuit 1 using the count value of the address as the address, and the send count frame timing pulse TD
The loop transmission delay time is corrected by setting the contents of the memory circuit 1 whose address is the count value of the read address counter circuit 3 which is reset by F or its own overflow pulse as the transmission signal TD. At this time, the count capacities of the write address counter circuit 2 and the read address counter circuit 3 are set equal to the number of frame bits of the transmission / reception signal. Therefore, the normal cycle of the received signal frame timing pulse RDF and the generation cycle of the overflow pulse are equal and simultaneous.

From the above, received frame number timing pulse RD
Whether the cycle of the received signal frame timing pulse RDF is normal by ANDing the F and the overflow pulse of the write address counter circuit 2 with the AND circuit 4 and monitoring the cycle of the output pulse with the mono-multi circuit 5 ,
It is possible to determine whether it is abnormal. That is,
The mono-multi circuit 5 outputs the reception signal frame timing pulse RDF in a normal cycle, and when the normal cycle and the overflow pulse generation cycle match, the AND circuit 6
An "H" level signal is sent to one of the input terminals at least until the read address counter circuit 3 completes reading data from the memory circuit 1. If the received signal frame timing pulse RDF is output in an abnormal cycle, the mono-multi circuit 5 AND
No "H" level signal is output to the circuit 6.
Therefore, when the output signal of the mono-multi circuit 5 and the read signal from the memory circuit 1 are ANDed by the AND circuit 6, when the cycle of the reception frame timing pulse RDF is abnormal, the transmission signal TD is set to "0". Can be fixed.

Although the transmission signal TD is fixed to "0" in the above embodiment, it may be fixed to "1".

〔The invention's effect〕

As described above, the present invention monitors the period of the received signal frame timing pulse and fixes the transmitted signal to “0” or “1” when an abnormality occurs in the period, thereby transmitting the signal. In addition, it is possible to prevent the apparently normal data from being output.

[Brief description of drawings]

The drawing is a circuit diagram showing an embodiment of the present invention. 1 ... Memory circuit, 2 ... Write address counter circuit, 3 ... Read address counter circuit, 4,6 ... AND circuit, 5 ... Monomulti circuit, 7,8 ... OR circuit.

Claims (1)

[Claims] 1. A memory, a write address counter, and a read address counter, wherein the read-out counter is reset by a transmission signal frame timing pulse, and the write address counter is reset by a reception signal frame timing pulse. Thus, in a loop synchronization circuit that corrects the loop transmission delay time, a reception signal frame timing pulse and a write address counter overflow pulse, which both have a periodic signal that temporally coincides with each other in a normal state, are input to an AND circuit, and the AND circuit Input to the mono-multi circuit to generate a pulse signal for the read-out time of the read data of the read address counter from the mono-multi circuit, and read from the memory according to the non-output of the mono-multi circuit. Data is "0" or Loop synchronization circuit, characterized in that it comprises means for fixing to 1. ".